JPH04196135A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To simply form a gate electrode whose gate length is short and to increase a current cutoff frequency by a method wherein a second mask member which has been applied to a sidewall on a gate formation region in a first mask member is used as a dummy gate as it is. CONSTITUTION:An active layer 1a, an SiN film 2 and a resist pattern (a first mask member) 3 are formed on a semiinsulating GaAs substrate 1; after that an SiO2 film (a second mask member) 4 is deposited on the film 2 and the pattern 3. After that, e.g. by performing an anisotropic etching operation from the upper part by using a gas such as CF4 or the like by an RIE method, the film 4 is etched back so as to leave only the film 4 which has been applied to a sidewall on a gate formation region in the pattern 3; a dummy gate (g) is formed. Since a low-resistance region can be formed on the side of a source in a self-aligned manner with an electrode G, it is possible to enhance a current cutoff frequency and a transconductance without reducing a drain-gate withstand voltage. Since the electrode G whose gate length is short can be formed, the productivity of the title transistor is enhanced. Since the electrode G is formed by a plating method, the reliability of the title transistor can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a field-effect transistor, particularly for high-frequency operation used in microwave integrated circuits (formerly C) and monolink microwave integrated circuits (MMIC). This invention relates to a method for manufacturing a field-effect transistor aimed at

[Conventional technology]

Old C and MMIG made of GaAs and intended for high frequency operation in the microwave band are constructed by combining active elements such as field effect transistors and passive elements such as resistors and capacitors. The operating frequency of old C and MMIC is 2GI
Since it is extremely high, exceeding Iz, the field effect transistor used here is required to have high speed.

Therefore, the current cutoff frequency (f
], ) Various efforts have been made to improve the results. Specifically, the transconductance (g)
In order to increase
Ion implantation is performed using the letter-shaped dummy gate as a mask to lower the resistance of the source formation region and the drain formation region in a self-aligned manner with respect to the gate electrode.

Further, in order to form an active layer and a low-resistance layer by evitaginal growth, a υj electric pole mobility transistor IIEMT) was used in which the gate formation region had a recessed structure.

[Problem to be solved by the invention]

However, if the resistance of the source formation region and drain formation region, which are located symmetrically on both sides of the gate electrode, is lowered by using a dummy gate I, the low resistance region on the source side becomes self-aligned with the gate electrode. This is desirable from the point of view of reducing the source resistance, but at the same time, the low resistance region on the drain side is also formed close to the gate electrode, which deteriorates the ■-■ characteristics and reduces the drain conductance (g d). Deteriorate. In particular, because the gate-drain breakdown voltage is low, it cannot be used in power 1'ETs that operate in a high frequency region and flow large currents.

Further, if a recessed structure is used, there is a problem that the uniformity of the device is impaired and the yield is reduced.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a manufacturing method that can easily form a gate electrode with a short gate length and can manufacture a field effect transistor with a high f.

[Means to solve the problem]

In order to solve the above object, the present invention forms a first mask member (for example, a resist film) in which the semiconductor substrate is exposed in the gate formation region and the source formation region of the semiconductor substrate, and converts this first mask member into a second mask member. Mask member (e.g. 5IO2
) and by etching back this second mask member, the second mask member on the source formation region is removed and the sidewall of the first mask member is covered with (=I
By leaving the second mask member with =ff to form a dummy gate on the gate formation region, and implanting impurities into the semiconductor substrate using the dummy gate and the first mask member as masks, the source After forming a low-resistance region in the formation region for a couple of steps, after removing the first mask member, only the head of the dummy gate is exposed and a third mask member (for example, a resist film) is placed on the surface. forming an opening in which the semiconductor substrate is exposed by removing the dummy gate on the gate formation region of the third mask member; a step of covering the exposed opening with a gate metal, a step of forming a gate pattern on the gate metal (for example, a metal film) having an opening wider than the opening in which the conductor substrate is exposed in step 16, and supplying power to the gate metal. A step of forming a gate electrode by growing a conductive portion in the opening of the gate pattern using a plating method, and a step of removing the gate metal, the gate pattern, and the third mask member that are not in contact with the gate metal. It consists of:

[Effect]

According to the method for manufacturing a field effect transistor according to the present invention, since the second mask member attached to the side wall of the first mask member on the gate formation region becomes a dummy gate, the second mask member is formed on the first mask member. The gate length is proportional to the film thickness of the second mask member. Therefore, if this film thickness is made submicron, a gate pattern with a submicron gate length can be formed. In addition, since power is supplied to the gate metal formed on the gate pattern to plate the conductive member, a field effect transistor having a gate length of a submicron can be efficiently manufactured.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in the explanation, the same number 7] is used for the same elements,
Duplicate explanations will be omitted.

First, a method for manufacturing a field effect transistor according to an embodiment will be explained. FIG. 1 is a process diagram showing a method of manufacturing the above-mentioned field effect transistor.

First, Si ions are implanted onto a cliff-insulating GaAs substrate 1, and then the ion implanted portion is activated by annealing to form an active layer [a] on the substrate surface.

Furthermore, SiN was added to the surface using plasma CVD technology.
The film 2 is grown to a thickness of, for example, 800 angstroms (FIG. 2(a)). Note that the active layer 1a may be formed by an epitaxial growth method.

Next, using photolithography technology, a resist pattern (first mask system) 3 having openings on the source formation region and gate formation region of the GaAs substrate 1 is formed with a 1.0
The resist pattern 3 and the SiN film 2 exposed from the openings are then coated with a sputtering method or an ECR-CVD method that allows low-temperature treatment to an extent that the resist pattern 3 is not destroyed. A SiO □ film (second mask portion I() 4) is deposited using the same method (FIG. 4(b)).

Thereafter, for example, by anisotropic etching from above using a gas such as CF4 by RIE, the Si○2 that has formed on the sidewall of the gate formation region in the resist pattern 3 is removed.
Etch back the SiO2 film 4 so that only the film 4 remains,
A dummy gate g is formed. Next, this dummy game-1-
Si ions are implanted obliquely from the drain side at an angle of about 7 degrees to 10 degrees using the resist pattern 3 and the resist pattern 3 as a mask to form a source region 1c with low resistance in self-alignment with the dummy gate 1-g ( Same figure (C)).

The acceleration energy of S1 ions is 90 keV, the dose melon can be used at about 4 x 1013 cm-2, and the distance between dummy game 1-g and source region 1s can be changed by changing the irradiation angle of Si ions. .

After that, the unnecessary part of the dummy gate g (GaAs substrate)
S i formed on a region other than the upper gate formation region
By removing the O2 film 4) and resist pattern 3 and performing annealing, the implanted Si ions are activated. Thereafter, using photolithography technology, a source electrode S and a drain electrode are formed in ohmic contact with the GaAs substrate, and again a resist film (third mask portion tA) 5 is formed with a film thickness of about 1.5 μm. (see figure (d)
)). The upper surface is substantially flattened by this resist film 5.

Thereafter, this resist film 5 is etched by RIE using a gas such as 02 until the top of the dummy gate g is exposed (FIG. 4(e)).

Next, the dummy gate g and the SiN film 2 in contact with the dummy gate g are removed by wet etching using buffer 1-HF or the like, and an opening 5g for the resist film 5 is formed on the gate formation area. ((f) in the same figure).

Further, the surface of the resist film 5 and the sidewall and bottom of the opening 5g where the GaAs substrate 1 is exposed are covered with a gate metal layer 6, and a resist pattern (gate pattern) 7 having an opening overlapping the opening 5g is formed on the gate metal layer 6. ((g) in the same figure). As the gate metal layer 6, T i /
It can be formed with a film thickness of about 1500 angstroms using a three-layer structure metal such as Pt/Au using a vapor deposition method or a sputtering method. Further, the resist pattern 7 is formed by a first lithography technique using a resist film that forms a lower opening g wider than the opening 5g.

Next, the resist pattern 7 is used to form a gate metal layer 6.
By supplying power as a cathode, Au metal (conductive member) is grown with a thickness of about 1.5 μm within the openings 5g and 7g using a metal key to form gates: i-poles G (same as Figure (h)).

Finally, after the resist pattern 7 is removed by RIE using O2, the gate metal layer 6 is removed by ion milling, and the resist film 5 is further removed by RIE using O2 (see the figure). 1)〉.

The FET is completed through the following two steps.

In this way, since a low resistance region can be formed on the source side in self-alignment with the gate electrode G, g 1 f7 can be improved without reducing the drain-gate breakdown voltage, and the gate G and source region ]S The interval between can be set with good viscosity.

Furthermore, unlike electron beam (EB) exposure, a gate electrode having a gate length on the submicron order can be formed only by optical exposure without directly drawing on the wafer, so productivity can be improved.

Furthermore, since the gate electrode of the FET manufactured according to this example is formed by a plating method, it is difficult to fall down, and the reliability of the FET is also 12j.

Note that the present invention is not limited to the above embodiments.

For example, in this embodiment, if the gate metal layer 6 and the conductive member are made of the same material, or if the uppermost layer of the gate metal layer 6 is a material with the same or lower ionization tendency, it can be used as the conductive member. Therefore, if Au is the uppermost layer of the gate metal layer 6, A1 can be used as the conductive member.

Furthermore, although GaAs is used as the substrate, GaAs
It is not limited to s.

〔Effect of the invention〕

In the method for manufacturing a field effect transistor according to the present invention, a dummy gate 1 attached to the side wall of the first mask portion I is formed, and a source region is formed using this dummy gate, so that an electric field operating at a high frequency Effective transistors can be manufactured with high productivity.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing a method of manufacturing a field effect type L transistor according to an embodiment of the present invention. S...source electrode, D...drain electrode, G...gate electrode,] -GaAs substrate, 2-8iN film,
3. Resist pattern (first mask member), 4.
・5102 film (second mask member), 5・resist film (
(third mask member), 6... gate metal layer, 7 resist pattern (gate pattern). Representative Patent Attorney Yoshiki Hasejo
Mountain 1) Row - FET manufacturing filtration method Figure 1

Claims (1)

[Scope of Claims] A step of forming a first mask member in which the semiconductor substrate is exposed in a gate formation region and a source formation region of the semiconductor substrate, and covering the first mask member with a second mask member; By etching back the mask member of 2,
removing the second mask member on the source formation region and leaving the second mask member attached to the sidewall of the first mask member to form a dummy gate on the gate formation region; forming a low resistance region in the source formation region by injecting impurities into the semiconductor substrate using the dummy gate and the first mask member as masks; and after removing the first mask member. forming a third mask member on the surface by exposing only the head of the dummy gate; and forming an opening in which the semiconductor substrate is exposed by removing the dummy gate into a gate formation region of the third mask member. forming a gate pattern on the gate metal; a step of covering the surface of the third mask member and the opening where the semiconductor substrate is exposed with a gate metal; and forming a gate pattern having an opening wider than the opening where the semiconductor substrate is exposed with a gate metal. a step of forming a gate electrode by growing a conductive member in the opening of the gate pattern by plating by supplying power to the gate metal; A method for manufacturing a field effect transistor, comprising the step of removing the pattern and the third mask member.