JPS6266682A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce a series parasitic resistance by forming a semiconductor operating layer on a substrate, forming a heat resistant gate electrode thereon, thermally feeding a resist thereon to cover as for as the side of the gate electrode, and forming a high density impurity region with the resist as a mask, thereby decreasing a contacting resistance. CONSTITUTION:An operating layer 10 is formed by ion implanting on a GaAs substrate 9. A high heat resistant gate electrode (e.g., WSi) is formed by reactive ion beam etching with CF4 as reaction gas on the substrate 9 with a resist pattern 12 formed by lithography as a mask. The resist on the gate electrode is thermally fed to form a spherical shape for coating to the side of the electrode, and high density regions 13, 14 are formed by an ion implanting method with the pattern 12 and the gate electrode 11 as masks. After removing the resistor 12', a source electrode 15 and a drain electrode 16 are formed to obtain an MESFET.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a Schottky gate field effect transistor that can operate at ultra high speed.

(Prior art and its problems) Schottky gate field effect transistor (hereinafter MESF)
(abbreviated as ET) has been praised as an excellent amplification or oscillation element, especially at ultra-high frequencies. Also,
It is well known that it is excellent as a basic component of integrated circuits operating at ultra-high speeds.

The 114-structure MESFET most commonly used in the past is as shown in FIG. Here, 1 is a high resistivity or semi-insulating semiconductor crystal substrate, and 2 is a conductive semiconductor crystal layer, which is usually called an active layer. 3 is a Schottky gate electrode, and 4.5 is a source and drain electrode each having ohmic characteristics. The carrier concentration Nd and thickness a of this active layer have a relationship with the pinch-off voltage Vp of the MESFET as shown in the following first equation.

However, vb is the built-in voltage, ε is the dielectric constant of the semiconductor crystal, and q is the charge volume Vp is given from the circuit design requirements. is determined.

One of the drawbacks of the conventional structure, such as that shown in Figure 1, is that the gate 3
and the series parasitic resistance value (Rs) between the source 4 or the gate 3 and the drain 5 is large, so that a sufficiently large mutual conductance value of 2m cannot be obtained. Another problem is that the noise characteristics deteriorate due to the large gate-source series resistance.

In particular, when the absolute value of the pinch-off voltage Vp is small, or when it is normally off (Vp>0), as is clear from equation (1), Nd or a must be a small value, so the series resistance between the gate and source is becomes a larger value. In addition, when the active layer 9 is made of GaAs crystal, there are high density surface states in the crystal surface area between the gate and the source and between the gate and the drain, so that the surface potential is almost fixed. Since a depletion layer is formed near the surface of the semiconductor crystal, the series resistance between the gate and the source becomes even larger, which is an extremely serious problem, especially in normally-off type devices.

Therefore, in order to solve these shortcomings, many innovations and
Efforts are being made. FIGS. 3 and 41 are device cross-sectional views for explaining conventional device structures devised to reduce Rs. In FIG. 3, the active layer 6.8 between the gate and source and between the gate and drain is made thicker than the active layer 7 directly under the gate electrode. In this method, it is necessary to determine the thickness of the active layer 7 and the carrier density to satisfy the conditions of the tl) equation, but considering this stepped structure, the thickness of the active layer 7 must be adjusted by etching, etc. It is difficult with current technology to control accurately and with good reproducibility.

Further, in the structure shown in FIG. 4, a reduction in Rs is achieved by arranging the source electrode, drain electrode, and gate electrode close to each other with an interval of 0.5 μm or less. However, manufacturing a device with this structure requires extremely high precision alignment or a special method such as a self-alignment method.

(Means and effects for solving the problems) The present invention has been made in view of the problems in the conventionally proposed methods, and is directed to a Schottky gate field effect transistor that can reduce the series parasitic resistance Rs. A manufacturing method is provided.

The method for manufacturing a field effect transistor of the present invention includes a step of forming a first semiconductor active layer on a substrate, a step of forming a heat-resistant gate electrode on the first semiconductor active layer, and a step of forming a resist on the gate electrode. After heating and fluidizing it to form a bowl-shaped shape that covers the sides of the gate electrode, a high-concentration impurity region is formed in a self-aligned manner by ion implantation using the resist as a mask, and then the resist is removed to form the gate electrode. It is characterized by including the step of forming.

(Example) The present invention will be explained in detail below with reference to the drawings. Figure 1: Prisoner (
E) is a diagram illustrating a method for manufacturing a Schottky gate field effect transistor.

First, as shown in the figure, ions that can become impurities (for example, S+) are implanted into the surface of a semi-insulating semiconductor substrate 9 made of GaAs by an ion implantation method to form an active layer IO. As shown in FIG. 9B, a highly heat-resistant gate electrode (for example, WSi, 5,000 nanometers) is formed on the surface of the substrate 9 (the surface of the active layer IO) using an acid resist (for example, WSi, 5,000 nanometers) formed by ordinary 7-otolithography. For example, AZ1400-27
) It is formed by reactive ion beam etching using pattern 12 as a mask and using CF as a reactive gas.

Next, the resist on the gate electrode is heated and fluidized at 200'G to form a bowl-shaped shape that covers the sides of the gate electrode, as shown in FIG. High concentration impurity region 13.1 is formed by ion implantation using electrode 11 as a mask.
form 4. ((D) in the same figure) Furthermore, Regis) 12'
After removing the source electrodes 15, the source electrodes 15,
A drain electrode 16 is formed. ((E) of the same figure) (Effects of the Invention) According to the present invention, the distance between the Schottky gate electrode, the source electrode, and the drain electrode can be reduced, and the portions other than the Schottky gate electrode region are doped with high-concentration impurities: il'l.
Since the contact resistance can be reduced and the series parasitic resistance Rs can be made small, a large resistance of 2 m can be obtained, so ultra-high speed operation can be expected.

Furthermore, according to the production method of the present invention, high quality F can be easily produced.
Since ET can be created, it has a great effect on improving productivity.

[Brief explanation of drawings]

FIGS. 1<A) (B) (C) ■) (E) are cross-sectional structural views showing the manufacturing process of the Schottky gate field effect transistor of the present invention. FIGS. 2, 3, and 4 are cross-sectional views of conventional Schottky gate field effect transistors. 1.9...Semiconductor substrate 2,10,13.1
4... Active layer 3.11... Schottky gate electrode 4, 15... Source electrode 5.16
......Drain electrode 6...Gate-source region 7...Channel region under the gate electrode 8...Gate-drain region 12...
...Resist 12'...Resist agent after heating and flow Patent attorney Satoshi Tsukasa Kami 3, Cuff', (
3“

Claims (3)

[Claims] (1) A step of forming a first semiconductor active layer on a substrate, a step of forming a highly heat-resistant gate electrode on the first semiconductor active layer, and a step of heating and fluidizing the resist on the gate electrode to form a gate electrode. After creating a bowl-shaped shape that covers the sides,
A method for manufacturing a field effect transistor, comprising the steps of forming a high concentration impurity region in a self-aligned manner by ion implantation using the resist as a mask, and then forming a gate electrode by removing the resist. (2) The method for manufacturing a field effect transistor according to claim 1, wherein the heating temperature of the resist is set higher than at least a post-bake temperature. (3) The method for manufacturing a field effect transistor according to claim 1, wherein the thickness of the resist is at least equal to or greater than the thickness of the heat-resistant gate electrode.