JPH039533A - Schottky gate type field effect transistor - Google Patents

Abstract

PURPOSE:To effectively restrain narrow channel effect by arranging a second conductivity type layer in a substrate region adjacent to the gate width direction of a conductive active layer. CONSTITUTION:A first conductivity type active layer 2 is formed on a semi- insulative semiconductor substrate 1, and a Schottky gate electrode 3 is formed so as to cross the active layer 2. Second conductivity type layers 5, 6 are arranged in a substrate region adjacent to the gate width direction of the active layer 2. That is, when potential distribution of a substrate region adjacent to the active region 2 is viewed from the active layer 2 regarding the gate width direction under a gate electrode 3, a large potential barrier of a PN junction is formed at a boundary part of the active layer 2. Thereby the influence of electric potential upon the active layer 2 from a part protruding from the active region of the gate electrode 3 is relieved, and narrow channel effect is effectively restrained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a Schottky gate field effect transistor (MESFET) constructed using an active layer formed on a semi-insulating semiconductor substrate. Regarding.

(Prior Art) As semiconductor devices become faster and more highly integrated, devices are becoming increasingly finer. The miniaturization of devices has various effects on device characteristics, but in field effect transistors (FETs),
Typical effects of device miniaturization on characteristics are short channel effects and narrow channel effects.

MESFETs using Schottky gate electrodes also have short channel effects and narrow channel effects. MES
Although various countermeasures against the short channel effect of FET have been proposed, the reality is that little consideration has been given to the narrow channel effect.

The narrow channel effect of MESFETs is largely influenced by the fact that the gate electrode is patterned to extend outward from the active layer region in the gate width direction due to the need for margin in the lithography process and the need for electrode extension. This is because the potential of the portion of the gate electrode protruding from the active layer region affects the active layer. From this point of view, as a method for suppressing the narrow channel effect of MESFETs, a method has been proposed in which an insulating film is interposed between the gate electrode and the substrate in the region where the gate electrode protrudes from the active layer region (1982).
January 21, IEICE Technical Research Report Vol. 8
6 No. 305).

However, with this method, a step is formed in the gate width direction of the gate electrode, so it is not sufficient to suppress the narrow channel effect, especially when the gate width is small, and the process is complicated. There was a problem that the coverage of the electrode metal also deteriorated.

(Problems to be Solved by the Invention) As described above, conventionally there has been no effective method for suppressing the narrow channel effect in MESFETs.

The present invention has been made in view of the above points, and an object of the present invention is to provide a MESFET that can effectively suppress narrow channel effects.

C Structure of the Invention] (Means for Solving the Problems) The present invention provides an electric field in which a first conductivity type active layer is formed on a semi-insulating semiconductor substrate, and a Schottky gate electrode is formed across this active layer. The effect transistor is characterized in that a second conductivity type layer is provided in a substrate region adjacent to the active layer in the gate width direction.

(Function) According to the present invention, when looking at the potential distribution from the active layer to the adjacent substrate region in the gate width direction under the gate electrode, a large potential barrier is formed at the boundary of the active layer due to the pn junction. . This reduces the influence of potential on the active layer from the portion of the gate electrode protruding from the active layer region, and effectively suppresses the narrow channel effect. Furthermore, unlike the method of interposing an insulating film, there is no need to consider the coverage of the gate electrode metal even if the gate width is small.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a), (b), and (e) show the G a of one embodiment.
Plan view showing A s M E S F E T and its A
-A' and BB' sectional views. Semi-insulating GaAs
, an n-type active layer 2 is formed on the l-plate 1 by ion implantation, and a Schottky gate electrode 3 made of, for example, a tungsten nitride (WN) film is formed on and across the n-type active layer 2. .

An insulating film 4 is formed on the side wall of the gate electrode 3, and an n-type layer 5.6 is formed by high-concentration St ion implantation using the gate electrode 3 and the insulating film 4 as a mask. Ohmic electrodes 7 and 8 are AuGe/Au
It is formed by a membrane. A p-type layer 9 is located in the region indicated by the broken line in FIG. 1(a), including the region where the gate electrode 3 is provided.
is formed. The p-type layer 9 is an nJ5 layer 2 which is an active layer.
It has a lower impurity concentration. Further, when viewed in a cross section in the gate width direction (FIG. 1C), the p-type layer 9 is located under the gate electrode 3 in the substrate region adjacent to the n-type active layer 3 region.

To explain the specific manufacturing process, first, semi-insulating GaAs
A resist pattern having a window is formed in the p-type layer forming region of the Mi plate 1 shown by the broken line in FIG.
A p-type layer 9 is formed by ion implantation at +2/am2.

The p-type layer 9 may be formed using other methods such as solid phase diffusion. Next, a resist pattern for forming an active layer is formed, and Si ions are implanted at an acceleration voltage of 25 keV and a dose of R6 x 10''/L:rn2, for example, to form an active layer of nJ.
e! An active layer 2 is formed. After removing the resist pattern, a WN film of, for example, 3,000 layers is deposited by sputtering, and patterned by reactive ion etching to form the gate electrode 3. Next, an insulating film 4 is deposited on the sidewalls of the gate electrode, a resist pattern with windows is formed in the element formation region including the source and drain regions, and this resist pattern is combined with the gate electrode 3 and sidewall insulating film 4.
For example, using Si as a mask with an acceleration voltage of 80 keV,
Ion implantation is performed at a dose of ffi I x 10''/an2 to form n+ type layers 5 and 6.Finally, A u G e
/ Source and drain ohmic electrodes 7 and 8 are formed using the Au film. Note that activation of impurities by ion implantation is performed by heat treatment at 820° C. for 20 minutes, for example, after performing ion implantation to form high concentration layers of the source and drain.

FIG. 2 shows the surface potential distribution in the cross section in the gate width direction of the MESFET according to this embodiment, that is, the cross section in FIG. 1(c). As is clear from the figure, a large potential barrier is formed at the boundary of the active layer 2 due to the pn junction. As a result, the influence on the active layer 2 due to the potential of the portion of the gate electrode 3 protruding from the active layer region is suppressed, and the narrow channel effect is suppressed. Further, the suppression of this narrow channel effect is considered to be due to the potential barrier between the p-type layer and the Schottky electrode. In other words, the narrow channel effect is suppressed due to the fact that the extension of each depletion layer from the potential barrier due to the pn junction and the p-Schottky junction is small.

FIG. 3 shows the results of the 4P1 determination of the relationship between the threshold voltage VLh and gate width Wg of the MESFET according to this example.
This is shown in comparison with a conventional example that does not have a p-type layer.

This is data for a MESFET with gate length Lg=0.5 μm. As is clear from the figure, in the conventional example, the average value of the threshold voltage vth changes greatly in the positive direction as the gate width becomes smaller, whereas in this example, the threshold voltage vth changes significantly even when the gate width becomes about 1 μm. voltage f
The average value remains the same as for large gate widths. In contrast to the conventional example in which variations in threshold value increase as the gate width becomes smaller, this embodiment does not exhibit such large variations.

As described above, according to this embodiment, the narrow channel effect is suppressed by providing the p-type layer in the substrate region in the gate width direction adjacent to the n-type active layer.

In order to suppress the narrow channel effect, the impurity concentration of the p-type layer is particularly important. As a result of trial calculation of this impurity concentration, when the n-type active layer is used as a channel region, I
The range of 0''/cm3 to IX1018/cm3 is good, especially lX1015/cII+3 to 1x10d/c
m' is good. By setting the impurity concentration of the p-type layer within this range, the narrow channel effect can be suppressed to a negligible level.

The present invention is not limited to the above embodiments.

For example, in the example, a p-type layer was formed over the entire region where the gate electrode was provided, and then an n-type active layer was formed so as to partially overlap this p-type layer. On the other hand, as shown in FIG. 4', p-type layers 93.9□ are formed on both sides of the n-type active layer 2 in the gate width direction, avoiding the region where the n-type active layer 2 is formed. It's okay. In this way, since the ion implantation into the n-type active layer region is only the ion implantation of n-type impurities, damage caused by ion implantation can be reduced and excellent Schottky gate characteristics can be obtained. Further, in the embodiment, the p-type layer is provided over the entire gate electrode in the region where the gate electrode protrudes from the active layer region, but the p-type layer does not necessarily have to be provided over the entire gate electrode. In other words, the influence on the active layer from the gate electrode portion that protrudes largely from the active layer becomes smaller as the distance from the active layer increases, so if the protrusion width of the gate electrode is large, the p-type layer should be provided in a narrower range. You can also obtain sufficient effects by doing this. Furthermore, the p-type layer can be formed so as to cover the entire l-type active layer.

Furthermore, in the example, G a A s M E S F E
Although T has been described, the present invention can also be applied to MESFETs using other semiconductor materials such as Si or Ge. Furthermore, even when the active layer is a p-type layer, the present invention is effective by making the p-type layer shown in the embodiment an n-type layer.

[Effects of the Invention] As described above, the present invention provides a MESFE in which the narrow channel effect is suppressed by providing the second conductivity type layer in the radix region adjacent to the first conductivity type active layer in the gate width direction.
You can get T.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) show G a A of one embodiment of the present invention.
A +1 plane view showing s M E S F E T and its AA' and BB' cross-sectional views, Figure 2 is a diagram showing the potential distribution in the cross section in the gate width h' direction, and Figure 3 The figure also shows the result of determining the relationship between the threshold voltage and gate width of the MESFET in comparison with the conventional example.
It is a sectional view showing ET. 1... Pato insulating GaAs substrate, 2... n-type active layer,
3... Schottky gate electrode, 4... Insulating film, 5
゜6...N゛-type layer 7, 8...Ohmic electrode, 9.
...p-type layer.

Claims (2)

[Claims] (1) In a field effect transistor in which a first conductivity type active layer is formed on a semi-insulating semiconductor substrate and a Schottky gate electrode is formed across the active layer, a first conductivity type active layer is formed in a substrate region adjacent to the active layer in the gate width direction. A Schottky gate field effect transistor characterized by having two conductivity type layers. (2) The Schottky gate field effect transistor according to claim 1, wherein the second conductivity type layer has an impurity concentration lower than that of the active layer.