JPS62291066A - Manufacture of vertical field-effect transistor - Google Patents

Abstract

PURPOSE:To render a process more simple and characteristics of products more stable as well as elements more compact by forming a impurity area of a conductivity opposite to that of a semiconductor substrate and taking other measures, thereby performing an ultra high energy ion implantation using a mask for etching or a residual polysilicon as the mask. CONSTITUTION:The surface of semiconductor substrate 1 has stepped portions in its thickness to grow an oxide film 2 and permits the stepped portions to grow polysilicons 3 on the oxide film 2. After that, the polysilicons 3 are treated by etching mainly at around thicker portions of film thickness of the oxide film 2 according to a technology of photo lithography. And then, an ultra high energy ion implantation 4 is carried out by using as mask 15 for etching and a residual polysilicon 3 as the mask to form a first impurity area 5 of a conductivity type opposite to that of the substrate 1. In addition, a second impurity area 6 of a conductive type that is identical to that of substrate 1 is formed in the first impurity area 5 by using the above residual polysilicon 3 as well as portions having the thicker portions of film thickness of the oxide film 2 as the mask to obtain a vertical type field effect transistor having a source 6 and gate 14 on the surface of semiconductor substrate 1 as well as a drain 9 on the rear face of its substrate.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a vertical M field effect transistor (hereinafter referred to as a vertical M
It is written as OS I'I' ET. ), and particularly relates to simplification of processes, stabilization of product characteristics, and miniaturization of devices.

[Conventional technology]

A conventional protein field effect transistor has been manufactured by a manufacturing method as shown in FIG. First, as shown in FIG. 3(a), an oxide film 2 is grown on a semiconductor substrate 1, and a resist 10 is formed using photolithography technology as shown in FIG. 3(b). 2 to form a P″ base region 11 (FIG. 3(C)).
As shown in Figure (d), P-paste region 1 after oxide film formation
1- Leaving the oxide film 12 on the substrate, grow polysilicon as shown in FIG. Using as a mask, perform 10 to 100 ion implantations.
A P base region 5 and an N+ source region 6 are formed by ion implantation of about keV (impurity peak depth: 500 to 3000 A), and a spacing insulating film 7 is further formed as shown in FIG. 3(f). A window is opened using photolithography technology, and a source aluminum electrode 8 is formed.

[Problem that the invention seeks to solve]

In the conventional manufacturing method of vertical field effect transistors described above, the base region is formed using low-energy ion implantation using polysilicon as a mask, so the impurity peak depth is 500 to 3000, which is a back-up.・If an impurity region of the same type as the base region is first formed in the gate region, the base region will not be connected and the withstand voltage will be reduced. Also, when forming an impurity region between the base regions, It had the disadvantage that there were a lot of

In addition, since a gap occurs between the P-base regions, the process becomes complicated.Furthermore, since the P-base and P-pace are formed separately, if misalignment occurs, the channel It had the disadvantage that the parts overlapped and the characteristics were unstable.

[Failure to solve the problem]

In the manufacturing method of vertical A40SFB'l', the present invention uses polysilicon as a mask to form a P space region through an oxide film using ultra-high energy ions (for example, 0.1 to 5 MeV), and vice versa. , N+ source regions are formed using polysilicon and oxide films as masks.

A method for manufacturing a vertical field effect transistor of the present invention includes a method for manufacturing a vertical field effect transistor having a source and a gate on the front surface of a semiconductor substrate and a drain on the back surface.
A process of growing an oxide film on the surface of a semiconductor substrate with steps in thickness, a process of growing polysilicon on top of the oxide film, and a process of etching the polysilicon mainly in the thick oxide film using photolithography technology. In the process, ultra-high energy ion implantation is performed using an etching mask and the remaining polysilicon as a mask to form a first layer of conductivity type opposite to that of the semiconductor substrate.
forming an impurity region; and further forming a second impurity region of the same conductivity type as the semiconductor substrate using the remaining polysilicon and the thick oxide film as a mask in the first impurity region. It is characterized by

〔Example〕

FIG. 1 is a sectional view of a first embodiment of the invention.

As shown in FIG. 1(a), an oxide film 2 is formed on a semiconductor substrate 1.
is grown with a step of, for example, 3000A to 2μm,
Polysilicon 3 is grown thereon as shown in FIG. 1(b), etched using photolithography, and ultra-high energy ion implantation 4 (for example
．． 1 to 5 MkeV) so that the peak value after ion implantation is 5000 to 3 μm. Next, using the polysilicon 3 and the resist 15 as masks, a P space region 5 is formed through the oxide film 2 (FIG. 1(C)). Next, using the polysilicon 3 and the oxide film 2 as a mask, an N+ source region 6 is formed (FIG. 1(d)).

By doing as described above, the back gate portion 14 can be formed without forming the P- region, so that the process can be simplified. In addition, there is no need to take the size of the P-base into consideration when installing the cell.
Cell size can be reduced.

FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. FIG. 2 shows an example in which the resist 15 in FIG. 1 is replaced with an aluminum cover 16, and the rest is the same as the first embodiment.

〔Effect of the invention〕

As explained above, the present invention uses ultra-high energy ion implantation in the manufacturing of vertical MO8FETs to oxidize the back gate region of the P base region using polysiligate or a cover during polysilicon etching as a mask. The N+ source region is formed using polysilicon and an oxide film as a mask.

This eliminates the need to form a P-base region, so
The process can be simplified, and if the barrier/gate area is secured, the device can be designed without taking into account further diffusion of P, so the device can be made smaller. There is an effect.

[Brief explanation of the drawing]

1(a) to (d) are process cross-sectional views of the first embodiment of the present invention, FIGS. 2(a) to (d) are process cross-sectional views of the second embodiment of the present invention, and FIG. Figures (a) to (f) are conventional vertical MO8
It is a process sectional view of FET. 1... N-type semiconductor substrate, 2... Oxide film, 3... Polysilicon, 4... Ultra-high energy ion implantation, 5...・P base area, 6...
...N+ source region, 7...--interlayer insulating film, 8
...Source aluminum electrode, 9...Drain electrode, 10...Photoresist, 11.
...P-base region, 12...Mask oxide film, 13...Channel part, 14-...
・Back gate section, 15...Resist, 16
...Aluminum cover. 2,\, Agent Patent Attorney Susumu Uchihara: 'I/I!
[' □□--Force-zu 15 Ni Resist $ 2 Special opening UG2-291066 (4) Play 3W! J (Cλ

Claims (1)

[Claims] A method for manufacturing a vertical field effect transistor having a source and a gate on the surface of a semiconductor substrate and a drain on the back surface includes a step of growing an oxide film on the surface of the semiconductor substrate with steps in thickness, and a step of growing polysilicon on the surface of the semiconductor substrate. The process of growing and
A process of etching the polysilicon mainly in the thick oxide film using photolithography technology, and performing ultra-high energy ion implantation using the etching mask and the remaining polysilicon as a mask to form a semiconductor substrate with a conductivity type opposite to that of the semiconductor substrate. forming a second impurity region of the same conductivity type as the semiconductor substrate using the remaining polysilicon and the thick oxide film as a mask in the first impurity region;
1. A method for manufacturing a vertical field effect transistor, comprising the step of forming an impurity region.