JPH0964193A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form sources and drains of both MOSFETs of high and low withstand voltages by ion implantation at one time and to attain high reliability. SOLUTION: On the occasion when FET of high withstand voltage and FET of low withstand voltage are formed on the same substrate, a field oxide film 1 is grown selectively on the substrate and a first gate oxide film 2 is grown. A first resist film wherein a region of low withstand voltage and a region except a region to be used as a gate oxide film of high withstand voltage and a region wherein a low-concentration diffused layer 6 of high withstand voltage is to be formed are opened is formed. The first gate oxide film 2 is removed by etching with the first resist film used as a mask and a second gate oxide film 3 having a smaller thickness than the first gate oxide film is formed on the substrate. Gate electrodes 4 are formed on the second gate oxide film 3 of low withstand voltage and on the first gate oxide film 2 of high withstand voltage and a second resist film having a region of high withstand voltage opened is formed on the substrate. The low-concentration diffused layer 6 is formed by ion implantation and high-concentration diffused layers 8 in regions of sources and drains of low and high withstand voltages are formed by ion implantation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an MO device having two different withstand voltages on the same substrate.
It relates to a method of forming an S FET.

In this case, two types of MOS FETs having different breakdown voltages are used.
The gate insulating film (hereinafter referred to as the gate oxide film) has a different thickness, and high withstand voltage MOS FETs often have an offset drain structure.

[0003]

2. Description of the Related Art A conventional example of a method for manufacturing a semiconductor device having a second MOS FET (described as a low breakdown voltage MOS FET) and a first MOS FET having an offset drain structure (described as a high breakdown voltage MOS FET) is illustrated. A description will be given using 2 and 3.

2 (A) to 2 (E) are explanatory views of the first conventional example. In the figure, the low-voltage MOS FET is on the left and the high-voltage MOS FE is on the right.
Form T. In FIG. 2 (A), a field oxide film 1 is selectively grown on a silicon substrate 11, and a thick first film for high breakdown voltage is formed.
The gate oxide film 2 is grown to form a resist pattern α with an opening on the low breakdown voltage side.

In FIG. 2B, using the resist pattern α as a mask, the first gate oxide film 2 on the low breakdown voltage side is removed by etching with a hydrofluoric acid-based solution, the mask is removed, and the first gate oxide film 2 is removed. A thinner second gate oxide film 3 is formed.

Next, the gate electrode 4 is formed on the low breakdown voltage side and the high breakdown voltage side. Here, if ion implantation for source / drain formation is performed simultaneously on the low breakdown voltage side and the high breakdown voltage side, if the thick oxide film is used, the thin film will go too deep, and if the shallow oxide film is used, the thick film will be used for the silicon substrate. Will not reach.
Therefore, using the resist patterns β and γ, ion implantation is separately performed on the low breakdown voltage side and the high breakdown voltage side.

In FIG. 2C, a resist pattern β having an opening on the high breakdown voltage side is formed, and a low concentration diffusion layer 6 is formed by ion implantation 5 with a dose amount of the order of 12 to 13th power. FIG.
In (D), the resist pattern γ with the low breakdown voltage side opened
And a high-concentration diffusion layer 8 is formed by ion implantation 7 with a dose on the order of the 15th power.

In FIG. 2 (E), a resist pattern δ is formed which covers the low breakdown voltage side and opens the region excluding the offset portion on the high breakdown voltage side, and a high concentration is obtained by ion implantation 7 ′ with a dose amount of the 15th power order. A diffusion layer 8'is formed.

FIGS. 3A to 3E are explanatory views of the second conventional example. In the figure, the low-voltage MOS FET is on the left and the high-voltage MOS FE is on the right.
Form T. In this example, since the source / drain of the low breakdown voltage portion and the high breakdown voltage portion can be formed by one-time ion implantation, the oxide film in the entire element region is removed using a hydrofluoric acid-based solution after the gate electrode is formed. is there.

In FIG. 3A, a field oxide film 1 is selectively grown on a silicon substrate 11, a thick first gate oxide film 2 for high breakdown voltage is grown, and a resist pattern α having an opening on the low breakdown voltage side is formed. Form.

In FIG. 3B, using the resist pattern α as a mask, the first gate oxide film 2 on the low breakdown voltage side is removed by etching with a hydrofluoric acid-based solution, the mask is removed, and the first gate oxide film 2 is removed. A thinner second gate oxide film 3 is formed.

Next, the gate electrode 4 is formed on the low breakdown voltage side and the high breakdown voltage side. In Fig. 3 (C), the oxide film in the device region is removed using a hydrofluoric acid-based solution. In Fig. 3 (D), an oxide film is formed to alleviate damage during ion implantation.
A resist pattern β with an opening on the high breakdown voltage side is formed, and a low-concentration diffusion layer 6 is formed by ion implantation 5 with a dose on the order of 12 to 13th power. A resist pattern γ with an opening on the low breakdown voltage side is formed, and a high-concentration diffusion layer 8 is formed by ion implantation 7 with a dose on the order of the 15th power.

In FIG. 3 (E), a resist pattern ε having an opening on the low breakdown voltage side and an area excluding the offset portion on the high breakdown voltage side is formed, and ion implantation 7 with a dose amount of the 15th order reduces the low breakdown voltage. And a diffusion layer 8 in the source / drain region on the high breakdown voltage side.

[0014]

In the conventional example 1, the number of steps is large, and particularly in the case of the CMOS process, MOSF of both channels is used.
This will be done for ET, which is a redundant process.

On the other hand, in the second conventional example, this problem can be avoided, but since the oxide film on the source / drain is removed with a hydrofluoric acid-based solution using the gate electrode as a mask, erosion of the gate oxide film from the end of the gate electrode To do. Although this is filled in by a later thermal oxidation process, it results in accelerating the deterioration due to hot carriers and weakening the dielectric breakdown resistance of the gate oxide film.

It is an object of the present invention to form a source / drain of a high / low dual breakdown voltage MOS FET by one-time ion implantation and to achieve high reliability.

[0017]

[Means for Solving the Problems] To solve the above problems, 1) a high breakdown voltage MOS FET and a low breakdown voltage MOS are formed on the same silicon substrate.
When forming a FET, a field oxide film is selectively grown on a silicon substrate, a first gate oxide film is grown, and a low breakdown voltage is obtained.
A first resist pattern is formed in which the MOS FET region is opened and the region except the region used as the gate oxide film of the high breakdown voltage MOS FET and the region forming the low concentration diffusion layer of the high breakdown voltage MOS FET is opened. One step, a second step of etching away the first gate oxide film by using the first resist pattern as a mask to remove the first resist pattern, and the first gate on the silicon substrate. A second gate oxide film, which is thinner than the oxide film, is formed, and then a low breakdown voltage MOS FE is formed.
A third step of forming a gate electrode on the second gate oxide film of T and on the first gate oxide film of the high breakdown voltage MOS FET, and a second resist having a high breakdown voltage MOS FET region opened on the silicon substrate. A fourth step of forming a pattern, forming a low concentration diffusion layer by ion implantation, and removing the second resist pattern, and a low withstand voltage MOS FET and a high withstand voltage by ion implantation.
A method for manufacturing a semiconductor device, comprising: a fifth step of forming a high-concentration diffusion layer in a source / drain region of a MOS FET; or 2) In the third step, a gate electrode is formed on the side of the high breakdown voltage MOS FET to form a first gate oxide film. It is achieved by the method for manufacturing a semiconductor device as described in the above item 1, characterized in that it is formed over the second gate oxide film on the upper side and the source side.

According to the present invention, the source / drain formation of the high and low withstand voltage MOS FET is performed by one-time ion implantation, and there is no step of removing the oxide film with the hydrofluoric acid solution after the gate electrode is formed. The reliability of the device is improved because this can be prevented. Further, the thick first gate oxide film left on the low-concentration diffusion region provides an alignment margin between the gate electrode and the thin oxide region on the drain.

Further, depending on the position where the gate electrode is formed, the gate oxide film thickness on the source side of the high breakdown voltage MOS FET can be made the same as that on the drain side [see FIG. 1 (C)], and it can be made thinner [FIG. 1]. (See (D)]. The latter case is advantageous in terms of withstand voltage and characteristics. Therefore, the degree of freedom in selecting the device structure increases.

[0020]

1 (A) to 1 (F) are explanatory views of an embodiment. In the figure, the low withstand voltage MOSFET is on the left and the high withstand voltage MO is on the right.
Form S FET.

In FIG. 1A, p-type silicon (p-Si)
A field oxide film 1 having a thickness of 500 to 800 nm is selectively grown on a substrate 11, a thick first gate oxide film 2 having a high breakdown voltage of 50 to 80 nm is grown, and a low breakdown voltage side is opened. A resist pattern α having an opening in a region other than a region used as a gate oxide film on the high breakdown voltage side and a region for forming a low concentration diffusion layer
(First resist pattern) is formed. The source side opening of the resist pattern α may reach the region where the gate electrode is formed [FIG. 1 (C)] or may not reach it [FIG. 1 (D)].

In FIG. 1B, using the resist pattern α as a mask, the first gate oxide film 2 is removed by etching with a hydrofluoric acid solution to remove the mask. In FIG. 1 (C), a second gate oxide film 3 having a thickness of 10 to 25 nm, which is thinner than the first gate oxide film 2, is formed.

Next, the gate electrode 4 is formed on the low breakdown voltage side and the high breakdown voltage side. FIG. 1 (D) shows a device structure in which the gate electrode 4 is formed on the source side in the same process as in FIG. 1 (C).

In FIG. 1 (E), a resist pattern β (second resist pattern) having an opening on the high breakdown voltage side is formed, and ion species: phosphorus ions (P ⁺ ), energy: 50-100
KeV, dose amount; a low concentration diffusion layer 6 is formed by ion implantation 5 of 10 ¹² to 10 ¹³ cm ^-2 .

In FIG. 1 (F), the resist pattern β is removed, and ion species: arsenic ion (As ⁺ ), energy: 3
0 to 70 KeV, dose; up to 10 ¹⁵ cm ^-2 ion implantation 7 Diffusion layer in source / drain region on low and high breakdown voltage side 8
To form

Here, the thick first gate oxide film on the low-concentration diffusion layer 6 serves as an implantation mask. At this time,
P-channel MOS FET or n-channel MOS FE as in the embodiment
A device with only T does not need to have an offset structure, and thus can be made maskless. In the case of the CMOS process, a resist pattern in which the opposite channel side is not opened may be formed as in the usual case.

Although the n-channel MOS FET has been described in the embodiment, the present invention can be similarly applied to the p-channel MOS FET. For CMOS devices, a collective source / drain formation mask for n-channel MOS FET and p-channel MOS FET
It is sufficient to prepare a batch source drain mask.

[0028]

According to the present invention, high breakdown voltage and low breakdown voltage MOS
The source / drain of the FET can be implanted by one-time ion implantation to reduce the number of manufacturing steps, and the erosion of the gate oxide film due to etching can be prevented to achieve high reliability.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment.

FIG. 2 is an explanatory diagram of Conventional Example 1.

FIG. 3 is an explanatory diagram of Conventional Example 2.

[Explanation of symbols]

 1 field oxide film 2 first gate oxide film 3 second gate oxide film 4 gate electrode 5 low concentration ion implantation 6 low concentration diffusion layer 7 high concentration ion implantation 8 high concentration diffusion layer 11 silicon substrate α to ε resist pattern

Claims (2)

[Claims] 1. When forming a first MOS FET and a second MOS FET on the same silicon substrate, the first MOS FET and the second MOS FET are formed on the silicon substrate.
The gate insulating film of the first MOS FET was grown, the second MOS FET region was opened, and the region used as the gate insulating film of the first MOS FET and the region forming the low concentration diffusion layer of the first MOS FET were removed. A first step of forming a first resist pattern having an opening in a region; a second step of removing the first gate insulating film by etching using the first resist pattern as a mask; and a second step of removing the first resist pattern A step of forming a second gate insulating film thinner than the first gate insulating film on the silicon substrate, and then forming a second gate insulating film of the second MOS FET and a second gate insulating film of the first MOS FET. The third step of forming a gate electrode on the first gate insulating film, the second resist pattern having the first MOS FET region opened on the silicon substrate, and the low concentration diffusion layer is formed by ion implantation. , A fourth step of removing the second resist pattern When, a method of manufacturing a semiconductor device characterized by having a fifth step of forming a high concentration diffusion layer of the source drain region of the second MOS FET and a first MOS FET by the ion implantation. 2. The first MOS FET in the third step
2. The method of manufacturing a semiconductor device according to claim 1, wherein a gate electrode is formed on the first gate insulating film and on the second gate insulating film on the source side.