JPH10107266A - Manufacture of mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of hot carriers by relieving an electric field near a gate electrode by forming a diffusion area having the same conductivity as that of a drain area and sufficiently low impurity concentration or a diffusion area having the opposite conductivity on the surface of a low- concentration area forming the drain area. SOLUTION: A photoresist 3 is formed on a gate oxide film 2 so as to open the area proposed for the formation of the low-concentration diffusion area of a drain area. In order to form, for example, a low-concentration N-type diffusion area on the surface of a P-type semiconductor area l by using the photoresist 3 as a mask, the ion of an N-type impurity, for example, phosphorus is implanted. Thereafter, the ion of a P-type impurity, for example, BF2 is implanted by utilizing the same mask. The P-type impurity is prepared by selecting an impurity combination which is less diffused than the N-type impurity. When thermal diffusion is performed in the succeeding process, therefore, a P-type impurity area 12 is formed in a state where the area 12 is surrounded by a low-concentration N-type diffusion area 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS FET (field effect transistor) constituting a semiconductor integrated circuit, and more particularly to a method of manufacturing a MOS FET requiring a high breakdown voltage.

[0002]

2. Description of the Related Art A conventional method of manufacturing an N-channel MOS FET having a high breakdown voltage structure will be described below. A gate oxide film 2 is formed on the surface of a P-type semiconductor region 1 in a region where an element is to be formed, which is a P-type silicon substrate or a P-type well region. A photoresist 3 is formed on the gate oxide film 2 so as to open the source and drain formation regions. Using the photoresist 3 as a mask, an N-type impurity is ion-implanted to form a low-concentration N-type diffusion region 4 on the surface of the P-type semiconductor region 1 (FIG. 7).

After removing the photoresist 3, thermal diffusion of the implanted impurity ions is performed to form a low concentration N-type diffusion region 4. A polysilicon film is formed on the entire surface, patterned, and a gate electrode 5 is formed. Here, the gate electrode 5
Is formed so as to overlap a part of the low-concentration N-type diffusion region 4. Thereafter, an oxide film is formed on the entire surface by the CVD method, and dry etching is performed to form sidewalls 6 on the side surfaces of the gate electrode 5.

A photoresist 7 is patterned so as to expose a part of the low-concentration N-type diffusion region 4, and a high-concentration N-type diffusion region 4 is formed on the surface of the low-concentration N-type diffusion region 4 by using the photoresist 7, the gate electrode 5 and the sidewall 6 as a mask. N-type impurities are ion-implanted to form the N-type diffusion region 8 (FIG. 8).

After that, the photoresist 7 is removed, and the implanted impurity ions are thermally diffused to form a high concentration diffusion region 8. Hereinafter, an interlayer insulating film 9 is formed, and a source electrode 10 and a drain electrode 11 are formed according to a normal MOS-type FET manufacturing method (FIG. 9).

In the MOS type FET having such a structure, the low-concentration N-type diffusion region 4 and the gate electrode 5 are formed so as to partially overlap each other, and when a voltage is applied to the gate electrode 5, the gate electrode 5 The carrier concentration in the vicinity is increased, the on-resistance of the transistor is reduced, and the current driving capability is increased. Further, the low-concentration N-type diffusion region 4 has a structure in which an electric field between the drain and the gate is reduced, and the generation of hot carriers can be reduced.

[0007]

However, when driving at a relatively low voltage of about 10 V between the drain and gate, there is no problem. However, when driving at a higher voltage, generation of hot carriers occurs. There is a problem that can not be ignored.

[0008] The present invention solves the above problems and provides a drain,
An object of the present invention is to provide a method of manufacturing a high withstand voltage MOS-type FET by relaxing an electric field between gates, a low concentration diffusion region, and a gate.

[0009]

In order to achieve the above object, a manufacturing method of the present invention comprises a source region and a drain region of opposite conductivity type formed in a semiconductor region of one conductivity type, and the source region and the drain region. A gate electrode formed with a gate oxide film interposed therebetween, wherein the drain region comprises a high-concentration diffusion region in contact with the drain electrode and a low-concentration diffusion region extending below the gate electrode. Forming a mask for opening the region where the low concentration diffusion region is to be formed, and introducing at least two types of impurities having different conductivity types into the opening; Forming a low-concentration diffusion region of a type and a diffusion region of the opposite conductivity type or a one-conductivity type diffusion region having a lower impurity concentration than the low-concentration diffusion region in the low-concentration diffusion region; and Forming a gate electrode through the gate oxide film so as to overlap with a part of the diffusion region of the opposite conductivity type having a low impurity concentration or a diffusion region of one conductivity type. is there.

In the low-concentration diffusion region formed by such a manufacturing method, the electric field near the gate electrode is relaxed by the diffusion region having a lower impurity concentration than the low-concentration diffusion region or a diffusion region of a different conductivity type, so that the hot carrier Generation is suppressed. Further, by keeping the region having a high carrier density away from the gate oxide film, the amount of hot carriers trapped in the gate oxide film is reduced.

In particular, one conductivity type impurity introduced to form a reverse conductivity type diffusion region or a one conductivity type diffusion region having an impurity concentration lower than that of the low concentration diffusion region forms the low concentration diffusion region. By selecting a combination having a smaller diffusion coefficient than the impurity of the opposite conductivity type to be introduced, the MOS FE of the present invention can be manufactured in a simpler process.
T can be formed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below by taking an N-channel MOS type FET as an example.
First, a gate oxide film 2 is formed on the surface of a P-type semiconductor region 1 in a region where an element is to be formed, which is a P-type silicon substrate or a P-type well region. Photoresist 3 is formed on gate oxide film 2 so as to open a region where a low concentration diffusion region is to be formed in the drain region. Although the figure shows a case where a low concentration diffusion region is also formed in the source region, it is not always necessary to form the low concentration diffusion region in the source region. In order to form a low-concentration N-type diffusion region on the surface of the P-type semiconductor region 1 using the photoresist 3 as a mask, phosphorus as an N-type impurity is ion-implanted under the conditions of an acceleration voltage of 120 KeV and a dose of 8.0 × 10 12 / cm 2. I do. Thereafter, using the same mask, BF2, which is a P-type impurity, is subjected to an acceleration voltage of 70 KeV,
Ions are implanted under the conditions of a dose of 5.times.10@12 / cm @ 2 (FIG. 1). At this time, as the P-type impurity, a combination of impurities that are harder to diffuse than the N-type impurity is selected. Thus, when thermal diffusion is performed in a later step, the P-type diffusion region 12 is formed so as to be surrounded by the low-concentration N-type diffusion region 4.
Note that, depending on the implantation conditions of the N-type impurity and the P-type impurity, N
Although the surface of the type diffusion region may not be inverted to the P type, if the impurity concentration is sufficiently lower than that of the low concentration N type diffusion region 4,
It may be N-type. Hereinafter, a description of the case of forming an N-type diffusion region having a sufficiently lower impurity concentration than the low-concentration N-type diffusion region will be omitted.

After removing the photoresist 3, a heat treatment is performed to diffuse the implanted impurities. The P-type diffusion region 12 is formed so as to be surrounded by the low-concentration N-type diffusion region 4 by thermal diffusion. In addition, this heat treatment process
As will be described later, it is also possible to perform this step concurrently with another step performed under high temperature conditions. Form a polysilicon film on the entire surface,
Patterning is performed to form a gate electrode 5. Here, the gate electrode 5 includes the low-concentration diffusion region 4 and the P-type diffusion region 1.
2 is formed so as to overlap with a part of the same. Then, CVD
An oxide film is formed on the entire surface by a method, and dry etching is performed to form sidewalls 6 on the side surfaces of the gate electrode 5 (FIG. 2).

The photoresist 7 is patterned so as to expose a part of the P-type diffusion region 12 on the surface of the low-concentration N-type diffusion region 4, and the photoresist 7, the gate electrode 5 and the sidewall 6 are used as a mask to form a low-concentration N-type diffusion region. 4 and the P-type diffusion region 12 are ion-implanted to form a high-concentration N-type diffusion region 8 for contacting the source and drain electrodes (FIG. 3).

Thereafter, the photoresist 7 is removed, and an interlayer insulating film 9 is formed in accordance with a normal MOS FET manufacturing method. By the heat treatment in the process of forming the interlayer insulating film, the high-concentration N-type diffusion region 8 is formed so as to be surrounded by the low-concentration N-type diffusion region 4. As described above, this step can also serve as a heat treatment for forming the P-type diffusion region 12 near the surface so as to be surrounded by the low-concentration N-type diffusion region 4. Thereafter, a source electrode 10 and a drain electrode 11 are formed to complete a MOS FET (FIG. 4).

According to the present invention, a combination of an N-type impurity implanted to form a low-concentration N-type diffusion region and a P-type impurity implanted to form a P-type diffusion region or a low-concentration N-type diffusion region is provided. By selecting the implantation conditions so that the diffusion of the P-type impurity is smaller than that of the N-type impurity, it is possible to simultaneously form them by performing a single thermal diffusion using a single ion implantation mask. It can be formed by simple steps. In particular, when phosphorus is selected as an N-type impurity for forming the low concentration N-type diffusion region 4 and BF2 is selected as a P-type impurity for forming the P-type diffusion region 12, the diffusion coefficient of BF2 is smaller than that of phosphorus. Thus, a desired structure can be easily obtained by using a single mask and considering only the setting of the ion implantation conditions.

The P-type diffusion region alleviates the electric field near the gate oxide film and reduces the generation of hot carriers. Also,
By keeping the region having a high carrier density away from the gate oxide film, hot carriers trapped in the gate oxide film can be reduced.

The MOS type FET thus formed will be compared with a conventional MOS type FET. FIG.
When BF2 is injected at a constant acceleration voltage of 80 KeV,
The change in substrate current when the dose is changed is shown. Here, the substrate current is a current value obtained by subtracting the drain current from the source current, and indicates the sum of the amount of holes flowing out of the substrate or the well and the amount of electrons trapped in the gate oxide film. In the figure, the gate-source voltage Vgs
Constant, source-drain voltage Vds is 10 V, 15 V
V and 20 V, the ratio of the substrate current to the drain current is shown in percentage. The low-concentration N-type diffusion region into which BF2 is injected is 1.0.times.10@17 / c.
It was formed to about m3.

As shown in the figure, as the dose increases, the ratio of the substrate current to the drain current decreases. In particular, it can be seen that the higher the voltage between the source and the drain, the greater the rate of decrease. Since no significant change in the amount of holes flowing out of the substrate or well out of the substrate current is found, it is considered that the MOS FET of the present invention has an effect of reducing electrons trapped in the gate.

FIG. 6 shows the results of the hot carrier breakdown voltage test of the FET. The test conditions were as follows: gate-source voltage Vgs = 4 V, drain-source voltage Vds = 15 V, 2
At 0 V, a change in characteristics due to drain avalanche hot carrier injection (which is considered to cause the most severe degradation at room temperature) was examined. In the figure, the horizontal axis shows the source,
The reciprocal of the drain-to-drain voltage Vds.
% Indicates the estimated time required to change. As shown in the figure, it can be seen that the life of the MOS-type FET of the present invention is greatly extended as compared with the conventional MOS-type FET.

In the case where an N-type diffusion region having an impurity concentration sufficiently lower than that of a low-concentration N-type diffusion region is formed instead of the P-type diffusion region, the electric field near the gate electrode is relaxed and the hot carrier density is increased. There is an effect of keeping the region away from the gate oxide film, and the life can be greatly extended as compared with a conventional MOS-type FET.

Although the above description has been made with reference to an N-channel MOS-type FET, the present invention can be similarly realized with a P-channel MOS-type FET. At this time,
The low-concentration P-type diffusion region constituting the drain region has a low-concentration P-type diffusion region having a sufficiently low impurity concentration or an N-type diffusion region on the surface of the low-concentration P-type diffusion region. It is formed.

Combination of a P-type diffusion impurity implanted to form a low-concentration P-type diffusion region and an N-type impurity implanted to form a sufficiently low-concentration P-type diffusion region or an N-type diffusion region, and ion implantation By selecting the condition so that the diffusion of the N-type impurity is smaller than that of the P-type impurity, ion implantation is performed using a single ion implantation mask and thermal diffusion is performed to obtain a desired structure. It can be formed by a simple process. In particular, by selecting arsenic as the N-type impurity, when forming a sufficiently low-concentration P-type diffusion region or N-type diffusion region on the surface of the P-type diffusion region, good controllability is obtained.
A thin diffusion region can be formed. Note that phosphorus was selected as an impurity to be implanted to form a low-concentration P-type diffusion region.

In the case of the P-channel FET, similarly to the above-mentioned N-channel FET, the P-type diffusion region or the N-type diffusion region formed on the surface of the low-concentration P-type diffusion region and having a sufficiently low impurity concentration is formed by the electric field near the gate electrode. And the area with high carrier density is kept away from the gate oxide film,
The generation of hot carriers and the number of hot carriers trapped in the gate oxide film can be reduced, and the life can be greatly extended.

[0025]

As described above, according to the present invention, a diffusion region having the same conductivity type as the drain region and having a sufficiently low impurity concentration or the opposite conductivity type is formed on the surface of the low concentration region constituting the drain region. By forming a diffusion region having the following characteristics, the generation of hot carriers is suppressed, and the number of hot carriers trapped in the gate oxide film is reduced, so that the life of the FET can be greatly extended. In order to form such a structure, the present invention provides a combination of an impurity for forming a low-concentration region and an impurity for forming a diffusion region or the like having a sufficiently low impurity concentration, and selecting ion implantation conditions. A desired structure can be obtained by a simple process of performing ion implantation and thermal diffusion using a single ion implantation mask. This process is a process used for manufacturing a normal semiconductor device, and a semiconductor device can be manufactured with high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a sectional view illustrating an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 5 is a graph comparing the characteristics of the MOS type FET of the present invention and the conventional structure.

FIG. 6 is a graph comparing the characteristics of the MOS FET of the present invention and the conventional structure.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional MOS-type FET.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a conventional MOS-type FET.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a conventional MOS-type FET.

[Explanation of symbols]

 Reference Signs List 1 P type semiconductor region 2 Gate oxide film 3 Photo resist 4 Low concentration N type diffusion region 5 Gate electrode 6 Side wall 7 Photo resist 8 High concentration N type diffusion region 9 Interlayer insulating film 10 Source electrode 11 Drain electrode 12 P type diffusion region

Claims (2)

[Claims] 1. A semiconductor device comprising: a source region and a drain region of opposite conductivity type formed in a semiconductor region of one conductivity type; and a gate electrode formed between the source region and the drain region with a gate oxide film interposed therebetween. The drain region includes a high-concentration diffusion region of the opposite conductivity type in contact with the drain electrode and a low-concentration diffusion region of the opposite conductivity type extending to below the gate electrode.
In the method for manufacturing an OS-type FET, a step of forming a mask for opening the region where the low concentration diffusion region is to be formed, and introducing at least two types of impurities having different conductivity types into the opening; Forming a reverse-conductivity-type low-concentration diffusion region and a reverse-conductivity-type diffusion region or a one-conductivity-type diffusion region having a lower impurity concentration than the low-concentration diffusion region in the low-concentration diffusion region; A MOS FET comprising a step of forming the gate electrode via the gate oxide film so as to overlap a part of the diffusion region of the opposite conductivity type having a low impurity concentration or the diffusion region of the one conductivity type. Manufacturing method. 2. The method according to claim 1, wherein said impurity is introduced to form a reverse conductivity type diffusion region or a one conductivity type diffusion region having a lower impurity concentration than said low concentration diffusion region. Is a method of manufacturing a MOS FET, wherein a diffusion coefficient is smaller than that of an impurity of the opposite conductivity type introduced to form the low concentration diffusion region.