JP3023934B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. Specifically, the present invention relates to a method for manufacturing a semiconductor device by a self-alignment (self-alignment) process.

[0002]

BACKGROUND OF THE INVENTION improve the transconductance g _m of a compound semiconductor MESFET or the like conventionally, for the purpose of reducing noise, self-aligned process of gate electrode that can achieve shortening of reducing the gate length of the source resistance is employed ing.

As the self-alignment process, a heat-resistant gate method and a dummy gate method (T-type gate method, side-wall gate method) are known, but in order to achieve the above object, there is a high degree of freedom in selecting process conditions. A high dummy gate method is effective.

FIGS. 15A to 15D show a manufacturing process of a GaAs MESFET by the T-type gate method. First, as shown in FIG. 15A, a photoresist 52 is formed in a field portion on the surface of a semi-insulating GaAs substrate 51, and an n-type active layer 53 is ion-implanted into an element formation region using the photoresist 52 as a mask. Then, a dummy gate 54 and a cap 55 are stacked at the center of the n-type active layer 53. Further, as shown in FIG. 15B, the dummy gate 54 is etched to form the dummy gate 54 and the cap 5.
5 is T-shaped, and ions are implanted into the element formation region of the GaAs substrate 51 using the cap 55 as a mask.
As shown in (c), an n ⁺ injection layer 56 is provided on both sides of the n-type active layer 53.
To form Then, after removing the cap 55, FIG.
5D, the source and drain electrodes 57 are formed on the n ⁺ implantation layer 56, and the position of the dummy gate 54 is reversed by a resist or the like.
Is removed, and the gate electrode 58 is formed by duplicating the dummy gate 54 with a Schottky electrode material.

[0005] According to the T-shaped gate method, can control the distance between the n ⁺ implanted layer by the width of the cap, it is possible to control the gate length by the width of the dummy gate, increasing the distance between the n ⁺ implanted layer, a gate length the shortened thereby improving the transconductance g _m by.

However, since a short channel effect occurs when the gate length is reduced, an n 'layer having a smaller impurity density than the n ⁺ implantation layer is required between the n ⁺ implantation layer and the gate electrode. However, in the standard step of the conventional T-type gate method, it was impossible to form an n 'layer due to the process.

FIGS. 16A to 16D show a GaAsM having an LDD (Lightly Doped Drain) structure by a sidewall gate method.
1 shows a manufacturing process of an ESFET. First, FIG.
As shown in FIG. 5, an n-type active layer 63 is formed by ion implantation in an element formation region of a semi-insulating GaAs substrate 61 using a photoresist 62 formed in a field portion as a mask.
A dummy gate 64 is provided on the n-type active layer 63. Further, as shown in FIG. 16B, sidewalls 65 made of an insulating film are provided on both side surfaces of the dummy gate 64, and GaAs is formed using the dummy gate 64 and the sidewall 65 as a mask.
Ion implantation is performed on the element formation region of the s substrate 61, and n ⁺ implantation layers 66 are formed on both sides of the n-type active layer 63. Then, after removing the sidewall 65, the dummy gate 6 is removed.
4 and the photoresist 62 as a mask, ions are implanted into the element formation region, and as shown in FIG.
An n 'layer 67 having an intermediate impurity density is formed between the ⁺ implantation layer 66 and the n-type active layer 63. Thereafter, as shown in FIG. 16D, a source and drain electrode 68 is formed on the n ⁺ implantation layer 66, and the position of the dummy gate 64 is reversed by a resist or the like. The gate electrode 69 is formed by removing and removing the dummy gate 64 with a Schottky electrode material.

According to this sidewall gate method, the length of the n 'layer can be controlled by the thickness of the sidewall, and the gate length can be controlled by the width of the dummy gate.

However, in the sidewall gate method, since the sidewall is formed by the insulating film, a thick sidewall cannot be obtained and an n 'layer having a large length cannot be obtained. In addition, the gate length is limited by the performance of photolithography. At present, it is very difficult to fabricate a submicron dummy gate.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and has as its object to form an n 'layer between an n ⁺ injection layer and a gate electrode. It is possible to freely determine the length of the n 'layer and the gate length.

[0011]

According to a method of manufacturing a semiconductor device according to the present invention, an ion-implanted region having a lower impurity density than the source and drain regions is provided between the source and drain regions and the side wall of the gate electrode. Forming a dummy gate having a substantially uniform width by laminating a low melting point layer made of a low melting point material on an upper surface of a dummy gate main body provided immediately above a channel region of a semiconductor substrate. Etching the two side surfaces of the dummy gate body to make the dummy gate substantially T-shaped; and melting the low melting point layer of the substantially T-shaped dummy gate on the upper surface of the dummy gate body so as to be wider than the original dummy gate. Forming a dummy gate having a narrow width and a substantially uniform width.

[0012]

According to the present invention, the width of the dummy gate can be gradually reduced each time the second and third steps are repeated after the formation of the three-layer dummy gate. Therefore, in the process of sequentially reducing the width of the dummy gate, first, a source / drain region (n ⁺ implantation layer) is formed, and when the width of the dummy gate is further reduced, a region having a lower impurity density than the source / drain region ( n ′ layer).

Moreover, the distance between the source and the drain, the distance between the regions having a low impurity density, the gate length, and the like can be freely determined, and the desired electrical characteristics can be obtained.

[0014]

1 to 14 show one embodiment of the present invention.
FIG. 4 is a cross-sectional view showing main steps for manufacturing a self-aligned MESFET using an ion implantation method.

First, the field portion of the semi-insulating GaAs substrate 1 is covered with a photoresist (not shown), and selective ion implantation is performed on the surface of the GaAs substrate 1 using the photoresist as a mask to form an n-type active layer (channel region). 2) [FIG. 1].

After removing the photoresist, an insulating film 3, such as a SiNx film or a SiO ₂ film, a high melting point metal film 4, and a low melting point metal film 5 are deposited on the entire surface of the GaAs substrate 1 (FIG. 2). Then, the insulating film 3, the high melting point metal film 4, and the low melting point metal film 5 are partially removed by a wet etching method or a dry etching method so as to leave a width of several microns or less substantially at the center of the GaAs substrate 1. A dummy gate 6 having a three-layer structure including an insulating film 3 having a width, a high melting point metal film 4, and a low melting point metal film 5 is formed (FIG. 3). This etching step may be performed using a general photolithography technique. However, the width of the insulating film 3, the high melting point metal film 4, and the low melting point metal film 5 remaining after the etching is determined by the source / source of the final MESFET. Since the distance between the drain regions is provided, the shape is suitable for the purpose. In this embodiment, the dummy gate body is constituted by the insulating film 3 and the high melting point metal film 4.

Thereafter, an implantation mask is formed in the field portion by using the photoresist 7, and high-concentration n-type ion implantation is performed using the photoresist 7 and the three-layer dummy gate 6 as a mask to form an n ⁺ implantation layer (source and drain). Region 8 is formed (FIG. 4).

Next, the insulating film 3 of the dummy gate 6 is selectively and isotropically etched by reactive ion etching (RIE) using a gas such as CF ₄ / O ₂ to form the T-type dummy gate 6. It is formed (FIG. 5). Since the etching length of the insulating film 3 (or the overhang dimension of the high melting point metal film 4 and the low melting point metal film 5) is the length of the n 'layer 9 as described later, the necessary n' layer 9 Etch until the length is equal.

Further, the refractory metal film 4 of the dummy gate 6
Is etched until it becomes equal to the length of the insulating film 3 (FIG. 6). The etching of the high melting point metal film 4 can be performed by either reactive ion etching or wet etching. However, in order to ensure the selective etching of the high melting point metal film 4 and the low melting point metal film 5, wet etching is desirable. .

Next, Ga having the structure shown in FIG.
The As substrate 1 is heated to melt the low melting point metal film 5, and the melted low melting point metal film 5 is spread over the entire high melting point metal film 4 (FIG. 7). As a heating method, lamp irradiation from the surface or oven heating may be used. At this time, if the high-melting-point metal film 4 does not exist under the low-melting-point metal film 5, the molten low-melting-point metal film 5 aggregates round (ball-up). Figure 7
Can be realized.

[0021] Thus after the short width of the dummy gate 6, the dummy gate 6 and performs a low ion implantation with little dose than n ⁺ implanted layer 8 using the photoresist 7 as a mask, n ⁺ implanted layer 8 and the n-type active N ′ layer 9 between layer 3
Is formed (FIG. 8).

Thereafter, the insulating film 3 of the dummy gate 6 is isotropically etched by reactive ion etching to form a T-shaped dummy gate 6 again (FIG. 9). Since the width of the insulating film 3 becomes the gate length of the gate electrode 13a, the etching is performed until the target gate length is obtained.

Next, the refractory metal film 4 of the dummy gate 6
Then, the low melting point metal film 5 is separated from the insulating film 3 by wet etching, and the photoresist 7 is also separated by etching [FIG. 10]. In this state, activation annealing of the ion-implanted layer is performed for about 15 minutes under the conditions of an As partial pressure of 3 Torr and 850 ° C.

Next, A
An ohmic electrode (source electrode and drain electrode) 10 of uGe / Ni / Au is formed on the n ⁺ implanted layer 8, and alloying is performed (FIG. 11). Photoresist 11 is replaced by Ga
The photoresist 1 is applied to the entire surface of the As substrate 1 to cover the dummy gate 6 (insulating film 3) and the ohmic electrode 10, and the photoresist 1
1 is baked and flattened, and then etched by reactive ion etching until the top surface of the dummy gate 6 is exposed (FIG. 12).

Subsequently, the dummy gate 6 is etched and removed by reactive ion etching using the photoresist 11 as a mask.
2 was formed, and a metal 13 for a Schottky electrode such as Ti / Pt / Au or Ti / Al was deposited by an evaporation method [FIG.
3] Then, the metal 13 for the Schottky electrode on the photoresist 11 is removed by a lift-off method to remove the gate electrode 13.
a is formed (FIG. 14).

Note that the steps of FIGS.
This is an example for forming T, and most other known methods can be applied.

Thus, according to the above method, the conventional T
GaAs with LDD structure by a method similar to the gate type method
can be produced SMESFET, it is possible to suppress the short channel effect while increasing the transconductance g _m.

Although not shown, according to another embodiment of the present invention, a MESFET may be manufactured as follows.
That is, after performing the steps of FIGS. 1 to 3, ions are implanted to form an n ⁺ implanted layer of FIG.
The process of FIG. 7 is performed. Thereafter, ion implantation with a high impurity concentration is performed in the state of FIG. 7 to form an n ⁺ implanted layer.
Returning to the step, the steps of FIGS. 5 to 14 are performed in the same manner as in the first embodiment.

According to this alternative embodiment, the distance between the n ⁺ injection layers, the distance between the n ′ layers, the gate length, and the like can be made shorter than those in the first embodiment.

Similarly, the width of the dummy gate can be arbitrarily reduced by repeating the steps shown in FIGS.

[0031]

According to the present invention, since the width of the dummy gate serving as a mask for ion implantation can be arbitrarily reduced, a region having a lower impurity density than the source / drain region can be formed by a method similar to the T-type gate method. Can be formed,
It becomes possible to manufacture a semiconductor device having an LDD structure.
Therefore, it is possible to achieve both the reduction of suppression and the source resistance of the short channel effect (increase of the transconductance g _m).

In addition, the distance between the source and the drain, the distance between the regions having a low impurity density, the gate length, and the like can be freely determined, and the desired electrical characteristics can be obtained.

[Brief description of the drawings]

FIGS. 1 to 14 are cross-sectional views showing one embodiment of the present invention.

FIG. 2 is a partial view of FIG. 1;

FIG. 3 is a block diagram of FIG. 1;

FIG. 4 is a partial view of FIG. 1;

FIG. 5 is a partial view of FIG. 1;

FIG. 6 is a partial view of FIG. 1;

FIG. 7 is a partial view of FIG. 1;

FIG. 8 is a block diagram of FIG. 1;

FIG. 9 is a partial view of FIG. 1;

FIG. 10 is a partial view of FIG. 1;

FIG. 11 is a partial view of FIG. 1;

FIG. 12 is a partial view of FIG. 1;

FIG. 13 is a partial view of FIG. 1;

FIG. 14 is a partial view of FIG. 1;

FIGS. 15A, 15B, 15C, and 15D are cross-sectional views illustrating a method of manufacturing a semiconductor device by a conventional T-gate method.

16 (a), (b), (c) and (d) are cross-sectional views showing a method for manufacturing a semiconductor device by a conventional side wall gate method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 GaAs substrate 2 n-type active layer 3 insulating film 4 high melting point metal film 5 low melting point metal film 6 dummy gate 8 n ⁺ injection layer 9 n 'layer 10 ohmic electrode 13 a Schottky electrode

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising an ion implantation region having a lower impurity density than a source and drain region between a source and drain region and a side wall of a gate electrode. Forming a dummy gate having a substantially uniform width by laminating a low melting point layer made of a low melting point material on the upper surface of the dummy gate body provided immediately above, and etching both sides of the dummy gate body to form a dummy gate. Forming a substantially T-shaped dummy gate; and melting a low melting point layer of the substantially T-shaped dummy gate on the upper surface of the dummy gate body to form a dummy gate having a substantially uniform width narrower than the original dummy gate. A method for manufacturing a semiconductor device having: