JPH03225837A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To prevent characteristic deterioration due to short-channel effect by enabling only a high-concentration n-type layer of a source electrode region to be self-aligned to a gate electrode and by forming the high-concentration n-type layer of a drain electrode region away from the gate electrode. CONSTITUTION:A gate electrode 14G is formed at a side wall of a first insulation film 11, metal layers 12 and 13 at a region other than this are eliminated, ion is implanted at a mask of the metal layers 12 and 13 and the first insulation film 11, thus forming a second high-concentration n-type layer 15 between the gate electrode 14G and a source electrode 145. Thus, since only the high- concentration n-type layer 15 of the region of the source electrode 14G is self- aligned to the gate electrode 14G and a high-concentration n-type layer 107 of a drain electrode 14D region is formed away from the gate electrode 14G, the gap between the high-concentration n-type layers 107 and 15 can be fully wide even if the gate length is shortened. Thus, even if the gate length is reduced, characteristic deterioration due to short-channel effect can be prevented.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a field effect transistor, and in particular to a highly doped n-type layer in which only a source electrode region is self-aligned with a high melting point gate electrode. The present invention relates to a method of manufacturing a field effect transistor having the following.

(Prior art) In recent years, field-effect transistors (hereinafter referred to as FETs) using ■-■ group compound semiconductors, especially GaAs, are showing promise in terms of improved performance, uniformity of characteristics, and reproducibility. Many matched FETs, such as FETs having a highly doped n-type layer (n+) self-aligned with a high melting point gate electrode, have been developed. This is because forming a highly doped n-type layer close to the gate electrode has the advantage of reducing the series resistance (Rs) of the device, and also eliminates the need for mask alignment between the gate electrode and the heavily doped n-type layer. It is characterized by excellent uniformity of characteristics and reproducibility.

However, since the highly doped n-type layer on the drain side is in contact with the gate electrode, the withstand voltage between the gate and the drain becomes low, and when the gate length is less than 1.0 volts, the distance between the two highly doped n-type layers is close, resulting in a short channel. Since the effect becomes noticeable and the train conductance increases, good characteristics cannot necessarily be obtained as a high frequency amplification element. Therefore, attempts have been made to form an insulating film on the side walls of the gate electrode and use this as a mask for ion implantation to separate the highly doped n-type layer from the end of the gate electrode. An example of such an attempt will be described below with reference to FIGS. 2(a) to (h).

Si ions are implanted into one main surface of the semi-insulating GaAs substrate 101 under conditions of an acceleration energy of 80 KeV and implantation of 4i4 x 1012 cm-2, and an n-type active layer 102 is formed by capless annealing at 850° C. and 15 m1n ( Figure 2(a)).

A high melting point metal layer 1, for example, tungsten nitride (WN
) layer 103 and a low resistivity metal such as an Au layer 104 laminated thereon (FIG. 2(b)).

A resist mask 1 is placed on the gate electrode formation region on the metal layer.
00 is formed (FIG. 2(C)).

Using this mask, the Au layer 104 was etched by ion milling, and the -N layer 1 was etched by reactive ion etching (RIE).
03 is anisotropically etched, and the gate electrode 1
05G is formed (FIG. 2(d)).

After forming, for example, a SiO □ film on the main surface of the GaAs substrate 101 as a first insulating film, anisotropic etching is performed by RIE, and S is formed on the side walls of the gate electrode.
In, a film 106 is formed (FIG. 2(e)).

Next, the acceleration energy was 250 KeV, the implantation amount was 4×10'3
Si ion implantation is performed under the condition of "cm-" to form a heavily doped n-type layer 107 (FIG. 2(f)).

After depositing, for example, a PSG film (108) as a second insulating film on the main surface of the GaAs substrate 101, it is heated at 850°C for 5 seconds.
The high concentration n-type layer 1 is subjected to Franche annealing of c.
07 is activated (Fig. 2 (g)).

Ohmic electrode 1 For example, by forming an Au-Ge/Pt metal layer and performing heat treatment, a source electrode 105S and a drain electrode 105D are formed, and a self-aligned GaAsFET is formed.
is completed (Fig. 2 (h)).

The above self-aligned GaAsFET has a gate electrode and a high concentration n
Since the type layer is separated by the insulating film 108, the gate-drain breakdown voltage is improved, and since the spacing between the high concentration n-type layers can be widened, characteristic deterioration due to the short channel effect can be prevented.

On the other hand, in order to improve the characteristics of FETs, it is necessary to shorten the gate electrode dimensions, but the conventional self-aligned Ga
In AsFETs, when the gate length is shortened, the spacing between the heavily doped n-type layers inevitably becomes narrower, resulting in a noticeable increase in drain conductance due to the short channel effect, which actually causes deterioration of the characteristics.

(Problems to be Solved by the Invention) As mentioned above, in conventional self-aligned GaAsFETs, the spacing between high-concentration n-type layers largely depends on the gate length. There was a problem that the layer spacing became narrower and the characteristics deteriorated due to the short channel effect. To solve this problem, a high concentration of n on the source side is required.
The structure reduces Rs by forming the type layer and the gate electrode close to each other through self-alignment, and prevents a drop in breakdown voltage by forming the highly doped n-type layer on the drain side and the gate electrode at a distance. Although this is desired, there has been no suitable manufacturing method to date.

The present invention has been made in order to eliminate the above-mentioned drawbacks.The present invention has been made to eliminate the above-mentioned drawbacks. An object of the present invention is to provide a method for manufacturing a field effect transistor in which the distance between the gate electrode and the gate electrode can be increased.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, in the present invention, in order to self-align only the highly doped n-type layer in the source electrode region with the gate electrode, from the drain side of the gate electrode region to the drain region, An insulating film is formed, and a high melting point metal that will become a gate electrode is first formed on the sidewalls of the insulating film. Next, ion implantation is performed using the gate electrode and the insulating film as a mask to form a highly doped n-type layer that is self-aligned to the gate electrode only in the source electrode region. forming an n-type active layer on the semiconductor substrate and a first high-concentration n-type layer forming a source electrode region and a drain electrode;
forming a first insulating film covering each of the mold layers;
a step of removing a first insulating film from a region where a gate electrode is formed to a source electrode region in the n-type active layer region; and a high-melting point metal or a high-melting point metal that makes Schottky contact with the n-type active layer. forming a metal layer containing metal; performing anisotropic etching on the metal layer to form a gate electrode on the sidewall of the first insulating film and removing the metal layer in other areas; The method is characterized by including a step of performing ion implantation using the metal layer and the first insulating film as a mask to form a second highly doped n-type layer between the gate electrode and the source electrode region.

(Function) Only the high-concentration n-type layer in the source electrode region can be self-aligned with the gate electrode, and the high-concentration n-type layer in the drain electrode region can be formed at a distance from the gate electrode, so the spacing between the high-concentration n-type layers can be reduced. Even if the gate length is shortened, sufficient spacing can be maintained, and therefore, even if the gate length is shortened, characteristic deterioration due to short channel effect can be prevented. Furthermore, in the present invention,
A high gate-drain breakdown voltage can be obtained while keeping Rs low.

(Example) An example of the method for manufacturing a field effect transistor according to the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views showing the manufacturing method of one embodiment in the order of steps.

First, one main surface of a semi-insulating GaAs substrate 101 was implanted with an acceleration energy of 80 KeV and an implantation amount of 4 x 10"cm-2, and an acceleration energy of 250KeV and an implantation amount of 4 x 10"cm-2.
Si ion implantation was performed under the condition of 10l3'' to form an n-type active layer 102 and two first high concentration n-type layers 107,
107 (FIG. 1(a)).

Next, after depositing, for example, a 5i02 film 11 as a first insulating film on the surface of the GaAs substrate 101, a resist mask is used to form a 5in2 film from the region of the n-type active layer region where the gate electrode is formed to the source electrode region. For film etching, a layer 12 of a high melting point metal, for example, is deposited on the surface of the GaAs substrate 101 by reactive sputtering, and an Au layer 13 is deposited thereon (FIG. 1(b)).
.

Next, the Au layer 13 is etched by ion milling, and the WN layer 12 is etched by reactive ion etching (RIE).
Anisotropic etching is applied to each of the gate electrodes 14G to form a gate electrode 14G on the side wall of the 5in2 film 11 on the train side (FIG. 1(C)).

Next, the acceleration energy is 250 eV, the implantation amount is 2×10”c
The n-type active layer 102.m-2 is formed on the side of the gate electrode 14G under the condition of .m-2. and the first high concentration n
Si ion implantation is performed on one side of the source side of the mold layer 107,
A second high concentration n-type layer 15 is formed (FIG. 1(d)).

Next, after removing the 5in2 film 11, a second insulating film made of, for example, 6 PSG films is deposited on the main surface of the GaAs substrate 101, and then flash annealing is performed at 850° C. for 5 seconds to remove the second insulating film. 1 and 2nd high concentration n-type layer 10
7. Activation of 15 is performed (Fig. 1(e)).

Finally, the highly doped n-type layer 10 on the source side and drain side
By forming an ohmic electrode, for example, an Au-Ge/Pt metal layer on 7 and performing heat treatment, a source electrode 14s and a drain electrode 140 are formed, respectively, and the self-aligned GaA
The sFET is completed (FIG. 1(f)).

〔Effect of the invention〕

As described above, according to the present invention, only the high concentration n-type layer in the source electrode region can be self-aligned with the gate electrode, and the high concentration n-type layer in the drain electrode region can be formed at a distance from the gate electrode. The high concentration n-type layer spacing can provide a sufficient distance even when the gate electrode is shortened, and therefore, even when the gate length is shortened, characteristic deterioration due to the short channel effect can be prevented.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are cross-sectional views showing one embodiment of the method for manufacturing a field effect transistor according to the present invention in order of steps, and FIGS. 2(a) to (h) are field effect transistors of the conventional example. All are cross-sectional views showing an example of a method for manufacturing a transistor in the order of steps. 11·5in2 film (first insulating film), 12··vN layer,
13-Au layer, 1.4G=gate electrode, 145-source electrode, 14D...drain electrode, 15-second high concentration n-type layer, 16-PSG film (second insulating film), 101... Semi-insulating GaAs substrate, 102... n-type operating layer, 107... first high concentration n-type layer.

Claims (1)

[Claims] forming an n-type active layer that will become a gate electrode region and a first high concentration n-type layer that will become a source electrode region and a drain electrode on a III-V group compound semiconductor substrate; forming a first insulating film covering each of the type active layer and the first high concentration n-type layer, and forming a first insulating film covering each of the n-type active layer region from the region where the gate electrode is formed to the source electrode region a step of removing the first insulating film;
forming a high melting point metal or a metal layer containing a high melting point metal that makes Schottky contact with the n-type operating layer; and performing anisotropic etching on the metal layer to form a gate on the sidewall of the first insulating film. A step of forming an electrode and removing the metal layer in other regions, and performing ion implantation using the metal layer and the first insulating film as a mask to form a second high concentration n between the gate electrode and the source electrode region. A method for manufacturing a field effect transistor, comprising the step of forming a mold layer.