JPH05190575A - Forming method of ldd structure of compound semiconductor mesfet - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing an LDD structure of a compound semiconductor MESFET, where the MESFET can be lessened in source resistance, gate length, and noises and enhanced in mutual conductance. CONSTITUTION:A first process where a first insulating film 4 large in etching rate, a second insulating film 5 small in etching rate, and a third insulating film 6 whose etching rate stands between those of the films 4 and 5 are laminated on a semi-insulating board 1 following this order, a second process where a dummy gate 8 of three-layered structure composed of the insulating films 4, 5, and 6 is formed on a channel region, and a third process where the dummy gate 8 is formed into a cross in cross section by etching are provided. A fourth process is added, where ions are implanted using the cross-shaped dummy gate 8 as a mask to form a high concentration impurity region 10 and a low concentration impurity region 11 at the same time in a source and a drain region which confront each other sandwiching a channel region between them.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a compound semiconductor MESF.
The present invention relates to a method for forming an LDD structure in ET (MEtal Semiconductor FET).

[0002]

2. Description of the Related Art Conventionally, in a compound semiconductor MESFET, in order to improve FET characteristics, LDD (Ligh
A structure called tly Doped Drain-source) or n'is adopted. That is, as shown in FIG. 4, this LDD structure is formed in each of the channel region under the gate electrode 30 forming the FET and the source and drain regions under the ohmic electrode 31 which are arranged to face each other with the gate electrode 30 interposed therebetween. A low-concentration impurity region (n ′ region) 33 having an intermediate impurity concentration between the formed high-concentration impurity region (n ⁺ region) 32 is formed. Reference numeral 34 in FIG. 6 is a semi-insulating compound semiconductor substrate, and 35 is an operation layer (active layer).

By the way, when forming such an LDD structure, it is general to use a so-called sidewall. That is, in this forming method, first, as shown in FIG. 5A, W is previously formed on the channel region of the FET in the semi-insulating compound semiconductor substrate 34.
After the gate electrode 30 made of a heat-resistant metal such as Si is formed and the side wall 36 made of an insulating film such as SiO ₂ is formed on the side portion of the gate electrode 30, the gate electrode 30 and the side wall 36 are masked. Is performed to form n ⁺ regions 32 in each of the source and drain regions. Further, subsequently, as shown in FIG.
As shown in (b), after removing the sidewall 36, ion implantation using the gate electrode 30 as a mask is performed again to form an n ′ region 33, and then an ohmic electrode 31 is formed on the source and drain regions. Is being done.

[0004]

By the way, in the conventional method of forming the LDD structure, it is difficult to shorten the gate length due to the limitation of photolithography, and since the heat resistant metal is used as the gate electrode 30, the gate resistance is reduced. Since it is difficult to increase the thickness of the sidewall 36, the distance between the gate electrode 30 and the n ′ region 33, that is, the degree of freedom in setting the dimensions of the n ′ region 33 becomes small. The inconvenience, such as, was to occur.

The present invention was devised to eliminate these disadvantages. The source resistance (Rs) can be reduced, the gate length can be shortened, and the mutual conductance (g) can be reduced.
m) and LDD capable of achieving low noise
It is intended to provide a method of forming a structure.

[0006]

In order to achieve such an object, a method for forming an LDD structure according to the present invention has a first insulating film having a large etching rate, a second insulating film having a small etching rate, and Depositing each of the third insulating films having an intermediate etching rate of both insulating films on the semi-insulating substrate in this order;
The step of forming a three-layered dummy gate made of these insulating films on the channel region, the step of making the cross-sectional shape of the dummy gate into a cross shape by etching, and the ion implantation using this dummy gate as a mask The method further includes the step of simultaneously forming a high-concentration impurity region and a low-concentration impurity region in each of the source and drain regions facing each other across the region.

[0007]

Embodiments of the method of the present invention will be described below with reference to the drawings. In the following description, it is assumed that the compound semiconductor MESFET is a GaAs MESFET, but the invention is not limited to this.

FIGS. 1 to 3 are process cross-sectional views showing a method of forming an LDD structure according to an embodiment of the present invention in accordance with the procedure. FIG. 1 is a front step group in the present forming method, and FIG. 2 is an intermediate step group. , FIG. 3 shows the subsequent process groups.

First, as shown in FIG. 1A, after a photoresist layer 2 is formed on a semi-insulating GaAs substrate 1 and patterned, the remaining photoresist layer 2 is selectively used as a mask. FE by performing simple ion implantation
An n-type operating layer 3 is formed over the entire surface in the T region. The ion implantation conditions for forming the operating layer 3 are, for example, implantation energy of 100 keV and a dose of 3 × 10.
It is set to ¹² cm ^-2 .

Next, after removing the photoresist layer 2,
As shown in FIG. 1B, first to third insulating films 4, 5 and 6 made of silicon nitride (SiN _x ) or the like and having different etching rates are continuously stacked by a PE-CVD method or the like. A film is formed and deposited on the surface of the semi-insulating GaAs substrate 1. At this time, the insulating films 4, 5,
6 Each film thickness is 3000Å, 1000Å, 4000
On the other hand, the etching rate of the first insulating film 4 located on the lower side is higher than the etching rates of the other insulating films 5 and 6 by changing the film forming conditions as appropriate. It is set that the second insulating film 5 located on the upper side has a low etching rate, and the third insulating film 6 located on the upper side has an intermediate etching rate between the first and second insulating films 4 and 5. To be done.

That is, the etching rates of these insulating films 4 to 6 depend on the ratio of silane (SiH ₄ ) and ammonia (NH ₃ ) at the time of film formation.
For example, when forming the first insulating film 4, SiH ₄ / NH ₃
The ratio is set to 0.15, the ratio when the second insulating film 5 is formed is 0.2, and the ratio when the third insulating film 6 is formed is 0.5. Here, all of the first to third insulating films 4, 5 and 6 are made of silicon nitride (Si
N _x) but it is assumed that the like, is not limited thereto, for example, any of these or those made of silicon dioxide (SiO _2), or to those made of an organic material Is optional.

Subsequently, a photoresist layer 7 is formed on the third insulating film 6 and patterned, and then, as shown in FIG.
As shown in (c), RIE using the photoresist layer 7 left in the portion corresponding to the channel region of the FET as a mask.
The unnecessary portions of the first to third insulating films 4, 5, and 6 are anisotropically removed by (reactive ion etching) to form a dummy gate 8 having a three-layer structure, and then the photoresist layer 7 is formed. Remove. After that, as shown in FIG. 1D, the dummy gate 8 is isotropically etched by wet etching or RIE so that its cross-sectional shape becomes a cross shape. That is, the etching rate of each of the first to third insulating films 4, 5 and 6 forming the dummy gate 8 is in the order of first insulating film 4> third insulating film 6> second insulating film 5. Therefore, the first insulating film 4 is removed most by the etching at this time,
Further, the third insulating film 6 is largely removed next to the insulating film 4, while the second insulating film 5 is left without being removed so much. As a result, the sectional shape of the dummy gate 8 is cross-shaped. It takes shape.

Further, after forming a photoresist layer 9 which newly covers the semi-insulating GaAs substrate 1 and performing patterning, as shown in FIG. 1E, this photoresist layer 9 and the dummy gate 8 are formed. Is used as a mask to perform ion implantation. Then, a high-concentration impurity region (n ⁺ region) 10 and a low-concentration impurity region (n 'region) 11 are simultaneously and self-alignedly formed in each of the source and drain regions facing each other across the channel region of the FET. To be done. And
At this time, the impurity concentration and the implantation depth in each of the n'regions 11 are adjusted by the setting conditions at the time of ion implantation and the film thickness of the second insulating film 5 located in the middle layer of the dummy gate 8 serving as a mask. It will be. That is, when the film thickness of the insulating film 5 is about 1000 Å, the ion implantation conditions are set to an implantation energy of 150 keV and a dose amount of 5 × 10 ¹³ cm ^-2 . At this time, the distance between the n'regions 11 is determined by the width dimension of the third insulating film 6 located above the dummy gate 8.

Next, after removing the photoresist layer 9,
Annealing is performed under a vapor pressure of As to activate the n ⁺ region 10 and the n'region 11 formed in the source and drain regions of the FET, respectively. Then, as shown in FIG. 2A, a photoresist layer 12 is newly formed over the entire surface of the semi-insulating GaAs substrate 1 and patterned, and then a metal layer 13 to be an ohmic electrode is formed by a vacuum deposition method. It is formed over the entire surface of the semi-insulating GaAs substrate 1. Further, as shown in FIG. 2B, the photoresist layer 12 is removed by using acetone or the like, and the unnecessary portion of the metal layer 13 deposited on the photoresist layer 12 is removed by lift-off, and then the photoresist layer 12 remains. Then, the metal layer 13 to be an ohmic electrode is arrowed.

Next, as shown in FIG. 2C, after newly forming a photoresist layer 14 covering the semi-insulating GaAs substrate 1, a third insulating film 6 located above the dummy gate 8 is formed. Photoresist layer 14 is ashed by RIE until exposed. When the upper portion of the third insulating film 6 is exposed, the dummy gate 8 made of the first to third insulating films 4, 5, 6 is removed by wet etching or RIE as shown in FIG. 3A. .. Subsequently, as shown in FIG. 3B, a metal layer 15 to be a gate electrode is entirely formed by a vacuum deposition method, and then the photoresist layer 14 is removed by using acetone or the like, and the photoresist layer 14 is lifted off. Resist layer 14
When unnecessary portions of the metal layer 15 deposited on the top surface are removed, as shown in FIG.
Thus, the FET having the LDD structure as shown in (c) is formed. In addition, in FIG.
6 indicates a gate electrode, and 17 indicates an ohmic electrode.

In the above description, the annealing for activating the n ⁺ region 10 and the n'region 11 formed in the source and drain regions of the FET respectively is performed.
It is said that the process is performed under the vapor pressure of s, that is, the so-called capless annealing method is used, but the method is not limited to this method, and the n ⁺ region 10 and the n'region 11
It is needless to say that a so-called cap annealing method may be adopted, in which a method for activating implanted ions after forming a protection film for annealing (not shown) covering the above is performed.

[0017]

As described above, L according to the present invention
According to the method of forming the DD structure, ion implantation is not performed using the gate electrode or the sidewall formed in advance as a mask. Therefore, it is necessary to form the gate electrode with a heat-resistant metal or to form the sidewall purposely. As a result, the gate electrode as well as the n ⁺ region and the n'region in the source and drain regions can be formed in a self-aligned and easy manner without the complicated process of the conventional example. Alternatively, the impurity concentration and depth of the n'region can be adjusted by only changing the composition ratio of the first and third insulating films forming the dummy gate, and the gate electrode and the n'region can be adjusted. You will be able to adjust the distance between them. Therefore, it is possible to obtain the excellent effects that the source resistance can be reduced and the gate length can be shortened, and the mutual conductance and the noise can be reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of forming an LDD structure according to a first embodiment of the present invention and showing a process group of a preceding stage thereof.

FIG. 2 is a process sectional view showing a process group in the middle stage.

FIG. 3 is a process cross-sectional view showing a subsequent process group.

FIG. 4 is a cross-sectional view showing an LDD structure in MESFET.

FIG. 5 is a process sectional view showing a method of forming an LDD structure according to a conventional example.

[Explanation of symbols]

4 First Insulating Film 5 Second Insulating Film 6 Third Insulating Film 8 Dummy Gate 10 n ⁺ Region (High Concentration Impurity Region) 11 n ′ Region (Low Concentration Impurity Region)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H01L 21/302 K 7353-4M 21/318 M 8518-4M 27/12 8728-4M

Claims (1)

[Claims] 1. A first insulating film (4) having a high etching rate and a second insulating film (5) having a low etching rate.
And a step of stacking and forming a third insulating film (6) having an intermediate etching rate of both insulating films (4, 5) on the semi-insulating substrate (1) in this order, and Forming a three-layered dummy gate (8) made of an insulating film (4, 5, 6) on the channel region, and forming the dummy gate (8) into a cross-shaped cross section by etching. A step of simultaneously forming a high-concentration impurity region (10) and a low-concentration impurity region (11) in each of the source and drain regions facing each other with the channel region in between by ion implantation using the dummy gate (8) as a mask. And L in a compound semiconductor MESFET characterized by including
A method for forming a DD structure.