JPH01310574A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To simplify a process by a method wherein a selective and continuous ion implantation is performed to make a gate electrode to be of an N or P-type low resistance and to form source and drain regions of a P and an N channel transistors at one time using a gate insulating film as a mask. CONSTITUTION:An continuous ion implantation of impurities 7 and 8 of two different types is performed so as to directly implant more N-type impurity 8 than a P-type impurity 7 into a part which is to be an N-type electrode 4' and another part which is to be a source and drain region 9' of a P channel transistor or implant the P-type impurity 7 selectively into a part which is to be a source and drain region 9 of a P channel transistor indirectly through the intermediary of a gate insulating film 3. As mentioned above, a continuous ion implantation is performed so as to make a Si semiconductor film 4 low in resistance at the formation of the N or P-type gate electrode 4' and form the source and drain regions 9 and 9' of the N and P channel transistor, consequently a process can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing a C-MOS type thin film transistor having both N and two channel transistors on the same insulating substrate.

Conventionally, C-MOS type thin film transistors are generally made of N,
Poly-
A Si semiconductor active layer 2 such as 3i, a-3L (amorphous SL) is formed [Fig. 1 ■], and its surface is thermally oxidized to form a gate insulating film 3 of SiO□ [Fig. 1 ■, Furthermore, a Si semiconductor film 4 for the gate electrode is formed over the entire surface [Fig. This low-resistance film 4 is patterned to form a gate electrode 4' [Fig. 1 ■], and then a part of the P (or N) channel transistor is covered with a resist 6 while leaving the resist 5. By introducing P (or N) type impurity 7 into the active layer portion which will become the source/drain region of the P (or N) channel transistor by ion implantation, the source/drain region of the P (or N) channel transistor is
A drain region 9 is formed [Fig. 1 ■], and after removing the resist, a part of the other transistor is covered with a resist 6, and an N (or P) type impurity 8 is similarly introduced by ion implantation or the like. P) Form the gate electrode 4' and source/drain region 9' of the channel transistor [Fig. 1 (■)], then treat and activate the whole in an oxidizing atmosphere [Fig. 1 (■)], and finally, by the usual method. SiO2 interlayer insulating film lO, contact hole and AΩ in this hole.
It is manufactured by forming a metal electrode 11 as shown in FIG. 1 (■).

In this way, in the past, N type (or P type) electrodes and N type electrodes were used.

Formation of the source and drain regions of a two-channel transistor required three separate ion implantation, vapor phase diffusion, or coating diffusion steps.

Bean-15 The purpose of the present invention is to reduce the resistance of the Si semiconductor film when forming an N- or P-type gate electrode, and to improve the process by performing continuous ion implantation to form the source and drain regions of both N and 2 channel transistors. An object of the present invention is to provide a simplified method for manufacturing a C-MOS type thin film transistor.

(2) There are the following two methods for manufacturing the thin film transistor of the present invention.

(1) After sequentially forming the Si semiconductor active layer, SiO2 gate insulating film, and Si semiconductor film for gate electrodes of both N and 2 channel transistors on the same insulating substrate, the N type gate electrode and the source of both N and 2 channel transistors are formed.・
In a method for manufacturing a C-MOS thin film transistor that includes a step of sequentially forming drain regions, the formation of an N-type gate electrode and the formation of source/drain regions of an N-channel transistor includes a portion that will become the N-type electrode and a portion of the N-channel transistor. Directly so that more N-type impurities are added than P-type impurities in the portion that will become the source/drain region, and selectively in the portion that will become the source/drain region of the P-channel transistor to form the source/drain region of the P-channel transistor. 1. A method for manufacturing a thin film transistor, which comprises performing continuous ion implantation of two different types of impurities indirectly through a gate insulating film so that P-type impurities enter the gate insulating film.

(2) After sequentially forming the Si semiconductor active layer, SiO□ gate insulating film, and Si semiconductor film for gate electrodes of both N and 2 channel transistors on the same insulating substrate, the P type gate electrode and the N and 2 channel transistors are formed. sauce·
In a method for manufacturing a C-MOS thin film transistor that includes a step of sequentially forming a drain region, forming a P-type gate electrode and forming a source/drain region of a P-channel transistor includes a portion that will become the P-type electrode and a portion of the P-channel transistor. Directly so that more P-type impurities are added than N-type impurities in the parts that will become the source and drain regions, and selectively in the parts that will become the source and drain regions of the N-channel transistor to form the source and drain regions of the N-channel transistor. 1. A method for manufacturing a thin film transistor, comprising sequentially performing ion implantation of two different types of impurities indirectly through a gate insulating film so that N-type impurities enter into the thin film transistor.

Methods (1) and (2) of the present invention In the following, the numbers in parentheses indicate the case of method (2). The same applies to the drawings]. To explain this in detail according to the process diagram in FIG. 2, first, Si semiconductors, such as poly-Si, are deposited on the same insulating substrate 1 such as a glass plate at the portions that will become N and P channel transistors using a low-pressure CVD method. For example, SiH, flow rate 40SCCM, vacuum degree 0.5
torr and a temperature of 630°C, for example, the thickness is 200°C.
After forming the SL semiconductor active film with about 0 people in attendance,
A Si semiconductor active layer 2 is formed by patterning by photolithography and etching [Fig. 2].

Subsequently, a gate insulating film 3 made of O5iO□ with a thickness of about 1,500 layers is formed on the surface of the active layer 2 by thermal oxidation.
Figure■ko. Furthermore, as in the case of the active layer, a Si semiconductor, such as poly-5i, which will become the gate electrode, is deposited on the entire surface by low pressure CVD.
The Si semiconductor film 4, which will become the gate electrode, is formed by stacking about 4,000 people to a thickness of about 4,000 using a method or the like [Fig. 2 (■)].

Conventionally, at this point, the N-type (or P-type) resistance of the Si semiconductor film 4 was reduced by ion implantation, coating diffusion, or vapor phase diffusion, but in the present invention, the resistance is reduced to N-type (or P-type) without introducing impurities. A gate electrode pattern is formed using a photophosphorographic etching process. At this time, what is etched using the photoresist 5 is S, which will become the gate electrode.
i Leave only the semiconductor film 4 and the gate insulating film 3 as is [Fig. Next, after removing the photoresist 5, the P (or N) channel transistor region is masked with a photoresist 6, and the gate insulating film in the source/drain region of the N (or P) channel transistor is selectively etched. In this case, if buffered hydrofluoric acid or an aqueous hydrofluoric acid solution is used as the etching solution, the Si semiconductor for the gate electrode can be etched as a mask [Fig. 2 (2)]. After that, if the photoresist 6 is removed, the Si that will become the gate electrode will be exposed.
Semiconductor film 4 and P.

Of the Si semiconductor active layer 2 that becomes the source/drain region of each N channel transistor, only the source/drain region of the P (or N) channel transistor is made of Si.
The state is masked by the gate insulating film 3 of O2 [second
Figure ■]. Subsequently, continuous ion implantation, which is a feature of the present invention, is performed. First, as a P (or N) type impurity 7, for example, B"
(or p”) with energy 80KeV (or 150KeV
V), implanted at a dose of 3×15”/ad.

At this time, B'' (or P'') is the portion 4 and P that will become the gate electrode.

It is implanted into the source/drain regions of the N-channel transistor, but does not pass through the gate insulating film under the gate electrode portion, but passes through the gate insulating film above the source/drain region of the P (or N) channel transistor. It is necessary that the conditions are met. Subsequently, as the N (or P) type impurity 8, for example, As” (or BF”)
is implanted at an energy of 40 KeV (or 50 KeV) and a dose of 6 x 10''/cd.
” (or BF”) is the part that becomes the gate electrode and N (
Or, it is implanted into the source/drain region of the P) channel transistor, but is not implanted into the source/drain region of the P (or N) channel transistor due to blocking by the SiO□ gate insulating film [Second Figure ■] 6 If continuous ion implantation is performed under the above conditions, P (or N) type impurities (B or P”) will be selectively implanted into the source/drain region of the P (or N) channel transistor. The Si semiconductor in this region 9 becomes P (or N) type. In addition, P type impurity B'' (
or BF2+) and N-type impurity As” (or P”)
Both of these impurities are implanted, but the dose of these impurities is
As mentioned above, As") B" (or BF2">P"), so B" (or p") is As" (or BF,
), and gate electrode 4' and N
(or P) The Si semiconductor in the source/drain region 9' of the channel transistor is of N (or P) type. Thereafter, after activation by heat treatment, for example, at 925° C. for 30 minutes, the interlayer insulating film 10 and the AQ electrode 11 are formed by the usual method, and the manufacturing process of the C-MO3 type thin film transistor according to the present invention is completed. Figure 2■].

In this example, as impurities for ion implantation, B'' (or BF2'') is used for P type and As'' (or P+
), but other impurities include P+ and sb'' (or As'' and sb'') for N type, and BF for P type.
, ” (or B”) can be used. In addition, the implantation energy and dose amount vary depending on the thickness of the active layer, gate insulating film, and gate electrode, but usually the active layer is
Polysilicon or amorphous silicon with a thickness of 0 to 10,000 is used as the gate insulating film, with a thickness of 500 to 2,0, respectively.
0.000m thick 0polyx oxide film or SiO2 film made by CVD method,
Further, as the gate electrode, polysilicon having a thickness of 0 to 3,000 to 6,000 is used. B” (or BF2”) implantation energy is 20-100KeV, dose is 5X
10" ~ 5 x 10"/cJ (or I x 10
1s~I x 10'''/cJ), As'' (or p''
) The implantation energy is 20-80 KeV (or 30-2
00KeV), the dose is I x 10" ~ I x
10"/aj (or 5X1014~5Xl01s/a
J) Conditions of degree will be adopted.

However, the doses of P-type and N-type impurities need to be N-type>P-type (or P-type>N-type), and it is preferable that the difference in dose is equal to or greater than IXl01s/aJ.

In the case of the above embodiment, the C-MOS type thin film transistor produced by the method (1) of the present invention has a sheet resistance of the N-type gate electrode of approximately 30 Ω/unit (conventionally 20 to 3° Ω/unit);
The sheet resistance of the N-type active layer is approximately 200 Ω/mouth (previously 15
0-200Ω/mouth), P-type active layer sheet resistance is approximately 800
Ω/mouth (same as conventional), and transistor operation was also good.

Effects Conventionally, the method for manufacturing a C-MO3 type thin film transistor according to the present invention required ion implantation three times. N or P type gate electrode with low resistance and formation of source/drain regions of both P and N channel transistors.
Since ion implantation is carried out at once by selective and continuous ion implantation using the gate insulating film left only on the source and drain regions of the channel transistor as a mask, the process can be significantly simplified. Furthermore, since no resist is used during ion implantation, problems such as resist deterioration and difficulty in removal can be solved.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are manufacturing process diagrams of an example of a conventional C-MO3 type thin film transistor and a C-MO3 type thin film transistor of the present invention, respectively. 1...Support 2...Si semiconductor active layer 3
...Gate insulating film 4...Si semiconductor film or layer 4
'...Gate electrode 5,6...Photoresist 7.8...Impurity 9.9'...Source/drain region 10...Interlayer insulating film 11...Afl electrode 1
Figure 1 Figure Horse 2 Figure

Claims (1)

[Claims] 1. After sequentially forming the Si semiconductor active layer of both N and P channel transistors, the SiO_2 gate insulating film, and the Si semiconductor film for gate electrode on the same insulating substrate, Source of both channel transistors
In a method for manufacturing a C-MOS thin film transistor that includes a step of sequentially forming drain regions, the formation of an N-type gate electrode and the formation of source/drain regions of an N-channel transistor includes a portion that will become the N-type electrode and a portion of the N-channel transistor. Directly so that more N-type impurities are added than P-type impurities in the portion that will become the source/drain region, and selectively in the portion that will become the source/drain region of the P-channel transistor to form the source/drain region of the P-channel transistor. 1. A method for manufacturing a thin film transistor, which comprises performing continuous ion implantation of two different types of impurities indirectly through a gate insulating film so that P-type impurities enter the gate insulating film. 2. After sequentially forming the Si semiconductor active layer of the N and P channel transistors, the SiO_2 gate insulating film, and the Si semiconductor film for the gate electrode on the same insulating substrate, the P type gate electrode and the source layer of the N and P channel transistors are formed.
In a method for manufacturing a C-MOS thin film transistor that includes a step of sequentially forming a drain region, forming a P-type gate electrode and forming a source/drain region of a P-channel transistor includes a portion that will become the P-type electrode and a portion of the P-channel transistor. Directly so that more P-type impurities are added than N-type impurities in the parts that will become the source and drain regions, and selectively in the parts that will become the source and drain regions of the N-channel transistor to form the source and drain regions of the N-channel transistor. 1. A method for manufacturing a thin film transistor, comprising sequentially performing ion implantation of two different types of impurities indirectly through a gate insulating film so that N-type impurities enter into the thin film transistor.