JPS63273362A - Manufacture of schottky barrier gate field-effect transistor - Google Patents

Abstract

PURPOSE:To simplify the manufacturing steps of a GaAsFET of LDD structure by simultaneously ion implanting a section not covered with an insulating film and a section covered with the film to generated a high impurity concentration layer and an intermediate impurity concentration layer. CONSTITUTION:After an N-type GaAs operation layer 21 is formed on a semi- insulating GaAs substrate 11, a gate electrode 31 made of WSi is formed thereon, and SiO2 sidewalls 61 are formed at both sides. Then, a photoresist film, not shown, is formed on an ion implantation unnecessary region, with the region and the electrode 31 as masks Si ions are implanted to form an intermediate impurity concentration N<-> type layer 51 under the sidewall 61. Simultaneously, source and drain regions 141 of deep N<+> type high impurity concentration are simultaneously formed at ion implantation necessary sections, i.e., at both sides of the sidewall 61, and source and drain electrodes 711, 712 are mounted. Thus, the manufacture is simplified to obtain a GaAsFET of LDD structure having characteristics of the same degree as.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor, and more particularly, to a method for manufacturing a field effect transistor, and more particularly, an intermediate impurity having an intermediate impurity concentration is formed between a gate electrode and a high (n+) aperture impurity concentration region. The present invention relates to a method of manufacturing a so-called LDD structure Schottky barrier gate type field effect transistor having an a-degree region.

[Prior Art] In order to improve the characteristics of a Schottky barrier field effect transistor, it is necessary to reduce the series resistance between the gate and the source and between the gate and the drain. For example, in a Schottky barrier field effect transistor (hereinafter referred to as GaAs HESFET) using GaAs, two element structures shown in FIG.
7th Conference on Solid State
Devices & Materials, Tokyo (E
XtendedAbstracts of the 1
7th Conference on 5solidSt
ateDevices and Materials
, Tokyo), 1985. l)p.

4()5-408). First, in FIG. 2(a), the high temperature high carrier concentration region (n layer) 42 is formed by ion implantation using the gate electrode and the insulating film made of 5i02 as a mask, so that the source parasitic resistance or the second Although this is larger than the case shown in FIG. 3(b), it has the advantage that the increase in the short channel effect due to impurity diffusion from the n layer to just below the gate electrode is small.

On the other hand, in Fig. 2 fb), the highly concentrated n+ layer □ is provided in contact with the gate electrode, so although the source resistance is smaller than in Fig. 2 (a), the effect of n+ layer diffusion is This has the disadvantage that the short channel effect becomes larger. As an element structure that suppresses the drawbacks of both (a) and (b) above and takes advantage of the advantages, the region under the insulating film has an intermediate concentration and depth that is intermediate between the n-type channel and the n+ region. LDD structures that form layers are known (
For example, the 18th (1986 International) Conference on Solid State Devices and Materials, Tokyo (Extended A
bstructs of the 18th (198
6International)Conference
on 5solid 5tate Devices a
nd Ha-terials, Tokyo), 19
86. pp. 383-386).

A method of manufacturing a conventional LDD structure@GaAs t-lEsFET will be described with reference to FIG.

In the conventional manufacturing method, as shown in FIG. 3(a), first, an n-type GaAs operating layer 23 is provided on a semi-insulating GaAs substrate 13, and then a thickness of, for example, WSix (X=0.6) is formed. A gate electrode 33 with a thickness of 0.5 mm is formed by dry etching. Next, a 5i02 film was applied to the entire surface to a thickness of 0.
Only 3 chambers were coated, and CF4 was used, and the gas pressure was 80 mTo.
Anisotropic dry etching is performed under conditions of rr and power of 0.9 W/cm to leave an insulating film sidewall 63 at least on the side surface of the gate electrode (FIG. 3(b)). Subsequently, unnecessary parts are covered with a photoresist film (not shown), and Si ions are accelerated using the gate electrode 33, the insulating film side wall 63, and the mask material as masks at an energy tookev and a dose of 3×1.
The high impurity concentration region 43 is implanted under the condition of 0.013 cm-2.
form. Roughly remove the insulating film side wall 63 by etching using 11F, cover unnecessary parts where ions will not be implanted again with a photoresist film, and remove the area where the insulating film side wall 63 was, using the electrode and mask material as a mask. At the bottom, Si ions are accelerated at an energy of 50 keV and a dose of m 1
It is formed by implanting under the condition of 1013 cm-2 (FIG. 3(C)). Further, after removing the photoresist film, annealing is performed for 15 minutes in an sH3 atmosphere at 800° C. to form a high carrier concentration region (n+ layer) 143 and an intermediate carrier concentration region (n' layer) 153. Next, as shown in FIG. 3(d), a source electrode 731 and a drain electrode 732 made of ohmic metal are formed, and GaA
s HESFET is completed.

The conventional method described above requires two ion implantation steps: one to form the n=layer 53 and the other to form the n1i43, resulting in an LDD structure as shown in FIG. There was a problem in that the number of steps was increased compared to the previous FET manufacturing process.

The present invention was made in order to solve the conventional problems as described above, and it is a Schottky barrier gate field effect transistor that can obtain an LO() structure with good reproducibility in a single ion implantation process. The purpose is to provide a manufacturing method.

[Means for Solving the Problems] The present invention includes a step of forming a gate electrode on a semiconductor active layer, a step of forming an insulating film on the entire surface of the semiconductor, and a step of forming the insulating film only near the sidewalls of the gate electrode. At least a portion of the insulating film is left in a process of removal using an anisotropic dry etching method, and selective ion implantation is performed using a mask material formed on the gate electrode and a predetermined portion as a mask, and an intermediate impurity concentration layer is formed under the insulating film. A step of simultaneously forming a high impurity concentration layer in the region not covered with the insulating film, a step of removing the mask material and heating the wafer to zero to activate the implanted impurity, and a step of activating the implanted impurity layer. forming an ohmic electrode thereon.

The insulating film may be made of silicon oxide (5i), for example.
02) or silicon nitride (Si3 N4).

In the present invention, by simultaneously implanting ions into the parts not covered by the insulating film and the parts covered with the insulating film, a high impurity temperature layer is created under the former part, and an intermediate impurity concentration layer is created under the latter part. It is characterized by forming. Therefore, the thickness of the insulating film that should be left near the side walls of the gate electrode is determined by implanting an appropriate amount of ions in the ion implantation process.
an intermediate impurity concentration may be formed;
It is appropriately selected depending on the semiconductor substrate material and the type of insulating film.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(d) are process diagrams showing one embodiment of the method of the present invention.

First, as shown in FIG. 1(a), a semi-insulating GaAs substrate 1
After providing the n-type GaAS operating layer 21 on the
A gate electrode 31 having a thickness of 0.5 mm and made of i x (X = O-6) is formed by dry etching. The gate length was set to one warehouse. Next, apply a 5i02 film to a thickness of 0 on the entire surface.
．． 80mTorr using CF4
, anisotropic dry etching was performed at a power of 0.9 W/cm to form a 5i02 side wall 61 as shown in FIG. 3(b). Next, anisotropic dry etching was performed under the same conditions to form the 5i02 sidewall through film 6 as shown in FIG. 3(C).
4 was formed. This sidewall through film 64 had a film thickness of 0.1 μm on the side in contact with the gate electrode. According to the inventor's experiments, 5i02119B4 at this time has a tapered shape as shown in FIG. 1(C), and becomes thinner as it moves away from the gate, reaching zero film thickness at 0.2 points from the gate end.

Next, areas that do not need to be ion-implanted are covered with a photoresist film (not shown) with a thickness of 1.5 c, and Si ions are accelerated with an energy of 100 KeV and a dose base of 3 x 1013 ctn-2 using the photoresist film and the gate electrode as masks.
When ions are implanted under these conditions, Si ions with reduced energy are implanted under the 5i02 film, and an intermediate impurity temperature region (n' layer) 51 is formed which is shallower and has a lower temperature than the region without the 5i02 film. It is formed. According to LSS theory, the ion implantation profile of 100KeV ion implantation of Si ions into 5i02 has a projected range of 0.1.
084mm, Gaussian part 15 with standard Q deviation of 0.0356mm, and the ion implantation profile into GaAS under the same conditions has a projected range of 0.085mm, standard deviation of 0.042μm.
is a Uth-shaped distribution. Therefore S! In the case of ion implantation through the 02 film, the n' implantation layer becomes shallower and has a lower temperature in the region where the ions are implanted into the 5i02 film than in the region without the 5i02 film.

After roughly removing the photoresist film, As
Annealing is performed for 15 minutes in a t13 atmosphere to form a high carrier concentration region 141 and an intermediate carrier aperture region 151. Next, as shown in FIG. 1(d), a laminated metal film made of AuGe-Ni as an ohmic film is deposited on the source and drain electrode regions according to a pattern formed using photoresist. AuGe-Ni in unnecessary parts
After removing the film by lift-off along with the photoresist,
GaAs HESFE is formed by performing alloying heat treatment to form a source electrode 711 and a drain electrode 712.
T is completed.

As described above, according to the present invention, a region with intermediate carrier concentration can be formed between the gate electrode and the n-high carrier concentration region by a single ion implantation, and the manufacturing process can be simplified.

[Effects of the Invention] As is clear from the above description, according to the present invention, an intermediate concentration region for preventing an increase in source parasitic resistance is implanted between the gate electrode and the high carrier concentration region in a single self-aligned ion implantation process. Since it can be formed simultaneously with the formation of NLL, the manufacturing process is simplified, and it has the effect that a [DD, structure GaAs HESFET] having characteristics as good as conventional ones can be obtained.

[Brief explanation of the drawing]

Figures 1(a) to (C) are process diagrams showing one embodiment of the method of the present invention, Figure 2 is a cross-sectional view schematically showing the structure of a conventional Schottky barrier Guth field effect transistor, and Figure 3 is a process diagram showing an embodiment of the method of the present invention. 1 is a process diagram showing a method of manufacturing a conventional LDD structure Schottky barrier gate field effect transistor; FIG. 11.12.13--Semi-insulating GaAs substrate 21.2
2.23...Active layer 31.32.33...Gate electrode 41.43...High impurity concentration region 42, 141.143...High carrier temperature region 51.
53... Intermediate impurity concentration region 61...5i02 side wall 63... Insulating film side wall 64...5i02 side wall through film 151, 153... Intermediate carrier concentration region 711, 7
21.731...source electrode 712, 722.732
... Drain Electrode Representative Patent Attorney Chieko Tateno Figure 1 Figure 2 Figure 3 Procedure Manual (Method) 7 August 7, 1986 (Figure 1)

Claims (2)

[Claims] (1) forming a gate electrode on the semiconductor active layer;
forming an insulating film on the entire surface of the semiconductor; removing the insulating film by anisotropic dry etching except for leaving at least a portion only near the sidewalls of the gate electrode; and forming the insulating film on the gate electrode and a predetermined portion. A step of performing selective ion implantation using the mask material obtained as a mask to simultaneously form an intermediate impurity concentration layer under the insulating film and a high impurity concentration layer in a region not covered with the insulating film; A Schottky barrier gate field effect transistor comprising the steps of: activating the implanted impurity by heating the wafer; and forming an ohmic electrode on the high impurity concentration layer. manufacturing method. (2) The method for manufacturing a Schottky barrier gate field effect transistor according to claim 1, wherein the insulating film is silicon oxide (SiO_2) or silicon nitride (Si_3N_4).