JPS62166571A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the contact of a source region and a drain region by heat treatment by ion implantation to form the source region and the drain region with a sidewall on the side of a gate electrode as a mask to form an impurity density region. CONSTITUTION:When ions are implanted with a gate electrode 3 formed on a one conductivity type gallium arsenide layer 2 as a mask to form a source region 5 and a drain region 6, a sidewall 91 is selectively formed on the side of the electrode 3, ions are implanted to form the source region 5 and the drain region 6 with the sidewall 91 as a mask to form impurity density regions 51, 61 between the layer 2 of the lower portion of the electrode 3 and the regions 5, 6. Thus, the regions 5, 6 are not contacted by heat treatment in the step of forming the regions 5, 6 to prevent a short channel effect from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is an improvement in a method for manufacturing a gallium arsenide field effect transistor.

In a method for manufacturing a gallium arsenide field effect transistor in which ion implantation is performed using a gate electrode formed on a gallium arsenide layer of one conductivity type as a mask to form a source/drain region in a self-aligned manner, when the gate electrode length is short, In order to prevent the short channel effect from occurring, sidewalls are selectively formed on the sides of the gate electrode, and ions are implanted using this sidewall as a mask to form the source/drain regions. This is a method of manufacturing a gallium arsenide field effect transistor in which an impurity concentration region is formed between the source and drain regions.

[Industrial application field]

The present invention relates to an improved method for manufacturing gallium arsenide field effect transistors. In particular, it relates to improvements that reduce short channel effects.

[Conventional technology]

An example of a process for manufacturing a gallium arsenide field effect transistor according to the prior art will be described with reference to FIGS. 7 to 9.

Refer to FIG. 7. One conductivity type impurity is introduced into a partial region of the semi-insulating gallium arsenide substrate l by ion implantation to a concentration of about 1017 am-3, and the thickness is about 0.15. Region 2 is formed. Since this region 2 of one conductivity type is used as a channel under the gate electrode, its impurity concentration and introduction depth are selected to meet this purpose.

After sputtering tungsten silicide or the like to a thickness of approximately 4,000 mm, a gate electrode 3 having a width of 1 to 2 mm is formed using a dry etching method.

Referring to FIG. 8, the area other than the element formation region is covered with a resist mask 4, and impurity ions of one conductivity type are implanted to increase the impurity concentration of the source region 5 and drain region 6 to about 10<18 >C<-3>.

After removing the resist mask 4 (see FIG. 9), heat treatment is performed to activate the introduced impurities. The depth of one conductivity type in this region is 0
．． It will be 2 to 0.3 ru meal.

A source electrode 7 and a drain electrode 8 made of a gold/germanium/gold layer are formed using a lift-off method.

[Problem that the invention seeks to solve]

In the gallium arsenide field effect transistor manufactured using the above manufacturing method, as shown by B in the graph showing the relationship between threshold voltage and gate length in FIG.
When the gate length is less than 1.5 mm, a short channel effect appears and the threshold value shifts significantly to the negative side, which is a drawback. In other words, the gate length 1.
At 5 JLs or less, a gallium arsenide field effect transistor that operates at desired design values cannot be manufactured with good reproducibility.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback, and to provide a method for manufacturing a semiconductor device that can manufacture a gallium arsenide field effect transistor with a gate length of less than 1IL with good reproducibility.

[Means for solving problems]

The means taken by the present invention to achieve the above object is to form a source region 5 and a drain region 6 by performing ion implantation using the gate electrode 3 formed on the gallium arsenide layer 2 of one conductivity type as a mask. In the method for manufacturing a semiconductor device, a sidewall 91 is selectively formed on the side surface of the gate electrode 3.
, and using this sidewall 91 as a mask, ions are implanted to form the source region 5 and the drain region 6. The gallium arsenide layer 2 of one conductivity type under the gate electrode 3, the source region 5, and the drain region 6 are implanted. An impurity concentration region 51.91 is formed between the region 6 and the region 6.

[Effect]

The short channel effect described above is caused by the side diffusion of impurities during the impurity activation process essential to the process of forming the source and drain regions, which causes the source and drain regions to expand to the bottom of the gate electrode. This is thought to be due to leakage current occurring between the two regions.

Therefore, if appropriate impurity concentration regions are provided between the source region and the gallium arsenide layer of one conductivity type below the gate electrode and between the drain region and the gallium arsenide layer of one conductivity type below the gate electrode. In order to embody the idea that the above drawbacks can be overcome, a sidewall is selectively formed on the side surface of the gate electrode, and this is used as a mask to form a sidewall in the source region.
Ion implantation was performed to form the drain region.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be further described with reference to the drawings.

Refer to Figure 2. N-type impurities are introduced into a partial region of the semi-insulating gallium arsenide substrate l by ion implantation to a concentration of about 1017c+i-3 to form an n-type region with a thickness of about 0.15 h. form 2. This n-type region 2 is used as a channel.

After sputtering tungsten silicide or the like to a thickness of approximately 4,000 mm, a gate electrode 3 having a width of 1 to 2 mm is formed using a dry etching method.

Referring to FIG. 3, a silicon dioxide film 9 is formed to a thickness of 5,000 to 8,000 mm using the CVD method.

A resist mask 4 is used to cover areas other than the element formation area.

Using resist mask 4 as a mask (see Fig. 4), carbon tetrafluoride and 3-1
The silicon dioxide film 9 is etched away using a dry etching method using a mixed gas with fluorocarbon. In this step, the silicon dioxide film 9 selectively remains only on the side surfaces of the gate electrode 3 to form sidewalls 91.

Referring to FIG. 5, using the sidewall 91 as a mask, this step of performing the first ion implantation of n-type impurities may be performed at an acceleration voltage of 175 K eV and a dose of about 2xlo13 cm-2.

Referring to FIG. 6, the sidewall 91 is removed by wet etching, and a second n-type impurity ion implantation is performed using the gate electrode 3 as a mask. This step is performed at an acceleration voltage of 1.5 to 120 KeV with an acceleration voltage of BO to 120 KeV. The introduced n may be heated at a dose of about 2 x 10"cm-2.
Type impurities are activated to form a source region 5 and a drain region 6.

Referring to FIG. 1, the resist mask 4 is removed, and if desired, the silicon dioxide film 9 is removed to form a source electrode 7 and a drain electrode 8 made of a gold/germanium/gold layer.

The gallium arsenide field effect transistor manufactured through the above steps has a gate electrode 3 (n
Since the impurity concentration regions 51 and 61 are interposed between the gallium arsenide layer 2) of the mold and the source region 5 and drain region 6, the length of the gate electrode 3 is as short as 1 to 2 μm layer. First, the heat treatment in the step of forming the source region 5 and drain region 6 prevents the source region 5 and drain region 6 from coming into contact with each other, thereby preventing the short channel effect from occurring.

The experimental results are shown as A in the graph showing the relationship between pinch-off voltage and gate length in Figure 10, and the gate length is 0.8.
It is possible to manufacture gallium arsenide field effect transistors with extremely high reproducibility up to the μ layer.

[Effects of the Invention] As explained above, the method for manufacturing a semiconductor device according to the present invention implants ions using a gate electrode formed on a gallium arsenide layer of one conductivity type as a mask to form a source region and a drain region. In a method for manufacturing a semiconductor device, a sidewall is selectively formed on the side surface of a gate electrode, and using this sidewall as a mask, ions are implanted to form a source region and a drain region. Since an impurity concentration region is to be formed between the gallium arsenide layer of one conductivity type and the source and drain regions, it is unavoidable in the heat treatment in the activation process of impurities introduced into the source and drain regions. Due to the side diffusion that occurs, the source and drain regions do not expand and come into contact with each other, thereby preventing the short channel effect from occurring.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of a gallium arsenide field effect transistor manufactured by implementing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 2 to 6 are cross-sectional views of a substrate after completion of the main steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 7 to 9 are cross-sectional views of a substrate after completion of main steps in a method of manufacturing a semiconductor device according to the prior art. FIG. 10 is a graph (pinch-off voltage versus gate length) showing the drawbacks of the prior art and the effects of the present invention. 1-φ-semi-insulating gallium arsenide substrate, 2...φ one conductivity type (n type) gallium arsenide layer (channel layer),
3rd eye/gate electrode. 4...Resist mask, 5...Source region,
6. First drain region, 51.91... Impurity concentration region, 7... Source electrode, 911... Drain electrode, 9. First silicon dioxide film, 91... Side wall. Process drawing No. 2 cA Process drawing No. 3 Process drawing No. 4 ■ Fig. 5 Process drawing Fig. 6 Present invention Fig. 1 Prior art Fig. 7 Prior art Fig. 8 Prior art Fig. 9

Claims (1)

[Claims] A gate electrode (3) is formed on a gallium arsenide layer (2) of one conductivity type.
), and selectively sidewalls ( ) are formed on the sides of the gate electrode (3).
91), and using the sidewalls (91) as a mask, a source region (
5) and the drain region (6), and the gallium arsenide layer (2) of one conductivity type and the source region (5)/drain region (6) are formed around the gate electrode (3). 1. A method of manufacturing a semiconductor device, comprising forming impurity concentration regions (51) and (61) between.