JPH02197136A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate a work and to improve the reverse withstand voltage characteristics of a device by a method wherein element formation regions are respectively covered with a mask provided with each sidewall on its side surfaces to inhibit the areas of the element formation regions from becoming narrow. CONSTITUTION:A thermal oxide film 2 is formed on the surface of a P-type Si substrate 1 and oxide films 2' only at element formation region parts are left by selective etching. Then, after a thermal oxide film 2'' is grown at a part, from which the film 2 is removed, an Si nitride film 3 is laminated. The film 3 is etched to form sidewalls (SWs) 13 consisting of an Si nitride film on the side surfaces of the films 2'. After boron is ion-implanted in surface parts 1a, field oxide films 5 and channel stopper regions 12 are formed by an oxidation treatment. The films 2' are removed by etching using a photoresist pattern to leave the SWs 13 and the element formation regions A are formed. MOSFETs are respectively formed at these regions A. Gate oxide films 8 are formed, gate electrodes 9 are respectively formed on them, phosphorus is ion- implanted using the electrodes 9 and the SWs 13 as masks to provide source and drain regions 10 and 11 and the SWs 13 are removed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

Conventionally, in a semiconductor device, a field oxide film and a channel bar region formed under the oxide film are provided on the sides of an element formation region in a semiconductor substrate, and a surface portion of the element formation region is provided. There is a semiconductor device in which a source region and a drain region of a semiconductor element (for example, a MOSFET) are formed. This semiconductor device has conventionally been manufactured in the following manner.

Figures 2 (a) to (f) show MOSFE as a semiconductor element.
This article will show you step-by-step how to manufacture a semiconductor device equipped with a T (insulated gate field effect transistor).

First, the creation of an element formation region on a semiconductor substrate will be explained.

As shown in FIG. 2(a), a P-type silicon semiconductor substrate 4
A thermal oxide film 42 with a thickness of about 500 densities was grown on the surface of 1, and then a silicon nitride film 43 with a thickness of about 1000 nitrides was grown in layers by low pressure CVD, and then, as shown in FIG. A photoresist layer 44 is provided in the element formation region, and the resist layer 44 of the silicon nitride film 43 is
Selectively remove portions not covered by plasma etching. Then, as shown in FIG. 2(b), the semiconductor substrate 41 is covered with a mask consisting of a silicon nitride film 43' and a resist layer 44 at a location where the device will be formed.

After forming the mask in this manner, impurity (for example, boron) for a channel stopper is ion-implanted. Of course, it goes without saying that boron is selectively implanted into the non-masked portions. After the ion implantation is completed, the resist layer 44 is removed and selective oxidation processing is performed using the silicon nitride film 43' as a mask. Through this heat treatment, as shown in FIG. 2 (C1), a field oxide film 45 with a thickness of approximately 8,000 nm is formed, the implanted boron is activated, and the channel stopper region 46 under the field oxide film 44 is formed on the semiconductor substrate 41. After that, a silicon nitride film 43' and an oxide film 42 under the same crotch are formed.
By selectively etching away ', an element formation region is completed.

Next, we will explain the fabrication of the MOS FET. First, as shown in FIG. 2(d), after forming a gate oxide film (thermal oxide film) 50 with a thickness of about 500 mm on the surface of the element formation region, As shown in FIG. 2(e), a gate electrode 51 made of polycrystalline silicon is provided on the gate oxide film 50. As shown in FIG. After that, using this gate electrode 51 as a mask, N
A source region 52 and a drain region 53 are formed by ion implantation and thermal diffusion of type impurities (for example, silicon). After that, a source electrode (not shown) and a drain electrode (not shown) are formed to form an N-channel MO3FET.
Once this is completed, the semiconductor device is complete.

[Problem to be solved by the invention]

However, the semiconductor device obtained by the above manufacturing method has a problem that reverse breakdown voltage characteristics are not good. This is because a PN junction is formed by the N layer of both the source and drain regions on the edge side of the element formation region and the channel stopper region outside of it, but this PN junction is a junction with a high impurity concentration, and the reverse bias This is because excessive electric field build-up sometimes occurs.

In addition, the semiconductor device described above also has a problem in that the area of the element formation region is small. This is because when selective oxidation is performed to form a field oxide film, oxidation also progresses in the lateral direction, forming so-called bead barbs under the silicon nitride film, narrowing the device formation area. be.

If the area of the element formation region is small, subsequent processing becomes difficult.

In view of the above-mentioned circumstances, it is an object of the present invention to provide a method for manufacturing a semiconductor device that has a large element formation region, is easy to process afterward, and has improved reverse breakdown voltage characteristics.

[Means to solve the problem]

In order to solve the above problem, in the manufacturing method of the present invention, a field oxide film and a channel stopper region formed under the oxide film are provided on the side of the element formation region in the semiconductor substrate, and In order to obtain a semiconductor device in which a source region and a drain region of a semiconductor element are formed in the surface portion of the formation region, a semiconductor substrate is used in which the element formation region is covered with a mask having a sidewall on the side surface. Using a substrate, the field oxide film and the channel stopper region are formed by supplying channel stopper impurities and heat treatment, and then a mask removal process is performed so that the sidewall remains, and then the source Impurity implantation for forming a region and a drain region is performed with the sidewall remaining.

[For production]

In the manufacturing method of the present invention, when implanting channel stopper impurities, the element formation region is covered with a mask having sidewalls on the sides. This sidewall prevents channel stopper impurities from being implanted at a high concentration at the end of the element formation region. Therefore, there is no channel stopper region with a high impurity concentration at the end of the element formation region, which can prevent the formation of a high impurity concentration PN junction.
Accordingly, the electric field concentration at the PN junction is alleviated and the reverse withstand voltage is improved.

Also when forming a field oxide film, the element formation region is covered with a mask having sidewalls on the sides. Sidewalls on the sides of the mask prevent lateral oxidation and prevent bead barbs from reaching under the mask. Therefore, narrowing of the area of the element formation region can be effectively suppressed.

The sidewalls remain even when impurities are implanted for the source/drain regions, and therefore prevent impurities from being implanted into the edges of the element forming regions. Therefore,
The end portions of the element forming regions in both the source and drain regions are separated from the channel stopper region with high impurity concentration, which prevents the formation of a high impurity concentration PN junction, and the electric field concentration at the PN junction is alleviated accordingly. − layer, the reverse dielectric strength will be improved.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail based on one embodiment thereof.

FIGS. 1(a) to 1(1) show a step-by-step process of manufacturing a semiconductor device in which a MOSFET is provided in an element formation region according to an example of the present invention. As shown in the figure, a thermal oxide film (Si island film) 2 with a thickness of approximately 8,000 wafers is formed by thermal oxidation on the surface of a P-type silicon semiconductor substrate 1.Next, the oxide film 2 is etched using a reactive ion etching method. By applying selective etching,
As shown in FIG. 1(b), only the oxide film 2' in the element forming region is left.

Subsequently, as shown in FIG. 1C, a thermal oxide film 2'' of about 500 layers is grown again on the portion where the oxide film 2 was removed, and then silicon nitride 11ff3 is laminated by low pressure CVD. Next, this silicon nitride film 3 is subjected to reactive ion etching to form a sidewall 13 made of a silicon nitride film on the side surface of the oxide film 2', as shown in FIG. 1(d).Silicon nitride film 3 is thicker on the side surface of the oxide film 2' than on other parts, so it remains locally and forms the sidewall 13. It becomes thinner as you leave the area.

No. Ido Wall 13 refers to the part of the film that remains locally on the side of the step when a film is applied to the surface with a step of a predetermined thickness, and then this film is removed. .

Following the formation of the sidewalls 13, channel stopper impurities (for example, boron) are ion-implanted (supplied) into the surface portion 1a shown in FIG. 1(e).

Boron cannot pass through a certain portion of the oxide film 2'. In Idwall No. 13, impurities pass through the thin portion in an amount inversely proportional to the thickness. As a result, on the lower side of the sidewall 13, the impurity concentration is high in the thinner portion of the sidewall 13, and as the thickness increases (as it approaches the side surface of the oxide film 2'), the impurity concentration decreases.

As can be seen from the above, during ion implantation, the element forming region of the semiconductor substrate 1 is covered with a mask consisting of the oxide film 2' and the sidewall 3.

After the ion implantation, a thermal oxidation process is performed to form a field oxide film 5 and simultaneously activate the implanted impurity to form a channel stopper region (field inversion prevention region) 12, as shown in FIG. Using a photoresist pattern, only the oxide film 2' was removed by etching, leaving the sidewall 13.
), an element formation area A is created. Note that during the thermal oxidation treatment, lateral oxidation is suppressed at the sidewall 13, so that the bead barb hardly penetrates under the oxide film 2', and the element forming region becomes approximately a predetermined area.

Following the creation of the element formation area, M is applied to this element formation area.
Create OS FET.

As shown in Figure 1 (h), gate oxide film (thermal oxide film)
Then, a gate electrode 9 made of polycrystalline silicon is formed on this gate oxide film 8, and using this gate electrode 9 and sidewall 13 as a mask, a MOSFE is formed.
Impurities for forming source/drain regions of T (e.g. phosphorus)
By ion implantation and thermal diffusion, a source region 10 and a drain region 11, which are N-type impurity diffusion regions, are formed in the surface portion of the element formation region. Next, as shown in Figure 1 (1),
While removing the sidewall 13, the source electrode (
(not shown) and a drain electrode (not shown) are provided, an N-channel MOSFET is formed in the element formation region, and the semiconductor device is completed.

When implanting impurities for forming source/drain regions, the sidewalls 13 (and the oxide film portions therebelow) suppress the implantation of impurities into the ends of the element forming regions.

Therefore, a P-type semiconductor region with a not very high impurity concentration exists between the source region 10, drain region 12, and channel stopper region 11, and the electric field at the PN junction is relaxed, further improving the reverse breakdown voltage characteristics. It happens.

The distance between the end of the source region or drain region and the channel stopper region, and the impurity concentration at the end of the channel stopper region are as follows:
Because it depends on the film thickness and shape of the sidewall 13,
By setting the thickness of the silicon nitride film or the reactive ion etching conditions to appropriate values, it is easy to optimize the reverse breakdown voltage characteristic.

This invention is not limited to the above embodiments. For example, the sidewall may be formed of a film other than silicon nitride film. The oxide film 2' may also be a film made of other materials. The channel stopper impurity may be other than boron, and the source/drain region forming impurity may be other than phosphorus.

〔Effect of the invention〕

According to the method for manufacturing a semiconductor device according to the present invention, since the area of the element formation region is not reduced, processing for forming the element is easy, and furthermore, in the completed semiconductor device,
Since the electric field at the junction at the end of the source/drain region is relaxed, the reverse breakdown voltage characteristics are significantly improved.

[Brief explanation of the drawing]

Figure 1+8) to (1) are MOS transistors according to an example of the present invention.
Figures 2(a) to 2(f) are schematic cross-sectional views showing the step-by-step process of manufacturing a semiconductor device with an FET. It is a schematic sectional view without further ado. 1... Semiconductor substrate 2'... Oxide film (mask) 5
...Field oxide film 10...Source region 11
...Drain region 12...Channel stomper L region 13...Side wall A...Element formation region agent Patent attorney Takehiko Matsumoto Month) - 0, 1999 Patent Section No. 5018602 2, Name of the invention 2454 Method of manufacturing a body device 3, Relationship with the case of the person making the amendment Patent applicant address 1048 Kadoma, Kadoma City, Osaka Prefecture Name (583 ) Matsushita Electric Works Co., Ltd. Representative Representative Director Toshio Miyoshi 4, Agent 6, Specification subject to amendment 7, Contents of amendment Bird’s Beebe,” he corrected. ■ “Bead Barb” on page 10, lines 17-18 of the specification
There is no correction to read "Bird's Beebe." 6. As per plate number 1 subject to amendment.

Claims (1)

[Claims] 1. A field oxide film and a channel stopper region formed under the oxide film are provided on the sides of the element formation region in the semiconductor substrate, and a source region and a source region of the semiconductor element are provided on the surface portion of the element formation region. In order to obtain a semiconductor device in which a drain region is formed, a semiconductor substrate in which the element formation region is covered with a mask having sidewalls on the side surface is used as the semiconductor substrate, and a channel stopper impurity is added to the semiconductor substrate. After forming the field oxide film and channel stopper region by supplying and heat-treating, a mask removal process is performed so that the sidewalls remain, and then impurity implantation for forming the source and drain regions is performed. A method for manufacturing a semiconductor device, characterized in that the manufacturing method is performed with sidewalls remaining.