JPH0225040A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of a wiring part by a method wherein a mask having a second opening wider than a first opening is formed on the first opening, an active layer is exposed by etching and a metal layer is adhered in such a way as to fill this active layer with the metal film. CONSTITUTION:An insulating layer 4 is formed on the surface of a semiconductor substrate 1 with an active layer 2 formed thereon. Then, the layer 4 is etched using a first mask 90 having a first opening 92 in a gate electrode formation part to form a first opening 921. Then, the mask 90 is removed and after that, the layer 4 is etched using a second mask 91 having a second opening 93 wider than the opening 92 in the gate electrode formation part to form a second opening 931 and a gate electrode window which is used as an opening whose upper part is wider than its lower part is formed. Then, after a gate electrode 9 which is buried in the gate electrode window and a metal layer 10 on the mask 91 are adhered, the mask 91 and the layer 10 are lifted off. In such a way, a gate length is short and moreover, the sectional area of the gate electrode is increased to make it possible to improve the efficiency of a device and the formation of a wiring part can be also easily conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect transistor.

The purpose is to improve performance and ensure reliability of the gate electrode by shortening the gate length and increasing the area of the upper surface of the gate electrode.

A step of forming an insulating layer 4 on the surface of the semiconductor substrate 1 on which active N2 is formed, and forming a first mask 90 having a first opening 92 in the gate electrode formation portion on the insulating layer; The insulating layer is etched using a mask to form a first opening 9.
21.

After removing the first mask, a second mask 91 having a second opening 93 wider than the first opening in the gate electrode forming portion is formed on the insulating layer, etching the insulating layer using a mask to form a second opening 931 to form a gate electrode window having a wider opening at the top than at the bottom; and etching metal approximately perpendicularly onto the surface of the semiconductor substrate. forming a metal layer 10 on the second mask and the gate electrode 9 deposited and embedded in the gate electrode window;

A method for manufacturing a semiconductor device includes a step of removing the second mask and the metal layer thereon by lift-off.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a field effect transistor.

Field-effect transistors have been improved in performance by shortening the gate length.

As a high-speed field effect transistor, Si
GaA of Schottky gate using the fact that it is higher than
Examples include sMESFET and heterojunction FET.

DCF L (Direct Co
FET Logic) circuits are used in integrated circuits.

FIG. 4 shows a DCFL circuit. This circuit has a normal
An on-type (D-mode) element and a normally-off-type (E-mode) element are used in pairs, and a relatively large current flows through the Schottky gate of the normally-off type element.

Therefore, when the gate length is shortened to improve the performance of the device, the current density of the gate electrode increases, accelerating deterioration and making it difficult to ensure reliability.

Therefore, it is necessary to take measures to ensure reliability.

[Conventional technology]

The structure of a conventional basic GaAs MESFET is shown in FIG. Figures 3(a) and (b) are respectively.

1 is a top view and a cross-sectional view, 1 is a semiconductor substrate, 2 is an active layer,
3 is an element isolation layer, 4 is an insulating layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 11 is a gate finger,
12 represents an external terminal.

Incidentally, a current flows into the gate electrode from the external terminal 12 via the gate finger 11, and when the cross-sectional area of the gate electrode is small, the current density becomes large.

For example, in the case of a CFL circuit as shown in FIG. 4, if 2 mm is supplied to the source electrode, 3 mA of current flows to the gate electrode. If this is converted into current density, the gate length is 0.1
In μm, it is approximately 6×10′ A/am2. This is a fairly large value, and electric field concentration occurs in the part where current flows from the external terminal to the gate finger shown in Figure 3, which accelerates deterioration in that part and may even lead to disconnection, which is a big problem in terms of ensuring reliability. becomes.

[Problem to be solved by the invention]

Therefore, in order to shorten the gate length and reduce the current density, it is desirable to use a gate electrode with a wide top or T-shaped cross section, with a short portion in contact with the active layer and a wide top.

The present invention provides a method for manufacturing a semiconductor device having a gate electrode having such a shape.

[Means to solve the problem]

FIG. 1 is a sectional view of a semiconductor device having a gate electrode formed by the manufacturing method of the present invention, and FIG. 2 shows the manufacturing process thereof.

Means for solving the problem will be described below with reference to the reference numerals in FIGS. 1 and 2.

A step of forming an insulator 1i4 on the surface of the semiconductor substrate 1 on which the active layer 2 is formed, and forming a first mask 90 having a first opening 92 in the gate electrode formation portion on the insulating layer;
etching the insulating layer using a mask to form a first opening 921;

After removing the first mask, a second mask 91 having a second opening 93 wider than the first opening in the gate electrode forming portion is formed on the insulating layer, etching the insulating layer using a mask to form a second opening 931 to form a gate electrode window having a wider opening at the top than at the bottom; and etching metal approximately perpendicularly onto the surface of the semiconductor substrate. forming a metal N10 on the second mask and the gate electrode 9 deposited and embedded in the gate electrode window;

By a method for manufacturing a semiconductor device including the step of removing the second mask and the metal layer thereon by lift-off,
The above problem is solved.

[Effect]

In the present invention, as shown in FIG. 1, the cross-sectional area can be increased by narrowing the part in contact with the gate electrode active N2 and widening the upper surface. When current flows into the gate, the electric field concentration at the connection between the external terminal and the gate finger is alleviated.As a result, deterioration and disconnection are prevented, ensuring high reliability.

Further, by aligning the upper surface of the gate electrode 9 with the upper surface of the insulating layer 4, subsequent processes such as upper layer wiring become easier.

In order to realize such a structure, a second mask 91 is formed with a second aperture 93 wider than the first aperture 92 above the first aperture 92, and etching is performed from that aperture. The active layer 2 is exposed and a gate electrode window is formed which is wider at the top than at the bottom.

Since the metal is deposited so as to bury the gate electrode window, the upper surface of the gate electrode 9 can be aligned with the upper surface of the insulating layer 4.

〔Example〕

Examples of the present invention will be described below with reference to the manufacturing steps shown in FIGS. 2(a) to 2(h).

Refer to FIG. 2(a) 1-A layer with a thickness of 1500 nm is formed on a GaAs semiconductor substrate 1.
- Epitaxially grow a GaAs active layer 2.

After that, approximately 2000 oxygen ions 0+ were added for element isolation.
Ion implantation is performed to a depth to form element isolation N3.

Refer to FIG. 2(b), an insulating layer 4 is formed by depositing 5,000 layers of SiO□ (or 5iON) on the entire surface by chemical vapor deposition (CVD). A mask 5 is formed by depositing photoresist on the entire surface and making holes in the source/drain electrode formation areas. At this time, attach a reverse taper so that the lower opening is wider than the upper opening. The insulating layer is etched using the mask to expose the active layer 2.

Next, ohmic metal (AuGe) is applied vertically to the entire surface.
200 Au/4800 Au) is deposited to form the ohmic metal layer 6.

Referring to FIG. 2(c), when the mask 5 and the ohmic metal layer 6 on it are lifted off, the ohmic metal (AuGe200) is formed on the active layer 2.
A source electrode 7 and a drain electrode 8 having Au/4800 Au) are formed.

Referring to FIG. 2(d), an EB resist film is deposited on the entire surface, and a first opening 92 with a width of 0.2 μm is made in the film by electron beam exposure to form a first mask 90.

The insulating layer 4 is etched from the opening by anisotropic dry etching to form a first opening 921.

The etching may be stopped halfway through the insulating layer, or may be continued until the active N2 is exposed.

Refer to FIG. 2(6) After removing the first mask 90, a resist film is again deposited on the entire surface.

The width of the opening on the top surface is 1 in the film above the first opening 921.
A second mask 91 is formed by opening a second opening 93 of an inversely tapered type, the width of which is larger on the lower surface by .mu.m.

Referring to FIG. 2(f), the insulating layer 4 is etched through the second opening by reactive ion etching to expose the active layer 2.

A second opening 931 is formed to serve as a gate electrode window.

Next, recess etching is performed to adjust the thickness of the active layer 2 under the gate.

Referring to FIG. 2(g), Al is deposited as a gate metal over the entire surface to a thickness of 4000 nm. This thickness is determined by the gate electrode 9 formed on the active layer 2.
The height is selected so that the upper surface of the insulating layer 4 is at the same height as the upper surface of the insulating layer 4.

A metal layer 10 is formed on the second mask 91.

Referring to FIG. 2(h), the second mask 91 and the metal layer 10 thereon are removed by lift-off.

Thus, the top surface of the gate electrode 9 is flush with the top surface of the insulating layer, and the top surfaces of the source electrode 7 and the drain electrode 8 are also flush with each other, and the length of the gate in contact with the active layer 2 is set to 0.2 μm.
A field effect transistor with a gate electrode upper surface width of 1 μm is realized.

〔Effect of the invention〕

As explained above,8 according to the present invention,2 the gate length is shortened2 and the cross-sectional area of the gate electrode is increased, thereby improving performance, and moreover, it can withstand large gate currents7 and the upper layer of the device is flat. This makes it possible to realize a highly reliable field-effect transistor with easy upper layer wiring, which will greatly contribute to the development of high-speed integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device. Figure 2 shows the manufacturing process. Figure 3 shows the structure of GaAs MESPET. Figure 4 shows the DCFL circuit It is. In fig. ■ is a semiconductor substrate. 2 is the active layer. 3 is an element isolation layer. 4 is an insulating layer. 5 is a mask. 6 is an ohmic metal layer. 7 is the source electrode. 8 is the drain electrode. 9 is a gate electrode. 90 is the first mask. 91 is the second mask. 92 is the first opening. 921 is the first opening. 93 is the second opening. 931 is a second opening. 10 is a metal layer. 11 is the gate finger. 12 is an external terminal Cross-sectional view of Homare conductor device Figure 1 Shocking) Manufacturing process Figure 2 (1,000 2) a+m top view (a) A-A sectional view (b) G, zAsMESFET7>horizontal 1 $3 figure

Claims (1)

[Claims] A step of forming an insulating layer (4) on the surface of the semiconductor substrate (1) on which the active layer (2) is formed; A mask (90) is formed on the insulating layer, and the insulating layer is etched using the first mask to form a first opening (921).
), and after removing the first mask, a second mask (91) having a second aperture (93) wider than the first aperture is provided in the gate electrode forming part. A step of forming a gate electrode window on the insulating layer and etching the insulating layer using the second mask to form a second opening (931) so that the opening is wider at the top than at the bottom. and a gate electrode (9) buried in the gate electrode window by depositing metal almost vertically on the surface of the semiconductor substrate and the second gate electrode (9).
A method for manufacturing a semiconductor device, comprising: forming a metal layer (10) on a second mask; and removing the second mask and the metal layer thereon by lift-off.