JPH02296343A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPH02296343A JPH02296343A JP11610489A JP11610489A JPH02296343A JP H02296343 A JPH02296343 A JP H02296343A JP 11610489 A JP11610489 A JP 11610489A JP 11610489 A JP11610489 A JP 11610489A JP H02296343 A JPH02296343 A JP H02296343A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- channel layer
- region
- gaas substrate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000007257 malfunction Effects 0.000 abstract description 4
- 238000013459 approach Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はメタルショットキ接合型の電界効果トランジス
ク(MESFET)に関し、特にデー1〜リーク電流の
低減を図った電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal Schottky junction field effect transistor (MESFET), and particularly to a field effect transistor with reduced leakage current.
〔従来の技術]
一般に、ショットキ接合型の電界効果I・ランジスタは
、半導体基板の表面にチャンネル層(活性層)を構成し
、かつこのチャンネル層においてショットキ接合を構成
するゲート電極としてのメタルを半導体基板上に形成し
た構成となっている。[Prior Art] In general, a Schottky junction type field effect I transistor has a channel layer (active layer) formed on the surface of a semiconductor substrate, and a metal serving as a gate electrode forming a Schottky junction in this channel layer is made of a semiconductor. The structure is formed on a substrate.
この場合、通常ではゲート電極の平面幅寸法をチャンネ
ル層の平面幅寸法よりも大きく形成してゲート電極がチ
ャンネル層上で延在されるように構成し、かつゲート電
極の一部を配線または電極として構成するために、チャ
ンネル以外の領域で大面積に形成する構成となっている
。In this case, the planar width of the gate electrode is usually formed to be larger than the planar width of the channel layer so that the gate electrode extends on the channel layer, and a part of the gate electrode is connected to wiring or electrodes. In order to configure it as a channel, the structure is such that it is formed over a large area in a region other than the channel.
[発明が解決しようとする課題]
上述した従来の電界効果トランジスタでは、ゲート電極
がチャンネル層以外の領域でも半導体基板に直接接触さ
れているために、次のような問題が生じている。[Problems to be Solved by the Invention] In the conventional field effect transistor described above, the following problems occur because the gate electrode is in direct contact with the semiconductor substrate even in areas other than the channel layer.
例えば、GaAs半導体の集積回路を構成する場合、形
成した電界効果トランジスタの近傍にある他の素子の電
極よりデー1〜電極にリーク電流が流れる。このリーク
電流がある程度大きいと、電界効果トランジスタのチャ
ネル層下部のトラップ準位番こ電子または正孔を注入し
、これによってチャネル層の厚さを変調し、その結果電
界効果トランジスタのスレッショルド電圧を変化させる
ザイドゲート効果と称される現象が引き起こされる。For example, when forming a GaAs semiconductor integrated circuit, a leakage current flows from the electrodes of other elements in the vicinity of the formed field effect transistor to the electrodes 1 to 1. When this leakage current is large enough, it injects electrons or holes into the trap level at the bottom of the channel layer of the field effect transistor, thereby modulating the thickness of the channel layer and, as a result, changing the threshold voltage of the field effect transistor. This causes a phenomenon called the Seidgate effect.
このGaAs半導体では電子トラップが主であり、外部
からの負電位による電子の注入によりチャネルを狭窄し
、スレッショルド電圧を小さくする。In this GaAs semiconductor, electron traps are the main feature, and the channel is narrowed by injection of electrons due to an external negative potential, thereby reducing the threshold voltage.
これを防止するためには、ゲート電極がチャンネル層以
外で半導体基板に直接接触される面積を小さくすればよ
いが、電界効果トランジスタを他の素子に接続するため
にはその面積に所要以上の大きさは必要であり、上述し
たリーク電流を抑制することは難しいという問題がある
。In order to prevent this, it is possible to reduce the area where the gate electrode is in direct contact with the semiconductor substrate other than the channel layer, but in order to connect the field effect transistor to other elements, the area must be larger than necessary. However, there is a problem in that it is difficult to suppress the leakage current described above.
本発明は上述したリーク電流を抑制した電界効果トラン
ジスタを提供することを目的とする。An object of the present invention is to provide a field effect transistor in which the leakage current described above is suppressed.
本発明の電界効果トランジスタは、半導体基板に設けた
チャンネル層上にショットキ接合のケート電極を設けた
電界効果トランジスタにおいて、前記チャンネル層以外
の領域における半導体基板表面とデー1−電極との間に
絶縁膜を選択的に形成している。The field effect transistor of the present invention is a field effect transistor in which a gate electrode of a Schottky junction is provided on a channel layer provided on a semiconductor substrate, in which insulation is provided between the semiconductor substrate surface and the D1-electrode in a region other than the channel layer. The film is selectively formed.
[作用]
この構成では、ゲート電極がチャンネル層以外の領域で
半導体基板に直接接触されることが防止でき、この領域
におけるゲート電極と半導体基板との間のリーク電流を
抑制する。[Function] With this configuration, the gate electrode can be prevented from coming into direct contact with the semiconductor substrate in a region other than the channel layer, and leakage current between the gate electrode and the semiconductor substrate in this region can be suppressed.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示しており、同図(a)は
平面図、同図(b)はその八−A線に沿う拡大断面図で
ある。図において、半絶縁性GaAs基板1の表面所要
領域にはチャンネル層3を形成しており、この上にショ
ットキ接合を構成するメタルによりゲート電極4を形成
している。このゲート電極4は前記チャン矛ル層3上で
は、所定のゲート長さでチャンネル層3の全幅方向にわ
たって形成し、かつその一部をチャンネル層3の隣接領
域において大面積に形成し、他の素子との接続用電極と
して構成している。そして、前記チャンネル層3以外の
領域で、かつゲート電極4の下側には、GaAsJJ板
1の表面との間にシリコン窒化膜2を選択的に形成し、
この領域においてゲート電極4とGaAs基板1との直
接接触を防止している。FIG. 1 shows an embodiment of the present invention, in which FIG. 1(a) is a plan view and FIG. 1(b) is an enlarged sectional view taken along line 8-A. In the figure, a channel layer 3 is formed in a required area on the surface of a semi-insulating GaAs substrate 1, and a gate electrode 4 is formed thereon from a metal constituting a Schottky junction. This gate electrode 4 is formed on the channel layer 3 with a predetermined gate length over the entire width direction of the channel layer 3, and a part thereof is formed in a large area in an area adjacent to the channel layer 3, and the other part is formed in a large area in an area adjacent to the channel layer 3. It is configured as an electrode for connection with an element. Then, in a region other than the channel layer 3 and below the gate electrode 4, a silicon nitride film 2 is selectively formed between it and the surface of the GaAsJJ plate 1,
Direct contact between the gate electrode 4 and the GaAs substrate 1 is prevented in this region.
第2図は、その製造方法の工程一部を示す第1図(b)
と同様の断面図である。Figure 2 is Figure 1(b) showing a part of the manufacturing method.
It is a sectional view similar to.
先ず、半絶縁性GaAs基板1にシリコン窒化If!J
2を300人堆積した後、フォI・レジスト5によるリ
ソグラフィ法によりチャネル層のパターンを形成し、C
F、とH2の混合ガスを用いた反応性イオンエツチング
法により開口部のシリコン窒化膜2を除去し、Si′イ
オンをイオン打込み法で注入し、チャンネル層3を形成
する。その後、希釈した弗酸で処理し、シリコン窒化膜
2をフォトレジスト5により0,2〜0.5μm・す”
イドエツチングする。First, silicon nitride If! is applied to a semi-insulating GaAs substrate 1. J
After depositing 300 layers of C.2, a channel layer pattern was formed by lithography using FoI resist 5, and C.
The silicon nitride film 2 at the opening is removed by reactive ion etching using a mixed gas of F and H2, and Si' ions are implanted by ion implantation to form a channel layer 3. After that, it is treated with diluted hydrofluoric acid, and the silicon nitride film 2 is coated with a photoresist 5 to a thickness of 0.2 to 0.5 μm.
Etching.
次に、フナ1〜レジスト5を除去し、全面にタングステ
ンシリサイド4を被着し、別のフ第1・レジストによる
リソグラフィ法でゲートパターンを形成し、CF 4と
SF、の混合ガスによる反応性イオンエツチングでデー
1〜電極4を形成ずろ。Next, the film 1 to the resist 5 are removed, tungsten silicide 4 is deposited on the entire surface, a gate pattern is formed by lithography using another film 1 and the resist, and a reactive layer is formed using a mixed gas of CF 4 and SF. Form electrodes 1 to 4 by ion etching.
したがって、この構成の電界効果トランジスタによれば
、チャンネル層3においてはゲート電極4がGaAs5
板1に直接接触してショットキ接合を構成するが、チャ
ンネル層3以外の領域ではシリコン窒化膜2によってゲ
ート電極4とGaAs基板1との直接接触が防止される
。これにより、チャンネル層3以外の領域におけるゲー
ト電極4とGaAs基板l基板間のリーク電流が抑制で
き、回FI!!誤動作を防止する。Therefore, according to the field effect transistor having this configuration, in the channel layer 3, the gate electrode 4 is made of GaAs5.
A Schottky junction is formed by direct contact with the plate 1, but direct contact between the gate electrode 4 and the GaAs substrate 1 is prevented by the silicon nitride film 2 in regions other than the channel layer 3. This makes it possible to suppress the leakage current between the gate electrode 4 and the GaAs substrate in the region other than the channel layer 3, thereby reducing the FI! ! Prevent malfunction.
なお前記実施例では、デー1−電極5とGaAs基板1
との絶縁分離にシリコン窒化膜を用いたが、他の絶縁膜
、例えばSiO□、 A I N、 S i 0XN
Vを用いてもよい。また、本発明はC’aAs基板のみ
ではなく、Siや他の化合物のメタルショットキ接合型
の電界効果トランジスタの全てに適用することができる
。In the above embodiment, the data 1-electrode 5 and the GaAs substrate 1
Although a silicon nitride film was used for insulating isolation from the
V may also be used. Further, the present invention can be applied not only to C'aAs substrates but also to all metal Schottky junction field effect transistors made of Si or other compounds.
以上説明したように本発明は、チャンネル層以外の領域
において、ゲート電極の下に絶縁膜を選択形成してゲー
ト電極と半導体基板との直接接触を防止しているので、
この領域におげろケ−1・電極と半導体基板との間のリ
ーク電流を抑制し、集積回路において素子が接近する場
合にも、回路誤動作の原因となるザイトゲー[・効果を
防止できる効果がある。As explained above, in the present invention, an insulating film is selectively formed under the gate electrode in a region other than the channel layer to prevent direct contact between the gate electrode and the semiconductor substrate.
This area has the effect of suppressing leakage current between the electrode and the semiconductor substrate and preventing the xytoge effect that causes circuit malfunctions even when elements are brought close together in an integrated circuit. .
第1図は本発明の一実施例を示しており、同図(a)は
平面口、同図(b)はその八−Δ線に沿う拡大断面図、
第2図は製造方法の工程一部を示す第1図(b)と同様
の断面図である。
1・・・半絶縁性GaAs基板、2・・・シリコン窒化
膜、3・・・チャンネル層、4・・・ケート電極、5・
・・フオl〜レジスト。
!−一
綜FIG. 1 shows an embodiment of the present invention, in which (a) is a plan view, (b) is an enlarged sectional view taken along line 8-Δ,
FIG. 2 is a sectional view similar to FIG. 1(b) showing a part of the manufacturing method. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... Silicon nitride film, 3... Channel layer, 4... Kate electrode, 5...
...Fol~Resist. ! −Issho
Claims (1)
合のゲート電極を設けた電界効果トランジスタにおいて
、前記チャンネル層以外の領域における前記半導体基板
表面とゲート電極との間に絶縁膜を選択的に形成したこ
とを特徴とする電界効果トランジスタ。1. In a field effect transistor in which a Schottky junction gate electrode is provided on a channel layer provided on a semiconductor substrate, an insulating film is selectively formed between the semiconductor substrate surface and the gate electrode in a region other than the channel layer. A field effect transistor characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11610489A JPH02296343A (en) | 1989-05-11 | 1989-05-11 | Field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11610489A JPH02296343A (en) | 1989-05-11 | 1989-05-11 | Field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02296343A true JPH02296343A (en) | 1990-12-06 |
Family
ID=14678799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11610489A Pending JPH02296343A (en) | 1989-05-11 | 1989-05-11 | Field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02296343A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07297386A (en) * | 1994-04-27 | 1995-11-10 | Nec Corp | Compound semiconductor device |
-
1989
- 1989-05-11 JP JP11610489A patent/JPH02296343A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07297386A (en) * | 1994-04-27 | 1995-11-10 | Nec Corp | Compound semiconductor device |
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