JPS60117678A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effect automatic alignment as necessary between a high electron density layer forming a source, drain and a gate Schottky contact in a fine- structure FET by a method wherein holes are provided for a source, drain, gate in an insulating film covering a dynamic layer. CONSTITUTION:An insulating film 11 is deposited on a dynamic layer 1a formed on a semi-insulating substrate 1, a source opening 13s, drain opening 13d, gate opening 13g are provided through a photoresist film 12 at locations whereat electrodes are to be built, and then ion implantation is performed for the formation of high electron density layers 14s, 14d, 14g. The photoresist film 12 is removed and then metal electrodes 15s for source, 15d for drain are built in the high electron density layers 14s, 14d. A process follows wherein the high electron density layer 14g is removed by ethcing for the formation of a gate metal electrode 15g. During this process, the position of Schottky contact is determined by the gate opening 13g, which means that a minor dislocation after alignment does not affect performance characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for reducing electrode contact resistance and setting a gate formation region in a finely structured field effect transistor.

[Technical background of the invention and its problems]

Below, a gallium arsenide (GaAs) crystal will be explained using a Schottky Noveria gate field effect transistor (hereinafter abbreviated as FET) as an example.

In order to improve the characteristics of low-noise power FETs, it is important to minimize the resistance of parasitic elements such as channel resistance and contact resistance of ohmic electrodes. A high electron concentration layer is placed under the drain electrode. This high electron concentration layer can be formed by vapor phase growth or ion implantation, but the use of ion implantation technology is particularly effective in suppressing in-plane variations in concentration and thickness when using large-diameter wafers. Furthermore, it is easy to selectively form using a mask, and has become a commonly used technique in recent years.

A typical FET manufacturing method using ion implantation technology is shown in FIGS. 1(a) to 1(b).

First, as shown in Figure (a), a GaAs semi-insulating substrate (
After performing ion implantation on 1) to form an N-type behavior (la), as shown in Figure (b), a photoresist film (2) is formed.
The source and drain regions are drawn by lithography, and ions are implanted using this as a mask to form a high electron concentration layer (3). As shown in Figure (C), the high electron concentration layer in the source and drain regions is (3) Metal electrodes (4), (5) on top
) is formed and heated to form an ohmic contact, and then a gate electrode (6) is formed between the source and drain electrodes as shown in FIG. 1(d).

At this time, the alignment of the gate electrode is performed with respect to the source, drain electrode, or high electron concentration layer, but misalignment is generally unavoidable, and when the distance between the high electron concentration layers becomes small, the gate electrode It is also possible that the electrons come into contact with the high electron concentration layer. For power FET, F shown in figure (d)
A large number of ETs are operated in parallel as a unit, but if a deviation from the desired position with respect to the gate electrode occurs, for example, as shown in FIG. The second gate electrode (6b
) is located away from the source electrode (4b), and the individual FETs have uniform characteristics. This FET, in which these characteristic values are combined, has uniform characteristics. It has been revealed that the characteristic value of this FET, which is a combination of these characteristic values, is inferior to the characteristic value of the FET when there is no positional deviation.

In order to eliminate the above problems, there is an improved manufacturing method shown in FIGS. 3(a) and 3(b). As shown in Figure (a), a gate electrode (6c) is first formed on a semiconductor substrate that has an active layer and is the same as before, and ions are implanted using this as a mask, and the implanted ions are activated by a high nose treatment. High electron concentration layers (3), (3) are formed on both sides of the gate electrode. Next, as shown in Figure (b), a high electron concentration layer (
3), forming a source electrode (4) and a drain electrode (5) on (3) to achieve manufacturing.

According to the above manufacturing method, the high electron concentration layer is automatically and always formed close to the gate electrode, so it is difficult to use it in power FETs that operate at high voltages, and the number of devices to which it can be applied is also limited.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned problems, and it is possible to automatically make the gate I-shot contact with the high electron concentration layer of the source and drain in a finely structured FET at a desired position. It is an object of the present invention to provide a method of manufacturing hair that allows alignment.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes a step of forming an active layer on one main surface side of a high resistivity semiconductor substrate;
a step of depositing an insulating film on the active layer and opening holes in the regions where the source and drain regions are to be formed and holes set at desired correlation positions with respect to each of these regions; a step of implanting ions into the opening to form a low resistivity layer shallower than the active layer; a heating step for activating the implanted ions; a source of the insulating film;
A step of forming a metal electrode in the drain hole and then heating it to bring it into ohmic contact; and a step of etching away the low resistivity layer in the gate hole of the insulating film to form a shuttling type metal electrode. It consists of

[Embodiments of the invention]

Next, one embodiment of the present invention will be described with reference to the drawings.

The manufacturing process is shown in FIGS. 4(a) to 4(d). Si+ ions are implanted into a GaAs semi-insulating substrate (1) to form an N-type operating layer (1a). This ion implantation is 4X 3128
10I2c+n-2゜Implemented under the conditions of 500KeV,
The expected electron concentration peak value and its depth are approximately I
XIO"cm-3,4400 people (Figure (a)).

Next, silicon nitride (SiN) (i') insulation [(11)
Deposit at A photoresist film (1
2), the source, drain, and gate 1 are drawn, and the insulating film in the resist hole is chemically etched (
CDE) method, and holes are formed in the area where electrodes are to be formed, forming a source hole (13g), a drain hole (13d),
A gate opening (13g) is provided to expose the GaAs surface in the core (Figure (b)). Next, ions are implanted into each opening to form high electron concentration layers (14g), (14d), (
14g).

This injection condition is 51211 at 2 x 1013c+m-
The key point of this invention is to implant at 2,60 KeV and to form the estimated peak concentration approximately 500 m from the surface, which is shallower than the N-type active layer (1a). Next, the photoresist is removed using a plasma ashing device, and high-temperature annealing is performed in an arsenic atmosphere while leaving the insulating film (11). This annealing condition was performed at 850° C. for 15 minutes.

Next, source and drain openings (13s) (13d)
High electron concentration layer (14s) exposed to (14s) = metal mold 11 (15s) to (14d).

(15d) is formed. This metal is AuGc (Ga
l holes%) were formed by lift-off to a thickness of 1000 mm. Next, the AuGe metal electrode was heat-treated at 400° C. for 30 seconds in a hydrogen atmosphere to form ohmic contact (Figure (C)).

Next, the high electron concentration layer (14g) formed in the gate opening (13g) (Figure (C)) is removed by etching, and with appropriate current control, the aluminum electrode of the gate is removed by lift-off using photoresist. (15g) to 1μm
Form to a thickness of . At this time, alignment is performed with the gate opening shown in FIG. 3(c), but since the position of Schottky contact is determined by the gate opening, a slight misalignment does not pose a problem in terms of characteristics.

In this example, the size of the gate opening shown in Figure (b) is approximately 0.5 μm, and the high electron concentration layer (13 g) is
, (13d) is designed to be 4μ4. figure(
The upper dimension of the gate electrode (15g) shown in d) is 2μm
Therefore, it is sufficient to align the pattern so that it covers the 0.5μ river, and there is no major difficulty. (Figure (d)).

Next, the method for forming the gate electrode (15g) according to the present invention may be performed as follows. That is, Fig. 4 (c
), a metal layer that will become the gate electrode is deposited over the entire surface, and the regions between the high electron concentration layers are covered with resist and etched.

Further, side etching of the metal layer under the resist coating is performed toward the gate opening (13g). In this way, the size of the upper part of the gate electrode (15g) in Figure (d) can be further reduced. That is, since the area of the electrode formed on the insulating film is made as small as possible, it is effective in reducing the parasitic capacitance that the gate electrode has with respect to the insulating film.

In addition, in this invention, in the feature of forming the high electron concentration layer shallower than the N-type active layer, in order to realize the position of the peak concentration peculiar to ion implantation near the surface of the crystal with good controllability, for example, as shown in FIG. Ion implantation may be performed after a thin film of metal such as titanium or aluminum is deposited on the entire surface of the semiconductor substrate having the structure shown in b).

〔Effect of the invention〕

As described above, according to the present invention, the position of the gate Schottky contact with the high electron concentration (low resistivity) layer in the source and drain electrode regions can be automatically determined at a desired position. Formation of a high electron concentration layer using ion implantation technology is applied to FET devices for many purposes.
Especially in power FETs, in order to perform high voltage operation,
It is necessary to increase the distance between the gate electrode and the high electron concentration layer in the drain electrode region, and conversely, it is effective for improving performance to bring the gate electrode closer to the source electrode region.

Furthermore, in order to operate a large number of FETs in a unit in parallel, it is necessary for each FET to have uniform characteristics, that is, to improve the characteristics, it is necessary to have a structure in which the electrodes are not formed out of position. be.

This invention solves all the problems that cannot be overcome with conventional manufacturing methods, including various effects of slanting.

[Brief explanation of the drawing]

Figures 1 (a) to (d) are cross-sectional views showing the conventional manufacturing method of FET in the order of steps, Figure 2 is a cross-sectional view showing a part of a power FET, and Figures 3 (a) and (b). ) is FET
Both are cross-sectional views showing the conventional manufacturing method in order of steps. FIGS. 4(a) to 4(d) show an F according to an embodiment of the present invention.
All are cross-sectional views showing the method for manufacturing ET in the order of steps. In addition, in FIG. 1, the same reference numerals indicate the same or corresponding parts. 1... Semi-insulating substrate la... Active layer 11... Insulating layer 13 (5, g, d)... Opening part (source, gate, drain) 14 (s, g, d)... High electron concentration layer (source, gate, drain) 15 (s', g, d)... Electrode (source, gate, drain) agent Patent attorney I
Top - Male Fig. 1 (d), l l (mun/d @ Fig. 2 Fig. 3 d Fig. 4 (υ) (b) - /4s Pot 〆

Claims (1)

[Claims] A step of forming an active layer on one main surface side of a high resistivity semiconductor substrate, depositing an insulating film on the active layer, and applying a source layer to the active layer.
A step of opening holes in each region of the drain region and a region of the gate region set at a desired relative position with respect to each region, and implanting ions into the openings to form a low-ratio layer shallower than the active layer. a step of forming a resistance layer; a heating step for activating the implanted ions; and a step of forming metal electrodes in the source and drain openings of the insulating film and then heating them to bring them into ohmic contact. . A method for manufacturing a semiconductor device, comprising the steps of: etching away the low resistivity layer in the gate opening of the insulating film to form a Schottky-type metal electrode.