JPS59119764A - Manufacture of field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET of a high output excellent in high frequency characteristics by a method wherein the mask of a large window is superposed on an insulation or semi-insulation GaAs series substrate, after ion implantation by means of the mask of a small window, and then a Schottky electrode is formed, which electrode is employed as a mask. CONSTITUTION:An Al mask 34 is applied by superposing an Al N film 32 and an SiO2 film 33 on the fixed GaAs series substrate 31, successively windows are bored through the films 32 and 33 by reactive ion etching, and an N-channel 36 is formed by implanting Si ions. Next, a hollow part 37 is formed by etching the film 33 on the side surface by isotropic etching, and an electrode 38 and a film 39 of WSi are formed by a magnetron sputtering method. The film 39 is exfoliated by removing the films 33 and 34 by etching. The electrodes 38 has the channel length Lg determined by the window of the film 32, and is placed on the film 32 by the width DELTAL, and its peripheral edge makes a slope. N-layers 41 and 42 are provided by Si ion implantation with a resist 40 and the electrode 38 as masks. Thereafter, the device is completed by attaching ohmic electrodes 43 and 44, an SiO2 film 45, and the upper layer wiring 46. This constitution enables to obtain a desired FFT with good controllability.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a field effect semiconductor device, and in particular to a method for manufacturing a Schottky Boot field effect transistor (SBF'ET) made of a gallium arsenide (GaAg) compound semiconductor. be. The present invention can be applied to the manufacture of GaAs SBFET integrated circuits (ICs).

(2) Background of the technology GaAa Schottkygut field effect transistors have excellent high frequency characteristics and can achieve high output, so research and development have progressed and they have been put into practical use. Previously, buffer layers and active layers were epitaxially grown on semi-insulating GaAa substrates.
A cathode electrode with Schottky characteristics was made of aluminum (At). In recent years, the active layer has been formed by ion implantation, and since it is necessary to perform annealing (high temperature heat treatment, approximately 800°C) after ion implantation, heat-resistant TiW silicide, which is an alternative to the previous gate electrode material, has been used. Schottky conductive materials such as W silicide or W (tungsten) have come into use. GaAs ion implanted selectively into the region corresponding to the active layer
After forming a silicide gate electrode on the substrate, ion implantation is performed to form source and drain regions using the dirt electrode as a mask, and annealing is performed to form ohmic contact source and drain electrodes. In this way G
Although aAs Schottky field effect transistors are manufactured, there are problems in practical use.

(3) Prior art and problems The conventional manufacturing process of a GaAg shot gate field effect transistor using ion implantation as described above is the first step.
This will be explained with reference to FIGS. 7 to 7.

As shown in FIG.
A resist layer 2 is formed by applying photoresist and developing and removing the portion corresponding to the field effect transistor region. Using this Renost layer 2 as a mask, silicon (s+) ions are implanted (with an implantation energy of 60 keV and a dose of 2 x 1012 crn-2) to form a low-concentration layer containing a channel layer in the GaAs substrate 1. An ion implantation region 3 is formed.

Next, after removing the resist layer 2, a heat-resistant G
A conductor, such as tungsten (W) silicide, which constitutes a Schottky contact with the aAs substrate is formed on the entire surface of the GaAs substrate 1, and a dirt electrode 4 (for example, thickness 0.4 μm, am2) remains by photoetching. Then remove the other parts (Figure 2). When this W silicide is etched using carbon tetrafluoride (CF4) as an etchant or by active ion beam etching, the exposed GaAs substrate 1 is slightly tilted to the side due to ion bombardment near the end of etching, and the substrate surface is There is a problem that the image is slightly damaged. However, in this reactive ion etching, side etching (i.e., undercutting) due to the plasma of reactive species progresses at the same time.
The cross section of the dart electrode 4 becomes trapezoidal as shown in FIG. Furthermore, in order to improve the characteristics of field-effect transistors, the width of the gate electrode (40 width of the dart electrode in Fig. 2) is required.
Since it is important to make the width of the dart electrode 4 as short as possible, the width of the dart electrode 4 is machined to a width of <i'a, but this causes an increase in the resistance Rg of the dart electrode 4, making it impossible to improve the characteristics.

Moreover, this also becomes a restriction in increasing the length of the dart electrode and the dart width Wg). For that purpose,
It is conceivable to reduce the dart resistance by making the dirt electrode thicker, but this time the dirt electrode thickness (height and thickness) is larger than the dart electrode width, making it easier to peel off during the cleaning process and the like.

Next, as shown in FIG. 3, the photoresist is made of GaAs.
An i4-turn resist layer 5 is formed by coating on the substrate 1 and removing the portions corresponding to the source and drain regions and the portions on the dirt electrodes 4 by developing. Using this resist layer 5 and dirt electrode 4 as a mask, silicon (
A source region 6 and a drain region 7, which are high-concentration ion implantation regions, are formed in the GaAs substrate 1 by ion-implanting St) with an implantation energy of, for example, 150 keV and a dose of I x 1015tyn-2. At this time, since the cross-sectional shape of the dart electrode 4 is trapezoidal, all the ions at both ends near the bottom of the dart electrode 4 penetrate through the G
Due to penetration into the aAs substrate 1 and lateral diffusion due to the annealing treatment in the post-process, the area immediately below the end of the dart electrode 4 also becomes a high concentration region. This causes a reduction in dirt reverse breakdown voltage and a fluctuation in threshold voltage. In order to avoid such disadvantages,
By making the cross section of the dart electrode 4 as short as possible (see Figure 7), the multilayer wiring structure is
When formed as shown in the figure, there is a possibility that step coverage of the upper wiring 22 above the dirt electrode 21 is insufficient and disconnection occurs. In addition, if an overlapping portion is formed in the interlayer insulating film 23 on the dirt electrode 4, the upper wiring 2
When etching 2 into a predetermined pattern, there is a possibility that a short circuit may occur due to a portion of the upper wiring 22 remaining under the overhang portion without being completely etched away.

After ion implantation, the resist layer 5 is removed and the GaAs substrate 1 is
Then, an insulating retention film 8 is formed using 5i02 or 5t3N4 on the entire surface of the dirt electrode 4 by chemical vapor deposition (CVD) (FIG. 4). This insulating protective film 8 prevents As from coming out from the GaAs substrate 1 during annealing treatment, and has a thickness of, for example, 0.1 μm. Then, annealing treatment (heat treatment) for activation after ion implantation is performed at approximately 800° C. for approximately 20 minutes. The ion implantation region consists of a source region 6, a drain region 7 and a channel region 9.

Next, in order to form the source electrode 10 and the drain electrode 11 (FIG. 5), a photoresist (not shown) is formed, and the portions corresponding to the source electrode and the drain electrode are removed by exposure and development. do. A continuous evaporation film of AuGe and Au is formed on this photoresist layer, and the photoresist layer is removed with a solvent, and at the same time, the evaporation film on it is removed (to-off) to form a source electrode 10 as shown in FIG. and a drain electrode 11 is formed. and,
These electrodes 10, l by heating to a temperature of about 400°C
Make ie ohmic contact.

Next, an insulating film of SiO2 or Si3N4 is formed over the entire surface by CVD to form an interlayer insulating film 12 (FIG. 6). Note that this glabellar insulating film 12 includes the previously formed insulating film 8. Then, by forming the upper wiring 13, a multilayer wiring structure is constructed, and a GaAs Schottky field effect transistor (integrated circuit) is completed. The upper wiring 13 is formed by etching (or lifting off) a continuous vapor deposited film of titanium/gold (Ti-Au) or titanium/platinum/gold (Ti-Pt4u) into a predetermined pattern.

(4) Object of the Invention The object of the present invention is to propose a manufacturing method for GaAs Schottky r-) field effect transistors that does not have the above-mentioned problems in conventional manufacturing methods.

(5) Structure of the Invention Therefore, according to the present invention, a first film and a second film having a different etchant from the first film are formed on a GaAs-based substrate having insulating or semi-insulating properties. Then, at least the second film is patterned to form a first opening in the channel region and the region where the gate electrode is to be formed, and then the GaA film is formed through the first opening.
Ion implantation is performed into the s-based substrate to form a channel region,
Next, a film having a second opening having a larger area than the first opening is formed on the first film, and then Schottky contact is made with the GaAs-based substrate within the first opening to form an edge on the surface. There is provided a method for manufacturing a field effect semiconductor device, comprising the steps of forming a dart electrode having a taper by a lift-off method, and then forming a source region and a drain region using the dirt electrode as a mask.

Note that the film having the second opening may include the second opening.
It is possible to apply either a film in which the openings existing in the second film are side-etched to enlarge the opening area, or a film in which the second film is removed and then deposited and the openings are formed. can.

(6) Embodiments of the invention Hereinafter, the present invention will be described in detail by way of embodiments of the invention with reference to the accompanying drawings.

8 to 14 are schematic cross-sectional views of a field effect transistor for explaining each step in the manufacturing method according to the present invention.

According to the present invention, first, as shown in FIG. 8, reactive A? Aluminum nitride (A/!) with a thickness of 1000 mm was produced using the tuttering method.
A first insulating film 32 made of N) is formed, and then a silicon dioxide (Si02
) is formed.

Next, on the second insulating film 33, an aluminum film 34 having a thickness of zoooi is formed as a dry etching resistant mask film by vapor deposition, and a window 15 of the channel region pattern of the field effect transistor is formed by photoetching. The window of the dirt electrode i4 turn may be formed by a soft-off method by depositing a pattern and a mask film material (for example, aluminum (AZ)) in the shape of a register, ',) e-F-Yannel region.

Next, the SiO□ of the second insulating film 33 is etched by anisotropic etching using CHF3 or active ion beam etching through the window of the dry etching resistant mask film 32.
Then, the ktN of the g1 insulating film 32 is removed using CF4f or active ion beam etching to expose the GaAs substrate 31. and ion implantation (e.g., Sl).

An n-type channel region 36 is formed in the exposed GaAs substrate 31 (FIG. 9) using an energy of 60 keV and a dose of 2.times.10 crn.

Next, the second insulating film 33 is selectively etched (side etching) to form a hollow portion 37 extending laterally, as shown in FIG. This can be done, for example, by plasma etching with CHF3 or by hydrofluoric acid (H
F) The second insulating film 33'f is etched by wet etching using an etching solution, so-called isotropic etching.
! : Just remove it.

Next, a heat-resistant case material (for example, tungsten silicide) is deposited on the entire surface by a deposition method such as magnetron sputtering, in which it is deposited somewhat laterally through the window 35, thereby forming the dart electrode 38 and the deposited film 39. form (first
Figure 1).

Then, the second insulating film 33 and the dry etching resistant mask film 34 are etched with an ethotender solution (for example, an HF-based aqueous solution), and at the same time, the entire deposited film 39 thereon is lifted on and removed.

The dirt electrode 38 formed in this way has an effective channel length Lg defined by the window formed in the first insulating film 32, and is formed in a state where it is placed on the first insulating film 32 by the width ΔL (12th figure). Therefore, the adhesion area of the dirt electrode 38 on the lower surface is larger than that of a conventional gate electrode in which only the channel region is adhered, and it may be difficult to separate it from the first insulating film 32. Since the volume of the dirt electrode 38 can be made larger than in the conventional case, it is possible to reduce the r-) resistance.

Next, a photoresist is applied, and portions corresponding to the source and drain regions of the field effect transistor are developed and removed to form a photoresist layer 40 as shown in FIG. 12. Thereafter, using the vaginal photoresist layer 40 and the dirt electrode 38 as a mask, silicon (St) ions are implanted into the GaAs substrate 1 through the first insulating film 32 to form a highly impurity-concentrated n-type source region 41 and an n-type drain electrode 42. form. The energy of St ions is 150 [k
eV:] and the dose is 5×10 cm.

In such silicon ion implantation, since the edge portions on both sides of the dart electrode 38 in the dart length direction are sloped as described above, the region profile of the source region 41 and drain region 42, which are high concentration regions, on the date electrode 38 side is changed. It can form a slope and be connected to the channel region 38 . Since the first insulating film 32 exists, the high concentration n-type region 4
0.41 never comes into contact with the gate electrode. For this reason, characteristics such as predetermined Schottky breakdown voltage, dirt reverse breakdown voltage, and threshold voltage can be obtained with good reproducibility.

Thereafter, in order to activate the ion-implanted regions 36, 41, 42, an annealing process is performed at about 800° C. for about 20 minutes in a gas atmosphere of nitrogen (N2) and hydrogen (H2).

Next, the photoresist layer 39 is removed, photoresist is applied again, and portions corresponding to the source and drain electrodes are removed to form a photoresist layer (not shown). Using this photoresist layer as a mask, the first insulating film (AtN) is selectively removed using, for example, an H3PO3 solution to expose the GaAs substrate 31.

Second, gold/rumanium (AuGe) and gold (Au
) is formed to a thickness of about 3000λ, and the photoresist layer is removed with a solvent and at the same time the deposited film above it is removed (lifted off) to form the source electrode 43 and drain electrode 44 as shown in FIG. Form. And about 4
Ohmic contact is formed between the source and drain electrodes 43 and 44 and the source region 41 and drain region 42 by heating at 00° C. for about 1 minute.

Thereafter, in the same way as in the conventional manufacturing method, for example, a 4000X thick glabellar round film 45 made of silicon dioxide is formed on the entire surface, and interlayer connection holes (through holes) are formed in desired regions of the interlayer insulating layer 45. Upper wiring 46 is formed (fourteenth
figure). In this way, a plurality of GaAs Schottky dart field effect transistors (although only one is shown in the drawing) can be formed simultaneously to produce an integrated circuit. According to the manufacturing method of the present invention, since the dart electrode 38 has a trapezoidal cross-sectional shape, disconnection of the upper wiring on the gate electrode can be avoided.

In the above-described embodiment, the second insulating film 33 and the dry etching-resistant mask film 34 were used as a mask for ion implantation in the channel region type and for forming a gate electrode. The embodiment may also be used.

That is, as shown in FIG. 15, a first insulating film 32 is formed on a GaAs substrate 31, a photon cyst layer 51 is formed thereon, and a portion of the first insulating film above the channel region is selectively formed. Remove by etching.

Then, this photoresist layer 51 and the first insulating film 3
Ion implantation is performed using 2 as a mask to form the channel region 3.
form 6.

After removing the photoresist layer 51, another 7 otrenost layer 52 (FIG. 16) is formed on the first insulating film 32.

In this photoresist layer 52, as shown in FIG. 16, a nine-turn hole corresponding to a predetermined dart electrode is formed such that the first insulating film 32 is exposed by a length ΔL. A heat-resistant dart material is deposited on the entire surface by a slat-and-vine method or the like to form a dart electrode 38 on the channel region 36 and an attached film 39 on the photoresist layer 52 (FIG. 16). Next, when the photoresist layer 52 and the deposited film 39 thereon are simultaneously removed, the state shown in FIG. 12 for the above-described embodiment is obtained.

Furthermore, in the embodiments shown in FIGS. 8 to 14, when forming the channel region 36 shown in FIG. 9, the first insulating film 32 (AzN) is also removed and a GaAs semi-insulating substrate is formed. the channel region 3 with the surface of 31 exposed;
Silicon ions (sl+) are being implanted to form 6.

However, the present invention is not limited to this embodiment, and the silicon ions may be implanted while the first insulating film 32 remains on the surface of the GaAs semi-insulating substrate 31. When silicon ions are implanted while leaving the first insulating film 32, the silicon ion dose is 3×10 tm and the implantation energy is 100 tm.
It is said to be about keV.

(7) Effect of invention According to the present invention, there are effects as listed below.

(1) When processing the dart electrode made of high melting point metal silicide, a lift-off method is applied, so the space between the source and the dirt and between the dirt and the drain will not be exposed to an ion beam for etching, for example. Therefore, the surface of the GaAs-based substrate in that area will not be damaged.

(2) The dimension of the dirt electrode surface where the ion implantation mask reaches is in the relationship of +2ΔL with respect to the length of r−) on the channel region. Each side edge tapers to form part of a trapezoid. Therefore, when forming source and drain regions with high carrier concentration by ion implantation,
These regions and the channel region are smoothly connected in terms of carrier concentration, and there is no overlap between the dirt electrode and the source and drain regions with high carrier concentration, so the dirt breakdown voltage does not decrease, and the source Since carriers in the channel region and the drain region do not diffuse into the channel region, the controllability and reproducibility of the threshold voltage are improved.

(3)) f-) Since the edges of the electrodes are curved as described above, no hangs occur in the film formed thereon, and the steps, forces, and marenos are good.

(4) Although the effective case length is short, when compared with the area in the cross section of the date electrode, it is much smaller than the conventional case, so its resistance value can be reduced, and the effective case length can be reduced. This is effective in shortening the gate width and increasing the gate width.

(5) In the process, it is possible to adopt through implantation technology through the AAN film (first insulating film), so in such a case, high concentration carriers exist on the substrate surface or very close to the surface. Therefore, the transfer conductance of the MES-FET can be increased.

[Brief explanation of the drawing]

1 to 7 are schematic cross-sectional views of a GaAs semiconductor device in a manufacturing process for explaining a conventional manufacturing method, and FIGS. 8 to 14 are for explaining a manufacturing method according to the present invention. FIG. 15 and FIG. 16 are schematic cross-sectional views of a GaAs semiconductor device in a manufacturing process according to another embodiment of the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... GaAs substrate, 3... Low concentration ion implantation region, 4... Dirt electrode, 6... Source region, 7...
...Drain region, 10...Source electrode, 11...
Drain electrode, 12... Interlayer insulating film, 13... Upper wiring, 31... GaAs substrate, 32... First insulating film, 34... Dry etching resistant mask film, 36...
Channel region, 38... Dirt electrode, 41... Source region, 42... Drain region, 43... Source electrode, 44... Drain electrode, 45... Interlayer insulating film,
46... Upper wiring. 10th 2nd page 3rd page 4th page 5th page 9th page] 0 blood Page 13 page 15 page 16th page 1 9

Claims (1)

[Claims] 1. Laminating a first film and a second film using a different etchant from the first film on a GaAs-based substrate having insulating or semi-insulating properties, and then depositing at least the second film. A first opening is formed in a channel region and a region where a dirt electrode is to be formed by turning, and then ions are implanted into the GaAs-based substrate through the first opening to form a channel region. A film having a second opening having a larger area than the first opening is formed on the first film, and then Schottky contact is made with the GaAs-based substrate within the first opening, and two holes on the surface are formed. A dart electrode with a taper is formed by a shift-off method,
A method for manufacturing a field effect semiconductor device, comprising the step of next forming a source region and a drain region using the dirt electrode as a mask.