JP2001085448A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor device conform with high-frequency operation with high reliability by forming a plurality of electrodes, comprising a gate electrode in a semiconductor substrate and forming an insulation film in contact with a part of a surface of the gate electrode. SOLUTION: An ohmic region 101 and a channel layer 102 are formed in a semiconductor substrate 100, and a first stage recess 11 is formed in a channel layer 102. First and second insulation films 103, 104 are deposited thereon, and a gate opening 12 is formed in a gate electrode formation region of the insulation films 103, 104. Thereafter, a third insulation film 105 is deposited on the second insulation film 104 and the semiconductor substrate 100 exposed to the gate opening 12. Then, the third insulation film 105 in the inside of the second insulation film 104 enclosing the gate opening 12 is left, and the rest of the third insulation film 105 is removed. After an ohmic electrode 106 is formed, a second stage recess 13 is formed, and a gate electrode 107 is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device in which a semiconductor element having a plurality of electrodes, such as a Schottky gate type field effect transistor, is formed on a semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device having a plurality of electrodes, for example, a field effect transistor is formed on a semiconductor substrate or the like.
It has become an important device for communication equipment using the microwave band. A higher frequency is required for the field effect transistor. In such a case, a T-type gate field effect transistor that can shorten the gate length and reduce the gate resistance is often used.

Here, a conventional method of manufacturing a semiconductor device will be described with reference to FIG. 4 taking a field effect transistor having a T-type gate as an example.

In FIG. 4A, reference numeral 400 denotes a semiconductor substrate, and the semiconductor substrate 400 is ion-implanted.
Ohmic region (N ⁺ ) 401 and channel layer (N)
402 is formed. S on the semiconductor substrate 400
A first insulating film 403 of iO2 is formed, and the first insulating film 40 is formed.
3, a gate opening 404 having a size corresponding to a desired gate length is formed by dry etching.

Next, a resist wider than the opening of the gate opening 404 is formed on the gate opening 404, and a gate metal (for example, Au / Pt / Ti) is deposited. After that, lift off the gate metal using resist,
A gate electrode 405 is formed as shown in FIG. In the figure, the Ti layer of the gate electrode 405 is indicated by a thick line 405a. Thereafter, an ohmic electrode 406 is formed in the ohmic region (N ⁺ ), and a passivation film 407 is formed on the entire surface.

Another conventional method for manufacturing a semiconductor device will be described with reference to FIG. In FIG. 5A,
Reference numeral 500 denotes a semiconductor substrate, and an N ⁺ -GaAs layer 501 and an AlGa
As electron supply layer 502a, InGaAs channel layer 50
3. An AlGaAs electron supply layer 502b is provided. On the semiconductor substrate 500, an electron beam (EB) exposure resist 504 in which the opening 52 is formed, a high sensitivity resist 505 for stepper exposure, and a low sensitivity resist 506 for stepper exposure are respectively applied.

Thereafter, as shown in FIG. 1B, openings 51 for the upper gate of the T-type gate electrode are formed in the stepper resist 505 and the low-sensitivity resist 506 for stepper exposure, respectively.

After depositing a gate metal (Au / Pt / Ti), a gate electrode 507 is formed by lift-off as shown in FIG. In the figure, the Ti layer of the gate electrode 507 is indicated by a thick line 507a. After that, a passivation film 508 is formed on the entire surface.

[0009]

The field effect transistor manufactured by the conventional method shown in FIG. 4 has a structure in which an insulating film is interposed between the upper part of the gate electrode and the semiconductor substrate. Therefore, there is a problem that a large gate parasitic capacitance occurs in this portion, and sufficient gain cannot be obtained even if the gate length is reduced.

As a method of solving this problem, there is a method of removing an insulating film by isotropic etching such as chemical dry etching. However, if the gate metal is Au /
In the case of a laminated structure such as Pt / Ti or Au / Mo / Ti,
When the insulating film is removed, Ti of the Schottky metal is corroded. Therefore, this method reduces the reliability of the product. Further, even when the gate metal is a refractory metal such as WSi or WN, the surface of the semiconductor substrate is exposed to etching when removing the insulating film, which causes problems in reliability and characteristics.

The field effect transistor manufactured by the conventional method shown in FIG. 5 has the following problems 1-3.
First, it is difficult to remove the resist located around the lower part of the gate electrode, and the remaining resist adversely affects the reliability. In the second method, a passivation film to be deposited after forming the gate electrode is difficult to deposit around the lower portion of the gate electrode because the periphery of the lower portion of the gate electrode is narrower in opening. Third, when the gate length is reduced, the adhesion strength between the gate electrode and the semiconductor substrate and the mechanical strength of the gate electrode are reduced, and the gate metal is peeled off at the time of lift-off, or only the upper part of the gate electrode is peeled off.

An object of the present invention is to provide a semiconductor device which solves the above-mentioned drawbacks and which is highly reliable and suitable for high-frequency operation, and a method of manufacturing the same.

[0013]

According to the present invention, there is provided a semiconductor device comprising:
The semiconductor device includes a semiconductor substrate on which a plurality of electrodes including a gate electrode are formed, and an insulating film formed in contact with at least a part of the surface of the gate electrode and having resistance to isotropic etching.

Further, a method of manufacturing a semiconductor device according to the present invention
A first step of forming a first insulating film on a semiconductor substrate, a second step of forming a gate opening in a gate electrode formation region of the first insulating film, and the first insulating step in which the gate opening is formed A third step of forming a second insulating film having a lower etching rate than the first insulating film on the film, and leaving a portion of the second insulating film surrounding the gate opening and leaving the second insulating film in another portion; (2) a fourth step of removing the insulating film, and forming a gate electrode in the gate opening portion and in the upper portion of the gate opening, the upper portion of the gate opening being wider than the gate opening portion; A fifth step of performing
And a sixth step of selectively removing the first insulating film from the insulating film.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. 1 which shows a cross-sectional view of a manufacturing process of a field-effect transistor as an example.

In FIG. 1A, reference numeral 100 denotes GaAs.
In the semiconductor substrate 100, an ohmic region (N ⁺ ) 101 and a channel layer (N) 102 are formed by ion implantation, and the channel layer (N) 10
A first-stage recess 11 is formed in the second recess 2. In addition, the first insulating film 10 made of SiO2 having a sufficiently low isotropic etching rate.
3 is deposited to form a so-called cap annealing film.

Next, as shown in FIG. 2B, the S isotropic etching rate is sufficiently higher than that of the first insulating film 103.
A second insulating film 104 of iN is deposited, and a gate opening 12 is opened in the gate electrode formation region of the first insulating film 103 and the second insulating film 104 by anisotropic dry etching (RIE). Thereafter, the third insulating film 10 of SiO2, whose isotropic etching rate is sufficiently lower than that of the second insulating film 104, is used.
5 is deposited on the second insulating film 104 and on the semiconductor substrate 100 exposed at the gate opening 12.

Next, as shown in FIG. 1C, the entire surface is etched back by anisotropic dry etching (RIE). At this time, the third insulating film 105 remains inside the second insulating film 104 surrounding the gate opening 12, and the other portions of the third insulating film are removed. Then, ohmic region (N ⁺ ) 10
An ohmic electrode 106 is deposited on the substrate 1 and heat treatment is performed to recover damage caused by anisotropic dry etching.

Next, a resist pattern is formed on the gate, and a second-stage recess 13 is formed in the gate electrode formation region of the semiconductor substrate 100 by wet etching as shown in FIG. Thereafter, a gate metal (for example, Au / Pt / Ti) is deposited, and a gate electrode 107 is formed by lift-off. Note that the T of the gate electrode 107 is
The i-layer is shown by the thick line 107a.

Next, as shown in FIG. 1E, the second insulating film 104 is selectively removed from the first insulating film 103 by isotropic etching such as chemical dry etching. After that, a passivation film 108 is deposited.

According to the above method, the third insulating film 105 remains on the side surface of the gate electrode 107, and the Ti of the Schottky metal is protected by the third insulating film 105. Therefore, T
The second insulating film 104 can be removed by isotropic etching such as chemical dry etching without corroding i. Therefore, the parasitic capacitance around the gate electrode 107 is reduced, and a highly reliable field effect transistor suitable for high-frequency operation can be obtained. In addition, the third insulating film 105 improves the reduction in the adhesion of the gate metal when the gate length is reduced, and improves the mechanical strength of the gate electrode. The third insulating film 105 also functions as a passivation film on the side surface of the gate electrode 107.

According to the above structure, the semiconductor substrate 100
Is provided with a cap annealing film 103 on the surface thereof.
The cap annealing film 103 also functions as a protective film for protecting the semiconductor substrate 100 when removing the second insulating film 104, and also realizes an efficient field effect transistor.

Further, no insulating film is formed in the recess 13. For this reason, the influence of the depletion layer on the surface of the recess 13 is reduced, and the width of the recess can be reduced.

The recess is formed after the heat treatment for recovering the damage due to the anisotropic dry etching. In this case, the current value can be adjusted when the recess is formed by wet etching.

Next, another embodiment of the present invention will be described with reference to FIG. 2 which shows a cross-sectional view of the manufacturing process, taking a case of manufacturing a field effect transistor as an example.

In FIG. 2A, reference numeral 200 denotes a semiconductor substrate, and N ⁺ -G
aAs layer 201, AlGaAs stopper layer 202, Ga
As layer 203, AlGaAs electron supply layer 204a, In
GaAs channel layer 205, AlGaAs electron supply layer 2
04b is formed. S on the semiconductor substrate 200
A first insulating film 206 made of iN and a second insulating film 207 made of SiN are formed.

In forming the above structure, first, the N ⁺ -GaAs layer 201 of the epitaxial substrate is selectively etched to the AlGaAs stopper layer 202 by anisotropic dry etching (RIE). Thereafter, the first insulating film 2 of SiN having a sufficiently high isotropic etching rate is used.
The gate opening 21 is formed in the gate electrode formation region of the first insulating film 206. After that, the second insulating film 207 of SiN having a sufficiently high isotropic etching rate is used.
Is deposited on the first insulating film 206 and the AlGaAs stopper layer 202 exposed at the gate opening 21.

Next, as shown in FIG. 3B, the second insulating film 207 is etched back by anisotropic dry etching (RIE). At this time, the first surrounding the gate opening 21
The second insulating film 207 remains inside the insulating film 206, and the other portions of the second insulating film are removed. Further, the portion of the AlGaAs stopper layer 202 exposed at the gate opening 21
And then anisotropic dry etching (RIE)
With this, GaAs is applied to the AlGaAs electron supply layer 204.
The s layer 203 is selectively etched to form the gate recess 22.
To form

Next, as shown in FIG. 3C, a third insulating film 208 of SiO 2 whose isotropic etching rate is sufficiently slower than that of the first insulating film 206 or the second insulating film 207.
Is deposited on the first insulating film 206, the second insulating film 207, and the gate recess 22.

Next, as shown in FIG. 4D, the whole surface is etched back by anisotropic dry etching (RIE).
At this time, a gate opening is formed in the gate formation region of the third insulating film 208, and the second insulating film 20 surrounding the gate opening is formed.
7 and the third insulating film 208 on the side wall of the gate recess.
Remain, and the third insulating film in the other portions is removed. Thereafter, an ohmic electrode 209 is formed, and a heat treatment is performed to recover RIE damage. Thereafter, a gate metal (for example, Au / Pt / Ti) is deposited, and a gate electrode 210 is formed by lift-off. Note that the Ti layer of the gate electrode 210 is indicated by a thick line 210a.

Next, as shown in FIG. 3E, the first insulating film 206 and the second insulating film 207 are selectively removed from the third insulating film 208 by isotropic etching (chemical dry etching). I do. After that, a passivation film 211 is deposited.

According to the above method, the third insulating film 208 remaining on the side surface of the gate electrode protects the Schottky metal Ti, and removes the first insulating film 206 and the second insulating film 207 without corroding Ti. it can. Therefore, the parasitic capacitance around the gate electrode 210 can be reduced. In addition, the side surface of the gate electrode 210 having an extremely thin shape is mechanically reinforced by the third insulating film 208, and the strength of the gate electrode 210 is improved. After the recess 22 is formed, the recess 22 is formed.
A third insulating film 208 is deposited on the surface. In this case, the third insulating film 20 is also provided between the side surface of the gate metal and the GaAs layer 203.
8 protected. Therefore, a decrease in breakdown voltage due to current leakage from the side surface of the gate metal is prevented, and a highly reliable field effect transistor suitable for high-frequency operation can be realized.

In the above structure, the second insulating film for protecting the side surface of the gate electrode is provided even in the recess. Therefore, when the recess is formed by wet etching,
The wraparound of the deposited gate metal around the inside of the recess is prevented. Further, when the recess is formed by anisotropic dry etching, a decrease in withstand voltage which occurs when the gate metal is buried to the side surface of the recess is prevented.

Next, another embodiment of the present invention will be described with reference to FIG. 3 which shows a sectional view of a manufacturing process of a case where a field effect transistor is manufactured as an example. In FIG. 3A, reference numeral 301 denotes a semiconductor substrate.
On the semiconductor substrate 301, a first insulating film 302 of SiN whose etching rate by buffered hydrofluoric acid is sufficiently slow is deposited, and then SiO2 whose etching rate by buffered hydrofluoric acid is sufficiently faster than that of the first insulating film 302.
Is deposited on the first insulating film 302.

Next, as shown in FIG. 3B, the gate electrode forming region of the second insulating film 303 is etched by anisotropic etching, and the gate opening 31 exposing the first insulating film 302 thereunder. To form After that, the etching rate with buffered hydrofluoric acid is
The third insulating film 304 is formed on the first insulating film 302 and in the second
It is deposited on the insulating film 303.

Next, as shown in FIG. 3C, an opening 32 is formed in the gate electrode forming region of the third insulating film 304 by anisotropic etching over the entire surface, and then the second insulating film 303 and the third insulating film are formed. An opening 33 is formed in the gate electrode formation region of the first insulating film 302 by anisotropic etching using the mask 304 as a mask.
To form At this time, the third insulating film 304 remains inside the second insulating film 303 surrounding the gate electrode formation region, and other portions are removed.

Next, as shown in FIG. 4D, anisotropic etching is performed using the first insulating film 2, the second insulating film 3, and the third insulating film 4 as a mask to form a recess 34 in the semiconductor substrate 301. Then, a WSi gate metal 305 is sputtered on the entire surface.

Next, as shown in (e), an Au upper gate 35 is formed on the gate metal 305 by pattern plating, and the gate metal 30 is formed using the upper gate 35 as a mask.
5 is etched to form a gate electrode.

Next, as shown in FIG. 5F, the second insulating film 303 and the third insulating film 303 are formed on the first insulating film 302 by isotropic wet etching, for example, etching using buffered hydrofluoric acid. The film 304 is selectively removed.

In the step shown in FIG.
When the gate electrode formation region of the second insulating film 303 is etched to form the gate opening 31, the first insulating film 30
2 are exposed. However, the second insulating film 303 may be left on the first insulating film 302 so that the first insulating film 302 is not exposed so that the first insulating film 302 remains in a subsequent step. In this case, the third insulating film 30
4 is deposited on the second insulating film 303, including the second insulating film 303 remaining on the first insulating film 302.

According to the above method, the first insulating film 302 is left on the surface of the semiconductor substrate 301 around the gate electrode. Therefore, the second insulating film 303 and the third insulating film 304 can be removed while protecting the surface of the semiconductor substrate 301. Accordingly, the insulating film around the gate electrode can be removed and the parasitic capacitance can be reduced without damaging the surface of the semiconductor substrate 301. In addition, a T-shaped fine gate electrode
Mechanically reinforced by the insulating film 302. For this reason,
A highly reliable field-effect transistor suitable for high-frequency operation can be provided.

As described above, according to the present invention, the insulating film for protecting the gate electrode from isotropic etching is provided on the side wall portion of the gate electrode and the surface of the semiconductor substrate. Therefore, even when a Schottky metal having low etching resistance is used or the semiconductor substrate surface is damaged by the etching, the insulating film around the gate electrode of the field effect transistor can be removed while leaving a thin insulating film for protection. Therefore, the parasitic capacitance due to the insulating film remaining around the T-type gate structure can be reduced. In addition, the gate length can be reduced,
The gate resistance is reduced, and a highly reliable field effect transistor suitable for high-frequency operation is realized.

In the above embodiment, the case where the gate Schottky metal is Ti or WSi, and the case where the isotropic etching for etching the insulating film is CDE or wet etching with buffered hydrofluoric acid will be described. ing. However, the Schottky metal of the gate may be another metal, and other methods can be used for the isotropic etching.

[0044]

According to the present invention, a highly reliable semiconductor device suitable for high-frequency operation and a method of manufacturing the same can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of a conventional example.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of another conventional example.

[Explanation of symbols]

Reference Signs List 100 semiconductor substrate 101 ohmic region (N ⁺ ) 102 channel layer (N) 103 first insulating film (SiO2) 104 second insulating film (SiN) 105 third insulating film (SiO2) 106 ohmic electrode 107 gate electrode 108 passivation film 11 recess 12 gate opening 13 recess

Claims (13)

[Claims] 1. A semiconductor comprising: a semiconductor substrate on which a plurality of electrodes including a gate electrode are formed; and an insulating film formed in contact with at least a part of the surface of the gate electrode and resistant to isotropic etching. apparatus. 2. The semiconductor device according to claim 1, wherein an insulating film resistant to isotropic etching is formed on a surface of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the gate electrode is located in a recess formed in the semiconductor substrate, and an insulating film in contact with the gate electrode surface extends into the recess. 4. A first step of forming a first insulating film on a semiconductor substrate, a second step of forming a gate opening in a gate electrode formation region of the first insulating film, and forming the gate opening. A third step of forming a second insulating film having a lower etching rate than the first insulating film on the first insulating film, and leaving a portion of the second insulating film surrounding the gate opening; A fourth step of removing the portion of the second insulating film,
A fifth step of forming a gate electrode in which the width of the upper part of the gate opening is larger than the width of the gate opening part in the gate opening part and the upper part of the gate opening; And a sixth step of selectively removing the first insulating film. 5. The second and fourth steps are performed by anisotropic etching, the sixth step is performed by isotropic etching,
5. The method according to claim 4, wherein the difference between the etching rates of the first insulating film and the second insulating film is in the isotropic etching. 6. The method according to claim 4, further comprising the step of forming an insulating film on the semiconductor substrate before the first step. 7. The method according to claim 4, further comprising the step of forming a recess in the semiconductor substrate located at the bottom of the gate opening after the second step. 8. A first step of forming a first insulating film on a semiconductor substrate, a second step of forming a gate opening in a gate forming region of the first insulating film, and the gate opening is formed. A third step of forming a second insulating film on the first insulating film, a fourth step of forming a gate opening in a gate forming region of the second insulating film, and a recess in the gate forming region of the semiconductor substrate. Forming a third step of forming a third insulating film having a lower isotropic etching rate than the first insulating film and the second insulating film on the first insulating film and the second insulating film;
A sixth step of forming the recess portion, and a seventh step of removing the third insulating film in the other portion while leaving the third insulating film in the portion surrounding the gate opening and in the side wall portion of the recess.
An eighth step of forming a gate electrode in the recess, in the gate opening, and in the upper part of the gate opening, in which the upper part of the gate opening is wider than the gate opening. And a ninth step of selectively removing the first insulating film and the second insulating film from the third insulating film. 9. The fourth step and the seventh step are performed by anisotropic etching, the ninth step is performed by isotropic etching,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the difference between the etching rates of the first insulating film, the second insulating film, and the third insulating film is isotropic etching. 10. A first step of forming a first insulating film on a semiconductor substrate, and a second step of forming a second insulating film on the first insulating film at a higher etching rate than the first insulating film.
A step of forming a gate opening in a gate formation region of the second insulating film; and forming the third insulating film having an etching rate higher than that of the first insulating film by forming the gate opening. A fourth step of forming on the second insulating film, a fifth step of leaving the third insulating film in a portion surrounding the gate opening and removing the third insulating film in another portion, A sixth step of forming a gate opening in a gate formation region of the first insulating film using the film and the third insulating film as a mask, and using the first insulating film, the second insulating film, and the third insulating film as a mask; A seventh step of forming a recess in the semiconductor substrate; a gate opening formed in the recess and in the first insulating film; a gate opening surrounded by the third insulating film;
An eighth step of forming a gate electrode above the gate opening; and a ninth step of selectively removing the second insulating film and the third insulating film from the first insulating film. Manufacturing method. 11. A first step of forming a first insulating film on a semiconductor substrate, and a second step of forming a second insulating film on the first insulating film at a higher etching rate than the first insulating film.
Forming a gate opening in a gate formation region of the second insulating film; and forming the second opening at the bottom of the gate opening.
A third step of leaving an insulating film; a fourth step of forming a third insulating film having a higher etching rate than the first insulating film on the second insulating film in which a gate opening is formed; A fifth step of leaving the third insulating film in a portion surrounding the opening for use and removing the third insulating film in another portion; and using the second insulating film and the third insulating film as a mask, forming the second insulating film. A sixth step of forming a gate opening in a film and a gate formation region of the first insulating film; and forming a recess in the semiconductor substrate using the first insulating film, the second insulating film, and the third insulating film as a mask. 7 steps, in the recess and in the first
An eighth step of forming a gate opening formed in the insulating film, a gate opening surrounded by the third insulating film, and a gate electrode above the gate opening; And a ninth step of selectively removing the second insulating film and the third insulating film. 12. An eighth step is to form a gate opening in the recess and in the first insulating film, a gate opening surrounded by the third insulating film, and a gate metal in an upper portion of the gate opening. 2. A step of forming an upper gate metal on the gate metal, and etching the gate metal using the upper gate metal as a mask.
The method of manufacturing a semiconductor device according to claim 1 or claim 12. 13. The third step and the fifth step, the sixth step,
The seventh step is performed by anisotropic etching, the ninth step is performed by isotropic etching, and the difference between the etching rates of the first insulating film, the second insulating film, and the third insulating film is isotropic. 12. The method according to claim 10, wherein the etching is performed.
The manufacturing method of the semiconductor device described in the above.