JPH06310710A - Fabrication of compound semiconductor device - Google Patents

Abstract

PURPOSE:To allow fabrication of an LDD structure FET having low gate resistance within the wafer surface with high uniformity. CONSTITUTION:A gate electrode 14 is formed on a semiinsulating Gaps substrate 11 on which an n-layer 12 is formed using a photoresist 13 as a mask followed by formation of an n<+> layer 15 by selective ion implantation. The gate electrode 14 is then side etched and SiO2 16 is selectively deposited, thicker than the gate electrode 14, from liquid phase on the semiinsulating GaAs substrate 11 except the gate electrode 14. An n' layer 17 is then formed on the surface of the GaAs substrate 11 through the SiO2 by ion implantation. Subsequently, the semiinsulating GaAs substrate 11 is annealed with the SiO2 as a protective film. Finally, a source-drain electrode 18 is formed followed by formation of a low resistance metal layer 19 on the gate electrode 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor, and more particularly to a method for manufacturing a field effect transistor for a high speed compound semiconductor IC used in communication equipment, computers and the like.

[0002]

2. Description of the Related Art Conventionally, in the manufacturing process of a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as GaAs, the parasitic source / drain resistance between the gate / source and the gate / drain is reduced, and To increase the breakdown voltage between the source and gate / drain,
LDD (Lightly D) using high melting point metal gate
A high melting point metal gate self-alignment process is widely used.

The manufacturing method will be described below with reference to FIG. First, as shown in FIG. 2A, a photoresist is coated on the semi-insulating GaAs substrate 11, and selective ion implantation is performed using a photolithography process to form a channel layer (n layer 12). Next, FIG.
As shown in (b), a refractory metal gate electrode 14 is formed on the n layer 12. Next, as shown in FIG. 2C, a photoresist is applied and selective ion implantation is performed using a photolithography process to form an n ′ layer 17 having a larger implantation amount and implantation depth than the n layer 12. Form. At this time, the refractory metal gate electrode 14 also serves as a mask for ion implantation, and the n-layer 12 and the n′-layer 17 are formed.
Are formed in a self-aligned manner. Next, as shown in FIG. 2D, after depositing an insulating film (through film 21) such as SiO ₂ , a photoresist is applied and selective ion implantation using a photolithography process is performed to source the FET source. Form a drain region (n ⁺ layer 15). At this time, the refractory metal gate electrode 14 also serves as a mask for ion implantation, and the n ′ layer 17 and the n ⁺ layer 1
The positions of 5 are formed in a self-aligned manner. Next, FIG. 2 (e)
As shown in FIG. 5, an insulating film (protective film 22) such as SiO ₂ is deposited, and an annealing process is performed using the film as a protective film to activate implanted ions and form an active layer of the FET. next,
As shown in FIG. 2F, the source / drain electrodes 18 are formed on the n ⁺ layer 15.

However, since refractory metals generally have high resistance, the FET thus manufactured has high gate resistance and is not suitable for high frequency operation. In order to operate the FET at a high frequency, it is necessary to reduce the gate resistance by forming a low resistance metal layer such as gold on the high melting point gate metal.

Therefore, as a method of forming a low resistance metal layer on a high melting point gate metal, a method of opening an insulating film on a gate electrode by using a photolithography process is used. Hereinafter, the manufacturing method will be described with reference to FIG.

First, as shown in FIG. 3A, a gate electrode 14 is formed on a semi-insulating GaAs substrate 11 using a conventional LDD refractory metal gate self-alignment process.
The source / drain electrodes 18 are formed. Next, FIG.
As shown in (b), the interlayer insulating film 31 is deposited on the entire surface. Next, as shown in FIG. 3C, the photoresist 1
3 is applied, and the photoresist 13 is removed only on the gate electrode 14 using a photolithography process. The width to be removed at this time is smaller than the gate length. Next, the insulating film on the gate electrode 14 is removed by dry etching to form the gate contact portion 32. Finally, as shown in FIG. 3D, a low resistance metal layer 19 such as gold is formed on the gate electrode 14 so as to be thicker than the gate electrode 14.

However, since it is difficult to perform fine processing of 0.5 μm or less in the photolithography process, in a FET having a gate length of 0.5 μm or less, a gate contact portion thinner than the gate length can be formed on the gate electrode. Can not. Further, since the alignment accuracy in the photolithography process is about ± 0.1 μm, in the FET with a gate length of 0.5 μm or less, when the alignment of the gate contact portion on the gate electrode is misaligned, During the dry etching for forming the film, the active layer may be damaged due to overetching.

Therefore, as a method of forming a low resistance metal layer on a gate electrode having a gate length of 0.5 μm or less without using a step of opening an insulating film on the gate electrode by using photolithography, an etch back method is used. The method using is used.

The manufacturing method will be described below with reference to FIG. First, on the semi-insulating GaAs substrate 11,
Using the conventional LDD refractory metal gate self-alignment process, a gate electrode formation step, an ion implantation step,
An annealing process and a source / drain electrode forming process are performed.
Next, as shown in FIG. 4A, the planarizing insulating film 41 is deposited so as to have the same film thickness as the gate electrode 14. Next, as shown in FIG. 4B, the photoresist 13 is applied and then heated to flatten the surface of the photoresist 13. Next, as shown in FIG. 4C, the photoresist 1
3 and the flattening insulating film 41 on the gate electrode 14 have the same etching rate, dry etching (hereinafter referred to as etch back) is performed to make the surfaces of the gate electrode 14 and the flattening insulating film 41 flat. In this state, the gate electrode 14 is exposed. Finally, as shown in FIG. 4D, a low resistance metal layer 19 such as gold is formed on the gate electrode 14 so as to be thicker than the gate electrode 14.

According to this manufacturing method, the low resistance metal layer can be formed on the gate electrode having a gate length of 0.5 μm or less without using the step of opening the insulating film on the gate electrode by using photolithography. it can. However, since the deposition of the insulating film and the dry etching cause a certain degree of non-uniformity within the wafer surface, in the etch-back process of FIG. 4C, the gate electrode is formed with the thickness of the insulating film uniform within the wafer surface. It is difficult to expose the top. Also, FIG.
In the step (b) of applying the photoresist and then heating it to flatten the surface of the photoresist, it is difficult to flatten a pattern having a large area, and a pattern having a large area on the gate electrode and in the etchback step. I can't expose the top at the same time. Therefore, in order to expose the pattern having a large area, a step of etching only the pattern having a large area is required, which increases the number of steps.

[0011]

Therefore, an object of the present invention is to easily and uniformly form a low resistance metal layer on a gate electrode having a gate length of 0.5 μm or less.
An object of the present invention is to provide a method for uniformly manufacturing an LDD structure type FET having a low gate resistance in a wafer surface.

[0012]

In order to solve the above problems, the present invention includes a step of etching a gate electrode on a compound semiconductor substrate by using a photoresist as a mask, and the photoresist and the gate electrode. A step of ion-implanting the compound semiconductor substrate surface, a step of side-etching the gate electrode using the photoresist as a mask, and the compound excluding the gate electrode using the photoresist as a mask on the compound semiconductor substrate. A step of selectively forming a SiO ₂ film thicker than the gate electrode on the semiconductor substrate by precipitation from a liquid phase; and the compound semiconductor substrate including the gate electrode through the SiO ₂ film after removing the photoresist. A step of implanting ions on the surface, and the above-mentioned SiO ₂
A method of manufacturing a compound semiconductor device, comprising: annealing the compound semiconductor substrate including the gate electrode using the film as a protective film.

[0013]

According to the present invention, the SiO ₂ film deposited from the liquid phase does not deposit on the resist and can be selectively formed using the resist as a mask, and when ions are implanted through the insulating film, the ions pass through the film. Since energy is lost at this time, it is utilized that the ion can be selectively implanted into the compound semiconductor substrate by controlling the film thickness of the insulating film.

[0014]

Embodiments of the method for manufacturing the FET of the present invention will be described below.
Will be described with reference to FIG. (1) A semi-insulating GaAs substrate 11 is used as a compound semiconductor.
The photoresist is used on the semi-insulating GaAs substrate 11.
Acceleration voltage 20 keV, dose 1.0
× 10¹³cm^-2Channel layer with Si ion implantation
The (n layer 12) is formed (FIG. 1A). (2) Gate metal 14 on the surface of semi-insulating GaAs substrate 11
WSi with a film thickness of 2000Å is deposited as
CF by RIE using the mask 13 as a mask_FourWith system gas
By anisotropic dry etching with a gate length of 1.0 μm
The gate electrode 14 is formed (FIG. 1B). (3) Photoresist on the semi-insulating GaAs substrate 11
As a mask, acceleration voltage 150 keV, dose 5.0 ×
10¹³cm^-2Inject Si ions to the extent of⁺Layer 15
Formed (FIG. 1 (c)). (4) CDE (CF
_FourThe gate length should be 0.5 μm depending on the system gas).
Side etching of the gate electrode 14 is performed (FIG. 1).
(D)). (5) Hydrofluoric acid SiO₂Adding boric acid to a saturated solution
Due to supersaturated SiO₂Make a solution. This solution
Then, the semi-insulating GaAs substrate 11 is dipped into the semi-insulating Ga
SiO on the surface of As substrate 11₂The film 16 is formed. This and
Photoresist has low wettability, so photoresist 1
3 on top of SiO₂The film does not deposit. Therefore, the photo cashier
Semi-insulation except gate electrode 14 masked by strike 13
On the surface of the crystalline GaAs substrate 11₂Selective membrane 16
Can be formed. Where SiO₂Film thickness of film 16
Is formed to be thicker than the gate electrode 14 (see FIG. 1).
(E)). (6) After removing the photoresist 13, semi-insulating GaAs
Acceleration voltage 5 on the substrate 11 using the photoresist as a mask
0 keV, dose 5.0 × 10¹²cm^-2Si is about
ON is injected to form the n'layer 17. Where the gate
SiO near the electrode ₂The film 16 has a film thickness of SiO in the peripheral portion.₂
Since it is thinner than the film thickness of the film 16, the gate electrode
SiO in the vicinity₂Si ions selectively only through the film 16
Are implanted to form the n'layer 17 in a self-aligned manner (Fig.
1 (f)). (7) Above SiO₂800 ° C. with the film 16 as a protective film,
Anneal for about 15 minutes to activate the ion-implanted layer.
(Fig. 1 (f)). (8) Source drain composed of AuGe / Ni / Au layer
After forming the electrode, a Ti / Au layer is formed to a thickness of 500/30.
About 00Å is vapor-deposited on the semi-insulating GaAs substrate 11 and
Ar using the photoresist as a mask⁺Ion using ion
Processed by milling, Ti / Au on the gate electrode 14
A low resistance metal layer 19 is formed (FIG. 1 (g)).

[0015]

As described above, according to the present invention, from the liquid phase to Si
A gate length of 0.5 can be obtained by selectively forming an O ₂ film.
easily low-resistance metal layer in μm below the gate electrode, and good uniformity it is possible to form, by further controlling the thickness of the SiO ₂ film, when the ions are implanted through the SiO ₂ film, self Since the n ′ layer is formed in a consistent manner, the LDD structure type FET having a low gate resistance can be uniformly manufactured in the wafer surface.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in order of the steps, showing a method for manufacturing a compound semiconductor device according to an embodiment of the present invention.

2A to 2C are cross-sectional views in order of the processes, showing an example of a conventional method for manufacturing a compound semiconductor device.

3A to 3C are cross-sectional views in order of the processes, showing an example of a conventional method for manufacturing a compound semiconductor device.

4A to 4C are cross-sectional views in order of the processes, showing an example of a conventional method for manufacturing a compound semiconductor device.

[Explanation of symbols]

11 semi-insulating GaAs substrate 12 n layer 13 photoresist 14 gate electrode 15 n ⁺ layer 16 SiO ₂ film 17 n'layer 18 source / drain electrode 19 low resistance metal layer 21 through film 22 protective film 31 interlayer insulating film 32 gate contact Part 41 Insulating film for planarization

Claims (3)

[Claims] 1. A SiO ₂ film formed by precipitation from a liquid phase on a compound semiconductor substrate, and S formed by precipitation from the liquid phase.
A method of manufacturing a compound semiconductor device, comprising the step of implanting ions into the surface of the compound semiconductor substrate through an iO ₂ film. 2. A compound semiconductor substrate having a gate electrode formed on the surface thereof, and using a photoresist as a mask, selectively depositing a SiO ₂ film by precipitation from a liquid phase on the compound semiconductor substrate excluding the gate electrode. And a step of planarizing the surface of the compound semiconductor substrate including the gate electrode. 3. A photoresist is formed on a compound semiconductor substrate.
The gate electrode is processed by etching as a mask
Process, including the photoresist and the gate electrode.
And a step of implanting ions into the surface of the compound semiconductor substrate,
The gate electrode is supported using the photoresist as a mask.
Process for id etching and the compound semiconductor substrate
Above the gate using the photoresist as a mask
Deposition from liquid phase on the compound semiconductor substrate excluding electrodes
By SiO₂Selectively make the film thicker than the gate electrode
Forming step, and after removing the photoresist, the Si
O ₂Through the film, the compound semiconductor including the gate electrode
The step of implanting ions on the surface of the body substrate;₂The membrane
The compound semiconductor including the gate electrode as a protective film
And a step of annealing the substrate.
Method for manufacturing semiconductor device.