KR100244273B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100244273B1 KR100244273B1 KR1019970067894A KR19970067894A KR100244273B1 KR 100244273 B1 KR100244273 B1 KR 100244273B1 KR 1019970067894 A KR1019970067894 A KR 1019970067894A KR 19970067894 A KR19970067894 A KR 19970067894A KR 100244273 B1 KR100244273 B1 KR 100244273B1
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- polysilicon layer
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- metal layer
- gate insulating
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 MOSFET제조시 폴리실리콘층의 불순물 도핑을 용이하게 조절하고, 폴리실리콘층 식각시 표면을 균일하게하여 게이트절연막의 절연특성을 개선시켜 소자의 신뢰성을 향상시키는데 적당한 반도체소자 제조방법을 제공하기 위한 것으로써, 반도체기판상에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1 폴리실리콘층, 제 1 메탈층, 제 2 폴리실리콘층을 차례로 형성한 후, 불순물 도핑을 실시하는 공정, 상기 제 2 폴리실리콘층, 제 1 메탈층을 제거하여 제 1 폴리실리콘층의 표면을 노출시키는 공정, 상기 제 1 폴리실리콘층상에 제 2 메탈층을 형성하는 공정, 상기 제 2 메탈층 및 제 1 폴리실리콘층을 선택적으로 제거하여 게이트전극을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The present invention provides a semiconductor device manufacturing method suitable for easily controlling the doping of the polysilicon layer during the MOSFET manufacturing, and uniformity of the surface during the polysilicon layer etching to improve the insulating properties of the gate insulating film to improve the reliability of the device. For example, a step of forming a gate insulating film on a semiconductor substrate, a step of sequentially forming a first polysilicon layer, a first metal layer, a second polysilicon layer on the gate insulating film, and then impurity doping, Exposing the surface of the first polysilicon layer by removing the second polysilicon layer and the first metal layer, forming a second metal layer on the first polysilicon layer, the second metal layer and the first poly And selectively removing the silicon layer to form a gate electrode.
Description
본 발명은 반도체소자에 관한 것으로서 특히, 얇은 폴리와 메탈로 이루어진 게이트에서 폴리의 도핑을 효과적으로 실시하기에 적당한 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for effectively doping poly in a gate made of thin poly and metal.
일반적으로 모스팻(MOSFET)의 게이트전극은 게이트절연막위에 폴리실리콘이 형성되고, 상기 폴리실리콘상에 게이트전극의 저항을 감소시키기 위한 실리사이드(Silicide)또는 메탈을 형성한다.In general, the gate electrode of the MOSFET is formed of polysilicon on the gate insulating layer, and forms silicide or metal to reduce the resistance of the gate electrode on the polysilicon.
메탈의 경우, 텅스텐(W)이나 티타늄나이트라이드(TiN) 등을 주로 사용하는데 만일, 게이트전극의 높이가 너무 높으면, 평탄화등과 같은 후속공정이 어려워진다.In the case of metal, tungsten (W) or titanium nitride (TiN) is mainly used. If the height of the gate electrode is too high, subsequent processes such as planarization, etc. become difficult.
따라서, 게이트전극을 형성하기 위한 폴리실리콘층의 두께를 조절한다.Therefore, the thickness of the polysilicon layer for forming the gate electrode is adjusted.
이하, 종래기술에 따른 반도체소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a semiconductor device manufacturing method according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래 반도체소자 제조방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device.
먼저, 도 1a에 도시한 바와같이 반도체기판(11)상에 게이트절연막(12)을 형성한다.First, as shown in FIG. 1A, a
이후, 상기 게이트절연막(12)상에 불순물이 도핑되지 않은 폴리실리콘층(13)을 형성한 후, 이온주입을 실시한다.Subsequently, after the
이때, 상기 폴리실리콘층(13)의 두께는 1500Å이하로 제한한다.At this time, the thickness of the
이와같이 폴리실리콘층(13)의 두께를 제한하는 대신에 도 1b에 도시한 바와같이 상기 폴리실리콘층(13)을 충분한 두께로 증착한 후, 이온주입을 실시한다.Thus, instead of limiting the thickness of the
이와같이 이온주입을 실시한 후, 열처리하여 불순물이 확산에 따른 불순물이 게이트절연막(12)이나 반도체기판(11)에까지 침투되는 것을 방지한다.After ion implantation is performed in this manner, heat treatment is performed to prevent impurities from diffusion into the
상기 도 1b의 공정이 완료되면, 도 1c에 도시한 바와같이 상기 폴리실리콘층(13)을 소정깊이로 식각하여 도 1a의 두께와 동일하도록 한다.When the process of FIG. 1B is completed, as illustrated in FIG. 1C, the
이와같이 상기 폴리실리콘층(13)의 두께를 조절한 다음, 도 1d에 도시한 바와같이 상기 폴리실리콘층(13)상에 게이트저항 감소용 메탈(14)을 증착한다.After adjusting the thickness of the
이후, 도면에는 도시되지 않았지만, 상기 메탈(14)상에 포토레지스트를 도포한 후 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 포토레지스트를 마스크로 이용한 식각공정으로 상기 메탈(14), 폴리실리콘층(13)을 선택적으로 제거하여 게이트전극을 형성하게 된다.Subsequently, although not shown in the drawings, the photoresist is coated on the
그러나 상기와 같은 종래 모스팻 제조방법은 다음과 같은 문제점이 있었다.However, the conventional method for preparing MOSFETs has the following problems.
첫째, 도 1a와 같이 최초에 폴리실리콘층을 얇게 형성하면, 낮은 에너지로 불순물주입을 실시하거나, 불순물을 틸트주입 하여야하며, 후에 열처리공정에서 불순물의 확산을 컨트롤하기가 어렵다.First, when the polysilicon layer is initially formed as shown in FIG. 1A, impurity injection or tilt impurity should be performed with low energy, and it is difficult to control the diffusion of impurities in the heat treatment process.
따라서, 불순물이 게이트절연막이나 기판으로까지 침투되어 게이트절연막의 특성을 저하시키고 소자의 문턱전압을 변화시키게 된다.Therefore, impurities penetrate into the gate insulating film or the substrate, thereby deteriorating the characteristics of the gate insulating film and changing the threshold voltage of the device.
둘째, 도 1b 내지 1c와 같이 최초에 폴리실리콘층을 두껍게 증착한 후 식각하는 경우에 있어서는 폴리실리콘층의 불순물 도핑을 컨트롤하기는 용이하지만, 폴리실리콘층을 식각할 때, 특정부분의 폴리실리콘층의 두께가 매우 얇아질 경우, 후공정에서 형성되는 메탈이 게이트절연막에 가깝게 형성되어 게이트절연막에 스트레스(stress)를 주게 된다.Second, in the case of etching the polysilicon layer after the first thick deposition of the polysilicon layer, as shown in FIGS. 1B to 1C, it is easy to control the doping of the polysilicon layer, but when etching the polysilicon layer, When the thickness of the thin film becomes very thin, the metal formed in the later process is formed close to the gate insulating film, which gives stress to the gate insulating film.
이로인해, 게이트절연막의 특성을 저하시키고, 폴리실리콘층의 식각면이 거칠어지므로 후속공정에 제한이 따른다.As a result, the characteristics of the gate insulating film are deteriorated, and the etching surface of the polysilicon layer becomes rough, so that subsequent steps are limited.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로써, 게이트전극용 폴리실리콘층에 불순물 도핑을 용이하게 실시하고, 폴리실리콘층의 식각에 따른 표면이 거칠어지는 것을 방지하는데 적당한 반도체소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor device manufacturing method suitable for easily doping impurity doping to the gate silicon polysilicon layer and preventing roughening of the surface of the polysilicon layer due to etching. The purpose is to provide.
도 1a 내지 1d는 종래 반도체소자 제조방법을 설명하기 위한 공정단면도1A through 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 2d는 본 발명의 반도체소자 제조방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,21 : 반도체기판 12,22 : 게이트절연막11,21
23,25 : 제 1, 제 2 폴리실리콘층 24,26 : 제 1, 제 2 메탈층23,25: 1st,
상기의 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은 반도체기판상에 게이트절연막을 형성하는 공정, 상기 게이트절연막상에 제 1 폴리실리콘층, 제 1 메탈층, 제 2 폴리실리콘층을 차례로 형성한 후, 불순물 도핑을 실시하는 공정, 상기 제 2 폴리실리콘층, 제 1 메탈층을 제거하여 제 1 폴리실리콘층의 표면을 노출시키는 공정, 상기 제 1 폴리실리콘층상에 제 2 메탈층을 형성하는 공정, 상기 제 2 메탈층 및 제 1 폴리실리콘층을 선택적으로 제거하여 게이트전극을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a gate insulating film on a semiconductor substrate, a first polysilicon layer, a first metal layer, and a second polysilicon layer are sequentially formed on the gate insulating film And then impurity doping, removing the second polysilicon layer and the first metal layer to expose the surface of the first polysilicon layer, and forming a second metal layer on the first polysilicon layer. And removing the second metal layer and the first polysilicon layer to form a gate electrode.
이하, 본 발명의 반도체소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명의 반도체소자 제조방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
먼저, 도 2a에 도시한 바와같이, 반도체기판(21)상에 게이트절연막(22)을 형성한다.First, as shown in FIG. 2A, a
상기 게이트절연막(22)상에 불순물이 도핑되지 않은 제 1 폴리실리콘층(23)을 형성한다.A
이때, 상기 제 1 폴리실리콘층(23)의 두께는 500∼1000Å정도이다.At this time, the thickness of the
이어, 상기 제 1 폴리실리콘층(23)상에 제 1 메탈층(24)을 형성한다.Subsequently, a
이때 상기 제 1 메탈층(24)의 두께는 50∼300Å정도로 얇게 형성하며, 상기 제 1 메탈층(24)의 물질은 후공정에서 이루어지는 불순물 도핑을 방해하지 않아야되고, 상기 제 1 폴리실리콘층(23)에 대해서는 식각선택비가 큰 물질 예컨대, 텅스텐 실리사이드(WSiX)이다.At this time, the thickness of the
특히, 후공정에서 이루어지는 열처리공정시 제 1 폴리실리콘층(23)과 반응하여 실리콘의 손실(loss)가 발생하지 않도록 X〉2.5(WSi2.5)인 텅스텐 실리사이드를 사용한다.In particular, a tungsten silicide having X> 2.5 (WSi 2.5 ) is used to react with the
이어, 상기 제 1 메탈층(24)상에 불순물이 도핑된 제 2 폴리실리콘층(25)을 1000∼2000Å정도로 형성한다.Subsequently, a
이때, 상기 제 2 폴리실리콘층(25)을 형성하는 이유는 후에 이루어질 불순물 도핑이 용이해지도록 하기 위함이다.In this case, the reason for forming the
이와같이 제 2 폴리실리콘층(25)을 형성한 후, 불순물을 이온주입한 다음, 열처리공정을 수행한다.After forming the
이때 N도전형의 도핑을 위해서는 아세닉(As)또는 인(P)을 주입하고, P도전형의 도핑을 위해서는 붕소(B) 또는 BF2를 주입한다.At this time, the insulator (As) or phosphorus (P) is injected for the doping of the N conductivity type, and the boron (B) or BF 2 is injected for the doping of the P conductivity type.
이어, 도 2b에 도시한 바와같이 상기 제 2 폴리실리콘층(25)을 선택적으로 식각하여 제거한 후, 도 2c에 도시한 바와같이 상기 제 1 메탈층(24)을 제거하여 제 1 폴리실리콘층(23)의 표면을 노출시킨다.Next, as shown in FIG. 2B, the
그리고 도 2d에 도시한 바와같이 상기 제 1 폴리실리콘층(23)상에 게이트저항을 감소시키기 위한 제 2 메탈층(25)을 형성한다.As shown in FIG. 2D, a
이때, 상기 제 2 메탈층(26)의 물질로써는 텅스텐(W), 티타늄나이트라이드(TiN), 몰리브덴(MO) 등을 500∼1000Å정도로 증착한다.In this case, as the material of the
여기서, 상기 제 1 폴리실리콘층(23)과 상기 제 2 메탈층(26)과의 반응을 없애기 위해 상기 제 2 메탈층(26)형성전에 티타늄나이트라이드(TiN)또는 티타늄 텅스텐(TiW)등과 같은 베리어층을 형성하는 공정이 가능하다.Here, in order to eliminate the reaction between the
이어, 도면에는 도시하지 않았지만, 상기 제 2 메탈층(26)과 제 1 폴리실리콘층(23)을 선택적으로 제거하여 게이트전극을 형성한다.Next, although not shown, the gate electrode is formed by selectively removing the
이상 상술한 바와같이 본 발명의 반도체소자 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention has the following effects.
첫째, 게이트전극용 폴리실리콘층을 정확하게 조절할 수 있고, 그 표면을 균일하게 형성하므로 게이트절연막에 스트레스를 주지않아 게이트절연막의 특성저하를 방지한다.First, the polysilicon layer for the gate electrode can be precisely adjusted, and the surface thereof is uniformly formed, thereby preventing stress on the gate insulating film and thus preventing deterioration of the characteristics of the gate insulating film.
둘째, 최초에 형성되는 폴리실리콘층의 두께를 얇게 형성하더라도 불순물 도핑을 용이하게 조절할 수 있다.Second, even when the thickness of the polysilicon layer formed initially is thin, it is possible to easily control the doping of impurities.
Claims (6)
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