JPS5892224A - Pattern formation - Google Patents

Pattern formation

Info

Publication number
JPS5892224A
JPS5892224A JP19146481A JP19146481A JPS5892224A JP S5892224 A JPS5892224 A JP S5892224A JP 19146481 A JP19146481 A JP 19146481A JP 19146481 A JP19146481 A JP 19146481A JP S5892224 A JPS5892224 A JP S5892224A
Authority
JP
Japan
Prior art keywords
film
substrate
predetermined
pattern
plasma etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19146481A
Other languages
Japanese (ja)
Inventor
Yoshihiro Todokoro
義博 戸所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP19146481A priority Critical patent/JPS5892224A/en
Publication of JPS5892224A publication Critical patent/JPS5892224A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes

Abstract

PURPOSE:To form a sharp and fine pattern by a method wherein a positive-type resist is applied after applying one or more-layer resin film on a predetermined substrate and the resin thin film is eliminated by using plasma etching after exposing and developing a predetermined figure on the positive-type resist. CONSTITUTION:A silicon substrate is used as a substrate 1, and PBS is used as a resin thin film 6 and after applying the film 6 on the Si substrate, prebaking is performed, followed by the prebaking again by applying AZ2400. Litht exposure is performed by using a predetermined mask. Next, the AZ2400 is developed and then etching is done with the aid of a facing electrode-type plasma etching device. Loss of the AZ2400 film hardly exists in this process and a fine pattern can be formed. The PBS just under a window section is etched by executing etching with the aid of a cylindrical plasma etching device and it was possible to form a pattern shape suitable for lift off.

Description

【発明の詳細な説明】 本発明は、所定基板上に樹脂膜とポジ型レジストを用い
て、リフトオフに適したパターンを形成する方法および
微細なパターンを形成する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a pattern suitable for lift-off and a method of forming a fine pattern on a predetermined substrate using a resin film and a positive resist.

半導体装置の集積化が進むにつれて、微細なパターンを
形成する必要性が高捷っている。餓細なパターンを形成
するためには、基板上に塗付するレジスト層を薄くする
必要がある。しかし、1/シスト層を薄くするとピンホ
ールが発生しやすくなること、あるいは凹凸のある基板
の被覆が不充分となることなどの不都合が生じる。この
ためレジスト層を薄くすることには限界があり、このこ
とによってパターンの微細化が制限されていた。まだ、
電子ビーム露光を用いてパターンを形成する場合は、基
板から後方散乱されてレジスト中にまい戻る電子が露光
に寄与するため、基板に近いレジスト層はど露光量が強
くなり、このレジスト内の露光量の変化がレジストの微
細化を妨げていた。
2. Description of the Related Art As semiconductor devices become more integrated, the need to form finer patterns becomes more complex. In order to form a thin pattern, it is necessary to thin the resist layer applied to the substrate. However, when the 1/cyst layer is made thinner, problems such as pinholes are more likely to occur or uneven substrates are insufficiently covered. Therefore, there is a limit to how thin the resist layer can be made, and this has limited the ability to make patterns finer. still,
When forming a pattern using electron beam exposure, electrons that are backscattered from the substrate and returned to the resist contribute to the exposure, so the amount of exposure in the resist layer closer to the substrate is stronger, and the exposure in this resist is increased. Changes in the amount hindered resist miniaturization.

一方、基板上に所定金属図形を形成するためにリフ1−
オフとよばれる方法がしばしば用い゛られる。
On the other hand, in order to form a predetermined metal figure on the substrate, the rift 1-
A method called off is often used.

このリフトオフ法では第1図で示す過程を経てパターン
形成がなされる。すなわち第1図(d)に示すように、
所定基板1上にレジスト膜2を塗付した後、露光、現像
を行い所定窓図形3を形成し〔第1図(b)〕、さらに
この上に金属膜4を蒸着して第1図(C)で示す基板構
造を得、こののちレジスト膜2を除去することにより、
この上の金属膜を同時に取り去り、所定の金属膜図形5
を形成する〔第1図(d)〕。
In this lift-off method, pattern formation is performed through the process shown in FIG. That is, as shown in FIG. 1(d),
After coating a resist film 2 on a predetermined substrate 1, exposure and development are performed to form a predetermined window pattern 3 [FIG. 1(b)].Furthermore, a metal film 4 is deposited on this to form a predetermined window pattern 3 (FIG. 1(b)). By obtaining the substrate structure shown in C) and then removing the resist film 2,
The metal film on this is removed at the same time, and a predetermined metal film figure 5 is formed.
[Fig. 1(d)].

ところで、実際に形成されるレンストパターンの断面形
状は第1図で示すようにはならず、通常は、第2図(a
)で示すように逆台形状となる。このため、レジスト膜
のパターンが形成された基板上に金属膜4を蒸着すると
、第2図(b)で示すように、所定窓図形3上の金属膜
部分とレジスト膜2上の金属膜部分とがつながり、リフ
トオフにより所定の金属図形6を形成するのが困難にな
る不都合があった。
By the way, the cross-sectional shape of the resist pattern that is actually formed is not as shown in FIG. 1, but is usually as shown in FIG.
), it has an inverted trapezoidal shape. Therefore, when the metal film 4 is deposited on the substrate on which the pattern of the resist film is formed, as shown in FIG. There was an inconvenience that the metal figures 6 were connected to each other, making it difficult to form a predetermined metal figure 6 by lift-off.

本発明は、所定基板上に一層以上の樹脂膜を塗付後、ポ
ジ型レジストを塗付し、ポジ型レジストに所定図形を露
光、現像した後、プラズマエツチングを用いて樹脂薄膜
を除去することを特徴とするパターン形成方法であって
、本発明によれば」二連の問題点を解決することができ
、基板に垂直な方向ヲ強くエツチングするプラズマエツ
チングニより、微細パターンの形成が可能となり、等方
的なプラズマエツチングをすることにより、リフトオフ
に適したパターンを形成することができる。
The present invention involves coating a predetermined substrate with one or more resin films, then coating a positive resist, exposing and developing a predetermined pattern on the positive resist, and then removing the resin thin film using plasma etching. According to the present invention, two problems can be solved, and fine patterns can be formed using plasma etching, which strongly etches in the direction perpendicular to the substrate. By performing isotropic plasma etching, a pattern suitable for lift-off can be formed.

以下に本発明第3図を参照して詳細に説明する。The present invention will be explained in detail below with reference to FIG.

先ず、第3図(a)に示すように所定基板1上に樹脂薄
膜6を塗付し、プリベークを行った後、レジスト膜2を
塗付し再度プリベークを行う。なお上記の樹脂薄膜6は
レジストであってもよいし、非感光性樹脂であってもよ
い。
First, as shown in FIG. 3(a), a resin thin film 6 is applied onto a predetermined substrate 1, prebaked, and then a resist film 2 is applied and prebaked again. Note that the resin thin film 6 described above may be a resist or a non-photosensitive resin.

次に、所定図形を露光、現像して、第3図(b)に示す
ようにレジスト膜2に窓3を形成する。この現像液に対
して不溶性の樹脂薄膜6を用いることにより、樹脂薄膜
6はそのまま残存する。ここで露光は、光露光、電子ビ
ーム電光が考えられるが、X線露光、イオンビーム露光
を用いることもできる。
Next, a predetermined pattern is exposed and developed to form a window 3 in the resist film 2 as shown in FIG. 3(b). By using the resin thin film 6 that is insoluble in this developer, the resin thin film 6 remains as it is. Here, the exposure may be light exposure or electron beam lightning, but X-ray exposure or ion beam exposure may also be used.

コノのち、対向電極型のプラズマエツチング装置を用い
て窓3内に露呈する樹脂薄膜6をエツチングすることに
より、第3図(c)で示すようにパターン形成がなされ
る。以上の過程を経て形成したパターンは極めて微細な
ものとなる。ここでは、一層の樹脂薄膜について説明し
たが、多層の樹脂薄膜を形成することも可能である。
Thereafter, the thin resin film 6 exposed within the window 3 is etched using a counter-electrode type plasma etching device to form a pattern as shown in FIG. 3(c). The pattern formed through the above process becomes extremely fine. Although a single layer resin thin film has been described here, it is also possible to form a multilayer resin thin film.

次いで、円筒形プラズマエツチング装置を用いて樹脂薄
膜6に対して等方的なエツチング処理を施すと、樹脂薄
膜6は第3図(d)で示すようエツチングされる。この
形状は、レジスト膜2が廂状に突出したリフトオフに好
適な形状である。
Next, when the thin resin film 6 is subjected to an isotropic etching process using a cylindrical plasma etching apparatus, the thin resin film 6 is etched as shown in FIG. 3(d). This shape is suitable for lift-off in which the resist film 2 protrudes like a ridge.

第3図(6)は、以」−の処理を経た基体に金属膜を形
成したのちの状態を示す図であり、図示するように、レ
ジヌト膜上の金属膜4と基体1上の金属膜図形6とが完
全に分断される。したかって、レジスト膜2を除去する
ことにより、同時にこの上の金属膜4を取り去ることが
でき、金属膜図形6をうろことができる。
FIG. 3 (6) is a diagram showing the state after a metal film is formed on the substrate which has undergone the above-mentioned treatment.As shown in the figure, the metal film 4 on the resin film and the metal film on the substrate 1 The figure 6 is completely separated. Therefore, by removing the resist film 2, the metal film 4 thereon can be removed at the same time, and the metal film figure 6 can be removed.

次に第3図に基いて具体例について説明する。Next, a specific example will be explained based on FIG.

基本1としてシリコン(Sl)基板を用い、樹脂薄膜6
としてポジ型電子ビームレシヌトとして知られるPBS
(ポリプランスルフォン)を用い、レジスト嘆2として
A Z 2400を用いる。81基板上に1μmの厚さ
にPBSを塗付後、160G10分間のプリベークを行
う。AZ2400を0.571 mの厚さに塗付しテ9
0’C、10分間のプリベークを再度行う。所定マスク
を用いて光露光を行う。
A silicon (Sl) substrate is used as the basic 1, and a resin thin film 6 is used.
PBS, also known as positive electron beam resin
(Polypuran Sulfone) and AZ 2400 as resist layer 2. After applying PBS to a thickness of 1 μm on the 81 substrate, a 160G prebaking was performed for 10 minutes. Apply AZ2400 to a thickness of 0.571 m and
Pre-bake again at 0'C for 10 minutes. Light exposure is performed using a predetermined mask.

次KAZ2401現像液を用いて、AZ2400を現像
する。こののち対向電極型プラズマエツチング装置を用
いて、RF出力200W 、圧力0.3Tovr 、 
 エンチングガスo2の条件で30秒間エツチングする
。この処理ではA Z 2400の膜ペリはほとんどな
く、最小パターンとして0.5μmスペースの微細パタ
ーンを形成することができる。
Next, develop AZ2400 using KAZ2401 developer. After that, using a facing electrode type plasma etching device, the RF output was 200W, the pressure was 0.3Tovr,
Etching is performed for 30 seconds under the condition of etching gas O2. In this process, there is almost no film periphery of AZ 2400, and a fine pattern with a minimum spacing of 0.5 μm can be formed.

リフトオフに適したパターンを形成するためには、円筒
形のプラズマエツチング装置を用いる。
A cylindrical plasma etching device is used to form a pattern suitable for lift-off.

RF出力200W 、圧力2 T□vr 、  工yチ
ングガス02の条件で6分間エツチングすることにより
、窓部直下のPBSはエツチングされ、サイドエツチン
グにより、リフトオフに適したパターン形状を形成する
ことができた。
By etching for 6 minutes under the conditions of RF output 200 W, pressure 2 T□vr, and etching gas 02, the PBS directly under the window was etched, and by side etching, a pattern shape suitable for lift-off could be formed. .

以上詳述したように、本発明によれば、基板が凹凸のあ
るものであっても樹脂薄膜を塗付することによりこの凹
凸を緩和して平らにするとともにピンホールの発生をな
くすことができるので、ポジ型レジスト層を薄く塗布で
き、しかも最終的にプラズマエツチングによりレジスト
を除去するのでレジスト残渣の発生がなくなり、切れの
よい微細なパターンを形成することができる。まだ、等
方向なプラズマエツチングを用いることにより、樹脂薄
膜がサイドエツチングされることにより、リフトオフに
適した形状のパターンを形成することができる。
As detailed above, according to the present invention, even if the substrate is uneven, by applying a resin thin film, the unevenness can be alleviated and made flat, and the occurrence of pinholes can be eliminated. Therefore, a positive resist layer can be applied thinly, and since the resist is finally removed by plasma etching, no resist residue is generated, and a fine pattern with good sharpness can be formed. However, by using isodirectional plasma etching, the resin thin film is side-etched, and a pattern with a shape suitable for lift-off can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(IL)〜(d)はリフトオフを説明する工程断
面図、第2図(2L) 、 (b)は従来のリフトオフ
工程の断面図、 第3図(IL)〜(el)は本発明の一実施例による微
細パターンを形成する方法およびリフトオフに適したパ
ターンを形成する方法を説明する断面図である。 1・・・・・・基板、2・・・・・・ボン型しシヌト、
3・・・・・・窓、4・・・・・・金属膜、6・・・・
・・金属膜図形、6・・・・・樹脂薄膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 (C)              [d)〔ε)  
         5
Figures 1 (IL) to (d) are process cross-sectional views explaining lift-off, Figures 2 (2L) and (b) are cross-sectional views of conventional lift-off processes, and Figures 3 (IL) to (el) are FIG. 2 is a cross-sectional view illustrating a method of forming a fine pattern and a method of forming a pattern suitable for lift-off according to an embodiment of the invention. 1...Substrate, 2...Bong-type sinuto,
3... Window, 4... Metal film, 6...
...Metal film figure, 6...Resin thin film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (C) [d) [ε)
5

Claims (1)

【特許請求の範囲】[Claims] 所定基板上に一層以上の樹脂膜を塗付後、ポジ型レジス
トを塗付し、前記ポジ型レジストに所定図形を露光、現
像した後、プラズマエツチングを用いてiJ記樹脂薄膜
を除去することを特徴とするパターン形成方法。
After applying one or more layers of resin film on a predetermined substrate, applying a positive resist, exposing and developing a predetermined pattern on the positive resist, and then removing the resin thin film using plasma etching. Characteristic pattern formation method.
JP19146481A 1981-11-27 1981-11-27 Pattern formation Pending JPS5892224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19146481A JPS5892224A (en) 1981-11-27 1981-11-27 Pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19146481A JPS5892224A (en) 1981-11-27 1981-11-27 Pattern formation

Publications (1)

Publication Number Publication Date
JPS5892224A true JPS5892224A (en) 1983-06-01

Family

ID=16275077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19146481A Pending JPS5892224A (en) 1981-11-27 1981-11-27 Pattern formation

Country Status (1)

Country Link
JP (1) JPS5892224A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH055191U (en) * 1991-06-28 1993-01-26 株式会社馬頭製作所 Car for children

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643729A (en) * 1979-09-18 1981-04-22 Matsushita Electric Ind Co Ltd Formation of fine pattern
JPS5687343A (en) * 1979-12-17 1981-07-15 Sony Corp Forming method of wiring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643729A (en) * 1979-09-18 1981-04-22 Matsushita Electric Ind Co Ltd Formation of fine pattern
JPS5687343A (en) * 1979-12-17 1981-07-15 Sony Corp Forming method of wiring

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH055191U (en) * 1991-06-28 1993-01-26 株式会社馬頭製作所 Car for children

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