JPS59103337A - Pattern formation - Google Patents

Pattern formation

Info

Publication number
JPS59103337A
JPS59103337A JP21313482A JP21313482A JPS59103337A JP S59103337 A JPS59103337 A JP S59103337A JP 21313482 A JP21313482 A JP 21313482A JP 21313482 A JP21313482 A JP 21313482A JP S59103337 A JPS59103337 A JP S59103337A
Authority
JP
Japan
Prior art keywords
film
etching
window
pattern
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21313482A
Other languages
Japanese (ja)
Inventor
Shuzo Oshio
大塩 修三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21313482A priority Critical patent/JPS59103337A/en
Publication of JPS59103337A publication Critical patent/JPS59103337A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To obtain a metal film of micro-miniature pattern by covering the entire part with a positive resist film, when etching a metal film deposited on a semiconductor substrate through an insulating film, opening an window and filling it with a polyimide film which is resistive to dry etching, removing the resist film leaving only such polyimide film and by etching the metal film with the polyimide film used as the mask. CONSTITUTION:An Al film 10 is deposited on a semiconductor substrate 1 through an insulating film 2, a positive resist film 11 is provided on the entire part, it is then exposed by the electronic exposing method and developed, and a window is opened in the desired region. A polyimide film 12 which is resistive to dry etching is applied to the entire part including the window and is baked. While adjusting such baking time, ion etching is carried out. Thereby, the film 12 is left only within the window. Thereafter, with the film 12 used as the mask, the film 11 in the periphery is removed by the O2 plasma. With the film 12 left used as the mask, the reactive ion etching is carried out to the film 10 using CCl4 and thereby the desired shape of Al film 10 can be obtained.

Description

【発明の詳細な説明】 +a)  発明の技術分野 本発明はパターン形成方法にかかり、特に微細なパター
ンを高精度に形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION +a) Technical Field of the Invention The present invention relates to a pattern forming method, and particularly to a method of forming a fine pattern with high precision.

(bl  従来技術と問題点 半導体集積回路(IC)などの半導体装置を製造する際
に、半導体装置の性能向上のためパターンの微細化が要
求されエツチング方法も従来のウエントエッチング方法
に代わってドライエツチング方法が重用されるようにな
ってきた。これはドライエツチング方法ではスパッタ効
果が加わるためにサイドエッチが生じにくいことが大き
な原因となってパターン精度が向上するからである。
(bl) Prior art and problems When manufacturing semiconductor devices such as semiconductor integrated circuits (ICs), miniaturization of patterns is required to improve the performance of semiconductor devices, and the dry etching method has replaced the conventional wet etching method. Etching methods have come to be used frequently because dry etching methods add a sputtering effect and are less likely to cause side etching, which improves pattern accuracy.

しかしながら、ドライエツチングを行うとレジスト膜の
マスクが損傷しやすくて、その点からパターン精度が悪
くなる欠点がある。例えば第1図に示すように半導体基
板1上に絶縁膜2を介してアルミニウム膜3を被着し、
その上面にレジスト膜4のマスクを形成してエツチング
すると、第2図に示すような精度の悪いアルミニウム膜
3のパターンが形成される。このようなレジスト膜は、
例えば電子線露光法に用いられるPMMAIQなどのよ
うに高感度で解像度の良いレジスト膜になるほど、ドラ
イエツチングに対する耐性が弱くて、折角レジスト膜パ
ターンの精度が良くても被エツチング材のパターン精度
は良くはならない。従って、例えば幅0.5〜1μm程
度の極めて微細なバターンの形成は非常に難しい問題と
なっている。
However, when dry etching is performed, the mask of the resist film is easily damaged, which has the disadvantage that pattern accuracy deteriorates. For example, as shown in FIG. 1, an aluminum film 3 is deposited on a semiconductor substrate 1 via an insulating film 2,
When a resist film 4 mask is formed on the upper surface and etched, a pattern of the aluminum film 3 with poor precision as shown in FIG. 2 is formed. Such a resist film is
For example, the higher the sensitivity and resolution of a resist film such as PMMAIQ used in electron beam exposure, the weaker the resistance to dry etching. Must not be. Therefore, forming extremely fine patterns with a width of about 0.5 to 1 μm, for example, has become a very difficult problem.

(C)  発明の目的 本発明はこのような問題点を解消して、微細パターンを
高精度に形成するパターン形成方法を提案するものであ
る。
(C) Object of the Invention The present invention solves the above-mentioned problems and proposes a pattern forming method for forming fine patterns with high precision.

((11発明の構成 その目的は、被エツチング材上にレジスト膜パターンを
形成し、その上面に耐ドライエツチング性の有機材料膜
を形成する工程、次いで該有機材料膜をエツチングして
上記レジスト膜パターンの窓内に該有機材料膜を残存さ
せる工程、次いで上記レジスト膜パターンを除去し、残
存させた有機材料膜をマスクとして上記被エツチング材
をエツチングする工程が含まれるパターン形成方法によ
って達成することができる。
(11 Structure of the Invention The purpose is to form a resist film pattern on a material to be etched, and to form a dry etching-resistant organic material film on the upper surface of the resist film pattern, and then to etch the organic material film to remove the resist film. Achieving this by a pattern forming method that includes the steps of leaving the organic material film in the window of the pattern, then removing the resist film pattern, and etching the material to be etched using the remaining organic material film as a mask. Can be done.

(el  発明の実施例 以下1図面を参照して実施例によって詳細に説明する。(el Embodiments of the invention An embodiment will be described in detail below with reference to one drawing.

第3図ないし第9図は本発明にがかる一実施例の工程順
断面図で、先づ第3図に示すように半導体基板1上に絶
縁膜2を介して被着したアルミニウム膜10の上面にP
MMA膜11全11して電子線露光法によって露光する
。そうして第4図に示すようなPMMAIIffllの
マスクパターンを形成する。このPMMA膜11全11
型レジスト膜で、その膜厚を0.5〜1μm程度とする
3 to 9 are cross-sectional views in the order of steps of an embodiment according to the present invention. First, as shown in FIG. niP
The entire MMA film 11 is exposed by electron beam exposure. Then, a mask pattern of PMMAIIffll as shown in FIG. 4 is formed. This PMMA film 11 total 11
A resist film with a thickness of about 0.5 to 1 μm.

次いで、第5図に示すようにその上に膜厚2μmのポリ
イミド膜12を塗布して約200°Cでヘーキングする
。このように厚く塗布するとポリイミド′膜の表面を平
坦化することができ−る。次いで、第6図に示すように
アルゴンガスを用いたイオンミリング法(ドライエツチ
ング法の一種)によってポリイミド膜全面をエツチング
し、エツチング時間を調整してPMMAIIQの窓内に
のみポリイミド膜12を残存させる。次いで、第7図に
示すように酸素ガスを用いたプラズマエンチング法によ
ってPMMA膜11全11チング除去する。この場合、
ポリイミド膜は酸素ガスプラズマによってエツチングさ
れにくいために、工・ノチング時間を調節すればPMM
A膜を除去してポリイミド膜12を残存させることがで
きる。また、第7図に示ず酸素ガスプラズマエンチング
工程を用いないで、上記のアルゴンガスを用いたイオン
ミリング法によって同時にPMMA膜11全11し、窓
内のポリイミド膜12を残存させることもできる。それ
はPMMA膜がアルゴン(Ar)を用いたイオンミリン
グ法によってポリイミド膜よりはるかにエツチングされ
やすいからである。
Next, as shown in FIG. 5, a polyimide film 12 having a thickness of 2 .mu.m is applied thereon and baked at about 200.degree. By applying it thickly in this manner, the surface of the polyimide film can be flattened. Next, as shown in FIG. 6, the entire surface of the polyimide film is etched by an ion milling method (a type of dry etching method) using argon gas, and the etching time is adjusted so that the polyimide film 12 remains only within the window of PMMAIIQ. . Next, as shown in FIG. 7, the entire PMMA film 11 is removed by plasma etching using oxygen gas. in this case,
Since polyimide film is difficult to be etched by oxygen gas plasma, PMM can be removed by adjusting the etching and notching time.
The polyimide film 12 can be left by removing the A film. Alternatively, instead of using the oxygen gas plasma etching step (not shown in FIG. 7), the entire PMMA film 11 can be removed at the same time by the ion milling method using argon gas as described above, leaving the polyimide film 12 inside the window. . This is because PMMA films are much more easily etched than polyimide films by ion milling using argon (Ar).

次いで、第8図に示すようにポリイミド膜12をマスク
パターンとしてアルミニウム膜1oを四塩化炭素(CC
14)ガスを用いたりアクチブイオンエツチングによっ
てエツチングする。次いで、ポリイミド膜12のマスク
パターンを酸素ガスプラズマエツチングによって除去す
ると、第9図に示すように微細なアルミニウム膜10パ
ターンが高精度に形成される。
Next, as shown in FIG. 8, the aluminum film 1o is coated with carbon tetrachloride (CC) using the polyimide film 12 as a mask pattern.
14) Etching using gas or active ion etching. Next, when the mask pattern of the polyimide film 12 is removed by oxygen gas plasma etching, a fine pattern of the aluminum film 10 is formed with high precision as shown in FIG.

このようにすれば幅0.5〜1μmの微細パターンも容
易に形成でき、本発明は上記のアルミニウム膜の他、シ
リコンや酸化シリコンなどの絶縁膜にも適用して同様に
精度の良いサブミクロンパターンを形成することができ
るものである。
In this way, fine patterns with a width of 0.5 to 1 μm can be easily formed, and the present invention can be applied to insulating films such as silicon and silicon oxide in addition to the above-mentioned aluminum film to produce submicron patterns with similar accuracy. A pattern can be formed.

(f)  発明の効果 以上の説明から明らかなように、本発明によればサブミ
クロンのパターンを精度2良く形成できて半導体装置の
高性能化、高信頼化に著しく役立てることができる。
(f) Effects of the Invention As is clear from the above description, according to the present invention, submicron patterns can be formed with a precision of 2, which is extremely useful for improving the performance and reliability of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来のパターン形成方法の工程順
断面図、第3図ないし第9図は本発明にかかる工程順断
面図である。 図中、1は半導体基板、2は絶縁膜、3はアルミニウム
膜、4はレジスト膜、10はアルミニウム膜、11はP
MMA膜(ポジ型レジスト膜)。 第1図 第2図 第 3 図 第4図 第5図 第6図 第7図 第9図 58.4,14 11.1’l” Ij’ be官殿 1°If I’lのノ(小 昭和タフf臼旨′)11・f1第、! / 3 /3!
弓;2 毎回の PI  K  ハ・つクー〉■杉p叉
2り去3、1ili 11^4る名 ・1τ1′1との閏1イ・ti”i’p7 l慣l′1
人(L所 神令用県用崎市中1叫メ1小Ill中101
5番地(522)名(j、富士通株式会社 4 代  理  人     fL+’li  神奈川
県用崎山中ハ;1区I11・Ill中1015市地5、
 tlli 11命1゛?σ・11イ・]昭和ぷト13
月ノ2j1(発送1」)
1 and 2 are step-by-step cross-sectional views of a conventional pattern forming method, and FIGS. 3 to 9 are step-by-step cross-sectional views according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is an aluminum film, 4 is a resist film, 10 is an aluminum film, and 11 is a P
MMA film (positive resist film). Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 9 Fig. 9 Showa Tough F Usuma') 11th F1,! / 3 / 3!
Bow; 2 Every time PI K ha・tsuku〉■Sugi p叉2 remove 3, 1ili 11^4 Runame・1τ1'1 leap 1i・ti"i'p7 l practice l'1
People (L place, Kamireiyo Prefecture, Yosaki City, 1st grade, 1st grade, 1st grade, 101st grade)
Address 5 (522) Name (j, Fujitsu Ltd. 4 Agent fL+'li Kanagawa Prefecture Yosakiyama Nakaha; 1 Ward I11/Ill Naka 1015 City 5,
tlli 11 lives 1゛? σ・11i・】Showa Puto 13
Tsukino 2j1 (Shipping 1)

Claims (1)

【特許請求の範囲】[Claims] 被エツチング材上にレジスト膜パターンを形成し、その
上面に耐ドライエツチング性の有機材料膜を形成する工
程、次いで該有機材料膜をエツチングして上記レジスト
膜パターンの窓内に該有機材料膜を残存させる工程、次
いで上記レジス)IIQパターンを除去し、残存させた
有機材料膜をマスクとして上記被エツチング材をエツチ
ングする工程が含まれてなることを特徴とするパターン
形成方法
A step of forming a resist film pattern on a material to be etched and forming a dry etching-resistant organic material film on the upper surface of the resist film pattern, and then etching the organic material film to form the organic material film within the window of the resist film pattern. A pattern forming method comprising a step of leaving the resist IIQ pattern, and then etching the material to be etched using the remaining organic material film as a mask.
JP21313482A 1982-12-03 1982-12-03 Pattern formation Pending JPS59103337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21313482A JPS59103337A (en) 1982-12-03 1982-12-03 Pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21313482A JPS59103337A (en) 1982-12-03 1982-12-03 Pattern formation

Publications (1)

Publication Number Publication Date
JPS59103337A true JPS59103337A (en) 1984-06-14

Family

ID=16634135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21313482A Pending JPS59103337A (en) 1982-12-03 1982-12-03 Pattern formation

Country Status (1)

Country Link
JP (1) JPS59103337A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321831A (en) * 1986-07-16 1988-01-29 Matsushita Electronics Corp Pattern forming method
JPS6351639A (en) * 1986-08-20 1988-03-04 Nec Corp Formation of fine pattern
JPH09148313A (en) * 1995-11-22 1997-06-06 Nec Corp Dry etching process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321831A (en) * 1986-07-16 1988-01-29 Matsushita Electronics Corp Pattern forming method
JPS6351639A (en) * 1986-08-20 1988-03-04 Nec Corp Formation of fine pattern
JPH09148313A (en) * 1995-11-22 1997-06-06 Nec Corp Dry etching process

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