JPS63175480A - Manufacture of recessed mesfet - Google Patents
Manufacture of recessed mesfetInfo
- Publication number
- JPS63175480A JPS63175480A JP779187A JP779187A JPS63175480A JP S63175480 A JPS63175480 A JP S63175480A JP 779187 A JP779187 A JP 779187A JP 779187 A JP779187 A JP 779187A JP S63175480 A JPS63175480 A JP S63175480A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- recess
- gate metal
- spacer insulating
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 16
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はリセス型MES FETの製造方法に関し、
特に、リセス型MES FETのゲート電極の形成方
法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a recessed MES FET,
In particular, the present invention relates to a method of forming a gate electrode of a recessed MES FET.
従来、リセス型MES FETのゲート電極形成方法
としては、第2図に示す様にゲートメタルの膜厚を大き
くするため、スペーサーとなる絶縁膜2を半導体基板(
ウェーハ)lの上に形成した後、フォトレジストを用い
てバターニングし、絶縁膜を開口し、リセス形成を行な
い、そのままゲートメタル4を蒸着法で付設し、リフト
オフ3行なって形成していた。Conventionally, as shown in FIG. 2, in order to increase the film thickness of the gate metal, the method for forming the gate electrode of a recessed MES FET is to deposit an insulating film 2, which will serve as a spacer, on a semiconductor substrate (
After forming on a wafer (1), patterning was performed using a photoresist, the insulating film was opened, a recess was formed, a gate metal 4 was attached by vapor deposition, and lift-off was performed three times.
上述したように、従来のゲート電極形成法では第2図の
ように余分な金属をリフトオフした後に、スペーサー絶
縁膜のひさしが残り、ひさし下のリセス表面の洗浄が充
分にはできないことや、ゲート電極形成後に、表面保護
のためのパッシベーション膜成長の際、ひさし下は被覆
が不充分になることや、デバイス全体での絶縁膜が多層
となり、ストレスが強くなる欠点がある。As mentioned above, in the conventional gate electrode formation method, after the excess metal is lifted off as shown in Figure 2, the eaves of the spacer insulating film remain, and the recess surface under the eaves cannot be sufficiently cleaned, and the gate When a passivation film is grown for surface protection after electrode formation, there are drawbacks such as insufficient coverage under the eaves, and the insulating film for the entire device becomes multilayered, resulting in increased stress.
本発明の目的は、ゲート金属を付着後余分な金属をリフ
トオフした後に、スペーサー絶縁膜のひさしが残らない
ようにし、その結果リセス表面の洗浄が充分にでき、表
面保護膜の形成が確実容易になり、又絶縁膜のストレス
を少くすることができるリセス型MES FETの製
造方法を提供することにある。The purpose of the present invention is to prevent the eaves of the spacer insulating film from remaining after depositing the gate metal and lifting off the excess metal.As a result, the recess surface can be sufficiently cleaned, and the formation of the surface protective film is reliably and easily made. Another object of the present invention is to provide a method for manufacturing a recessed MES FET that can reduce stress on an insulating film.
本発明のリセス型MES FETの製造方法は、半導
体基板上にゲート金属膜厚を厚くするためのスペーサー
用絶縁膜を形成する工程と、そのスペーサー用絶縁膜の
上にリセス用開口部を有するフォトレジストパターンを
形成する工程と、そのフォトレジストパターンをマスク
としてエツチングし半導体基板にリセスを形成する工程
と、そのリセス形成後にウェットエツチングしリセス上
部の絶縁膜を除去する工程と、ゲート金属を蒸着法で被
着する工程と、余分なゲート金属をリフトオフで除去す
る工程と、新たにフォトレジストを塗布し露光・現像し
て半導体基板上のゲート金属を被覆する工程と、残りの
前記絶縁膜を除去する工程とを含んで構成され、ゲート
金属膜厚を厚くし、かつひさしのないリセス型ME’S
、FETのゲート電極を付設できる特徴を有している。The method for manufacturing a recessed MES FET of the present invention includes the steps of forming a spacer insulating film for increasing the gate metal film thickness on a semiconductor substrate, and a photolithography process having a recess opening on the spacer insulating film. A process of forming a resist pattern, a process of etching the photoresist pattern as a mask to form a recess in the semiconductor substrate, a process of wet etching after forming the recess to remove the insulating film above the recess, and a process of depositing gate metal. a step of removing excess gate metal by lift-off, a step of applying a new photoresist, exposing and developing it to cover the gate metal on the semiconductor substrate, and removing the remaining insulating film. A recessed ME'S with a thick gate metal film and no eaves.
, it has the feature that a gate electrode of a FET can be attached.
次に、本発明の実施例について図面を参照して説明する
。第1図(a)〜(d)は本発明の一実施例を説明する
ために工程順に示した半導体素子の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.
まず、第1図(a>に示す様に半導体基板1の上にスペ
ーサー絶縁膜2を成長させ、次いでスペーサー絶縁膜2
の上にフォトレジストを塗布、露光・現像してリセス用
の開口部を有するフォトレジストパターン3を形成する
。次いで、ドライエツチングでスペーサー絶縁膜2をウ
ェットエツチングし、リセス端上部に、ひさしがなくな
るまでエツチング除去する。次いで、ゲート金属4を蒸
着し、図示のような構造を得る。First, a spacer insulating film 2 is grown on a semiconductor substrate 1 as shown in FIG.
A photoresist is applied thereon, exposed and developed to form a photoresist pattern 3 having an opening for a recess. Next, the spacer insulating film 2 is wet-etched by dry etching, and the upper part of the recess end is removed by etching until the eaves disappear. A gate metal 4 is then deposited to obtain the structure shown.
次に、第1図(b)に示す様に、リフトオフして余分な
ゲート金属を除去する。次いで、フォトレジストを新た
に塗布し、ゲート金属上部を完全に覆うように露光・現
像し、第1図(c)に示す様なフォトレジストパターン
5を形成する。次いで、スペーサー絶縁膜2をエツチン
グ除去する。Next, as shown in FIG. 1(b), the excess gate metal is removed by lift-off. Next, a new photoresist is applied, exposed and developed so as to completely cover the upper part of the gate metal, thereby forming a photoresist pattern 5 as shown in FIG. 1(c). Next, the spacer insulating film 2 is removed by etching.
次に、第1図(d)に示す様にフォトレジストパターン
5を除去する。しかるときは、リセス上部にひさしのな
いゲート金属のみを半導体基板上に付設した構造が得ら
れる。Next, the photoresist pattern 5 is removed as shown in FIG. 1(d). In this case, a structure can be obtained in which only the gate metal without an eaves above the recess is attached on the semiconductor substrate.
以上説明したように、本発明は、ゲート金属膜厚を厚く
するために、用いるスペーサー絶縁膜をウェットエツチ
ングでリセス上部から除去してからゲート金属を蒸着し
、リフトオフした後、ゲート金属上部を被覆するフォト
レジストを形成し、スペーサー絶縁膜をエツチング除去
して、その後、ゲート上部を被覆したフォトレジストを
除去することにより、リセスの上面にスペーサー絶縁膜
のひさしが残らなくなり、その結果リセス内の洗浄を完
全にし、パッシベーション膜の被覆性を改善し、さらに
、スペーサー絶縁膜を除去しているので、デバイス全体
での膜応力を減少することができる効果がある。As explained above, in order to increase the thickness of the gate metal film, the present invention removes the spacer insulating film from the upper part of the recess by wet etching, then evaporates the gate metal, lifts it off, and then coats the upper part of the gate metal. By forming a photoresist, etching away the spacer insulating film, and then removing the photoresist covering the upper part of the gate, no eaves of the spacer insulating film remain on the top surface of the recess, and as a result, the inside of the recess can be cleaned. Since the passivation film is completely covered, the passivation film coverage is improved, and the spacer insulating film is removed, the film stress in the entire device can be reduced.
第1図(a)〜(d)は本発明の一実施例を説明するた
めに工程順に示した半導体素子の要部の断面図、第2図
は従来の方法により形成されなリセス型MES FE
T素子の要部の断面図である。
1・・・半導体基板、2・・・スペーサー絶縁膜、3・
・・フォトレジストパターン、4・・・ゲート金属、5
・・・フォトレジストパターン。FIGS. 1(a) to (d) are cross-sectional views of essential parts of a semiconductor device shown in order of process to explain an embodiment of the present invention, and FIG. 2 is a recessed MES FE not formed by a conventional method.
FIG. 3 is a cross-sectional view of the main part of the T element. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Spacer insulating film, 3.
...Photoresist pattern, 4...Gate metal, 5
...Photoresist pattern.
Claims (1)
サー用絶縁膜を形成する工程と、該スペーサー用絶縁膜
の上にリセス用開口部を有するフォトレジストパターン
を形成する工程と、該フォトレジストパターンをマスク
としてエッチングし半導体基板にリセスを形成する工程
と、該リセス形成後にウェットエッチングしリセス上部
のスペーサー絶縁膜を除去する工程と、ゲート金属を蒸
着法で被着する工程と、余分なゲート金属をリフトオフ
で除去する工程と、新たにフォトレジストを塗布し露光
・現像して半導体基板上のゲート金属を被覆する工程と
、残りの前記スペーサー絶縁膜を除去する工程とを含む
ことを特徴とるリセス型MESFETの製造方法。A step of forming a spacer insulating film for increasing the gate metal film thickness on a semiconductor substrate, a step of forming a photoresist pattern having a recess opening on the spacer insulating film, and the photoresist pattern. a step of etching using the recess as a mask to form a recess in the semiconductor substrate, a step of wet etching after the recess formation to remove the spacer insulating film above the recess, a step of depositing gate metal by vapor deposition, and a step of removing excess gate metal. a step of removing the spacer insulating film by lift-off, a step of newly applying photoresist, exposing and developing it to cover the gate metal on the semiconductor substrate, and a step of removing the remaining spacer insulating film. Method of manufacturing type MESFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP779187A JPS63175480A (en) | 1987-01-14 | 1987-01-14 | Manufacture of recessed mesfet |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP779187A JPS63175480A (en) | 1987-01-14 | 1987-01-14 | Manufacture of recessed mesfet |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63175480A true JPS63175480A (en) | 1988-07-19 |
Family
ID=11675477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP779187A Pending JPS63175480A (en) | 1987-01-14 | 1987-01-14 | Manufacture of recessed mesfet |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63175480A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6051485A (en) * | 1997-04-24 | 2000-04-18 | Siemens Aktiengesellschaft | Method of producing a platinum-metal pattern or structure by a lift-off process |
JP2002329679A (en) * | 2001-04-27 | 2002-11-15 | New Japan Radio Co Ltd | Method of forming electrode for semiconductor device |
-
1987
- 1987-01-14 JP JP779187A patent/JPS63175480A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6051485A (en) * | 1997-04-24 | 2000-04-18 | Siemens Aktiengesellschaft | Method of producing a platinum-metal pattern or structure by a lift-off process |
JP2002329679A (en) * | 2001-04-27 | 2002-11-15 | New Japan Radio Co Ltd | Method of forming electrode for semiconductor device |
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