JPH02202030A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02202030A JPH02202030A JP2295289A JP2295289A JPH02202030A JP H02202030 A JPH02202030 A JP H02202030A JP 2295289 A JP2295289 A JP 2295289A JP 2295289 A JP2295289 A JP 2295289A JP H02202030 A JPH02202030 A JP H02202030A
- Authority
- JP
- Japan
- Prior art keywords
- organic material
- layer
- material layer
- metallic layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000011368 organic material Substances 0.000 claims abstract description 23
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 17
- 239000012044 organic layer Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体及び集積回路等の製造方法に関し、特
に、電極金属の微小配線を精度よく形成する技術に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing semiconductors, integrated circuits, etc., and particularly relates to a technique for forming minute interconnections of electrode metals with high precision.
従来の技術
従来、この種の電極形成技術としては、−船釣に真空中
における蒸着法、スパッタ法等により電極金属層を形成
し、しかるのちに感光性樹脂を使用して所望のパターン
を形成していた。Conventional technology Conventionally, this type of electrode formation technology includes: - Forming an electrode metal layer by vapor deposition, sputtering, etc. in a vacuum on a boat, and then forming a desired pattern using a photosensitive resin. Was.
発明が解決しようとする課題
しかしながら、上述した従来の方法は、配線間隔が狭く
なれば、金属層をパターンニングする為に施す紫外線感
光樹脂膜の解像度の問題から金属配線間で金属が接触す
るいわゆる短絡を生ぜしめ、特性不良となる場合があっ
た。この傾向は配線間隔が狭くなればなるほど発生頻度
は高くなる。Problems to be Solved by the Invention However, with the above-mentioned conventional method, as the wiring spacing becomes narrower, there is a problem with the resolution of the ultraviolet photosensitive resin film applied to pattern the metal layer. This may cause a short circuit, resulting in poor characteristics. This tendency occurs more frequently as the wiring spacing becomes narrower.
この課題を解決するために、従来は紫外線光量を弱くし
たり感光樹脂膜厚を薄くするなどの方法を検討してきた
。しかるに、光量不足に起因する樹脂の重合不十分、膜
厚が薄い為に生じる樹脂のピンホール等、パターンニン
グ不具合が多発するという欠点があった。In order to solve this problem, conventional methods have been considered such as weakening the amount of ultraviolet light and reducing the thickness of the photosensitive resin film. However, there have been disadvantages in that patterning defects occur frequently, such as insufficient polymerization of the resin due to insufficient light intensity and pinholes in the resin due to the thin film.
本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消し、精度良く金属層の微小パターンの配線を可能
とした半導体装置の新規な製造方法を提供することにあ
る。The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks inherent in the conventional technology and enables wiring of minute patterns of metal layers with high accuracy.
発明の従来技術に対する相違点
上述した従来技術の方法では、金属層に微小パターンを
形成する場合には配線間短絡及びピンホール等による金
属層の破壊が発生し１歩留り低下の原因となった。これ
に対して本発明は、金属層をパターンニングして配線を
形成すると同時に、その間にさらに配線を可能とし、上
記欠点を解決するという相違点を有する。Differences between the invention and the prior art In the method of the prior art described above, when a minute pattern is formed on a metal layer, short circuits between wirings and destruction of the metal layer due to pinholes occur, resulting in a decrease in yield by one. On the other hand, the present invention has a difference in that the metal layer is patterned to form wiring, and at the same time, further wiring can be formed in the meantime, thereby solving the above-mentioned drawbacks.
課題を解決するための手段
前記目的を達成する為に、本発明に係る半導体装置の製
造方法は、金属層に感光性樹脂を塗布し、これをパター
ンニングし、さらに、有機物質層を形成した後にこれを
パターンニングし、所望の配線を形成するためのエツチ
ングをする。その後、前記金属層、フォトレジスト層及
び有機物質層等の上から金属層を形成し、不要領域の金
属層及びフォトレジスト層、有機物質層を除去すること
を特徴としている。Means for Solving the Problems In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes applying a photosensitive resin to a metal layer, patterning the same, and further forming an organic material layer. This is later patterned and etched to form desired wiring. Thereafter, a metal layer is formed on the metal layer, photoresist layer, organic material layer, etc., and unnecessary areas of the metal layer, photoresist layer, and organic material layer are removed.
この場合、第１の金属配線に対し、第２の金属配線はセ
ルファラインされており第１の金属層に対し等間隔の位
置になる。従って、微小配線を精度良くパターンニング
することを可能ならしめる特徴を有している。In this case, the second metal wiring is self-lined with respect to the first metal wiring, and is positioned at equal intervals with respect to the first metal layer. Therefore, it has a feature that allows fine wiring to be patterned with high precision.
実施例
次に本発明をその好ましい各実施例について図面を参照
して具体的に説明する。EXAMPLES Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明するた
めの工程を示す断面図であり、（ａ）は完成された断面
を示す。FIGS. 1(a) to 1(f) are cross-sectional views showing steps for explaining an embodiment of the present invention, and FIG. 1(a) shows a completed cross-section.
第１図（ａ）〜（ｆ）を参照するに、第１図（ｂ）に示
すように半導体基板１に第１の金属層２（本実施例では
アルミニウム層を２μ）を形成し１次に第１の有機物質
層３（本実施例ではポジタイプフォトレジスト０ＦＰＲ
８００を使用）を形成したのちにこれをパターンニング
する。Referring to FIGS. 1(a) to (f), as shown in FIG. 1(b), a first metal layer 2 (in this example, the aluminum layer is 2μ) is formed on a semiconductor substrate 1. and a first organic material layer 3 (in this example, a positive type photoresist 0FPR).
800) is formed and then patterned.
次いで第１図（ｃ）に示すように、第２の有機物質層４
を（本実施例ではポリイミド樹脂ＰＩＸを使用）を形成
し、さらに第３の有機物質層５（本実施例ではネガタイ
プフォトレジスト使用）を形成し、続いて第１ＵＡ（ｄ
）に示すごとく、これを第１の開口領域３′を含む領域
を窓開け（開口部５゛）する。Next, as shown in FIG. 1(c), a second organic material layer 4 is formed.
(polyimide resin PIX is used in this embodiment), a third organic material layer 5 (negative type photoresist is used in this embodiment), and then the first UA (d
), the area including the first opening area 3' is opened (opening 5').
次にこの有機物質層をマスキングとして該有機物質層４
を除去しく本実施例では酸素グラズマを用いて約１５分
間実施）、第１の金属層２を露出させる０次にこの金属
層２を除去する。Next, using this organic material layer as a mask, the organic material layer 4 is
In this example, the metal layer 2 is removed to expose the first metal layer 2.
本実施例ではリン酸系のエッチャントを使用し、６０℃
で１５分間実施した。これにより第１の金属層２は横方
向にもエツチングされ、第１図（ｅ）に示す空間５″が
形成される。In this example, a phosphoric acid-based etchant was used, and the
It was carried out for 15 minutes. As a result, the first metal layer 2 is also etched in the lateral direction, forming a space 5'' shown in FIG. 1(e).
次に再度金属層２′を形成（本実施例ではアルミニウム
層を２μ形成）し、しかるのちに前記有機物質層３．４
，５及び金属層２′を有機溶剤中に浸し、綿花或いは超
音波をかけてｌｆｌ［的に不要部を除去する。これによ
り完成したものが第１図（ａ）である。Next, a metal layer 2' is formed again (in this example, an aluminum layer of 2μ is formed), and then the organic material layer 3.4 is formed.
, 5 and the metal layer 2' are immersed in an organic solvent, and unnecessary parts are removed using cotton or ultrasonic waves. The completed product is shown in FIG. 1(a).
次に本発明による他の実施例について説明するに、第１
図（ｃ）に示す様に、半導体基板ｌに第１の金属層２を
形成し、さらに第１の有機物質層３を形成したのちに第
２の有機物質層４を形成する場合に、上記実施例では、
ポリイミド樹脂を使用したが、この代わりに感光性ポリ
イミドを使用しても良い。Next, other embodiments according to the present invention will be described.
As shown in Figure (c), when forming the first metal layer 2 on the semiconductor substrate l, further forming the first organic material layer 3, and then forming the second organic material layer 4, the above-mentioned In the example,
Although polyimide resin was used, photosensitive polyimide may be used instead.
この場合には、直接１選択的に所望部の窓開けが可能で
あり、上記実施例で示した場合よりも工程が短くなる利
点がある。In this case, it is possible to directly and selectively open a window in a desired part, and there is an advantage that the process is shorter than in the case shown in the above embodiment.
発明の詳細
な説明したように、本発明によれば、半導体基板に配線
間隔の短い電極金属層をパターンニングする場合におい
て予め形成した金属配線間に、セルフアライメント方式
でさらに配線を形成することにより、精度良く微小パタ
ーンの配線を可能ならしめる効果が得られる。DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, when patterning an electrode metal layer with short wiring intervals on a semiconductor substrate, further wiring is formed between pre-formed metal wirings using a self-alignment method. , it is possible to achieve the effect of making it possible to wire minute patterns with high precision.
第１図（ａ）〜（「）は本発明の一実施例を説明するた
めに示した断面図である。
１・・・半導体基板、２．２′・・・第１及び第２の金
属層（アルミニウム層）、３．３’・・・第１の有機物
質層（ポジ型フオトレジス１−）ａＬ”開口部、４・・
・第２の有機物質層（ポリイミド樹脂）、５゜５′、５
″・・・第３の有ｅｌｌ物質層（ネガ型フォトレジスト
）及び開口部FIGS. 1(a) to 1(a) are cross-sectional views shown to explain one embodiment of the present invention. 1...Semiconductor substrate, 2.2'...First and second metals layer (aluminum layer), 3.3'...first organic material layer (positive photoresist 1-) aL'' opening, 4...
・Second organic material layer (polyimide resin), 5°5', 5
″...Third ELL material layer (negative photoresist) and opening
Claims (1)
金属層上に第１の有機物質層を形成する工程と、さらに
前記第１とは異なった第２の有機物質層を形成する工程
と、これをパターンニングし所望の窓開けをする工程と
、前記第１の金属層を横方向に除去する工程と、しかる
のちに第２の金属層を形成する工程と、前記第１及び第
２の有機物質層を除去する工程とからなり、前記第１及
び第２の金属層を精度良く形成することを特徴とする半
導体装置の製造方法。forming a first metal layer on a semiconductor substrate; forming a first organic material layer on the first metal layer; and further forming a second organic material layer different from the first. patterning the first metal layer to form a desired window; laterally removing the first metal layer; thereafter forming a second metal layer; and a step of removing a second organic material layer, and forming the first and second metal layers with high precision.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2295289A JPH02202030A (en) | 1989-01-31 | 1989-01-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2295289A JPH02202030A (en) | 1989-01-31 | 1989-01-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02202030A true JPH02202030A (en) | 1990-08-10 |
Family
ID=12096950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2295289A Pending JPH02202030A (en) | 1989-01-31 | 1989-01-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02202030A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5474956A (en) * | 1995-03-14 | 1995-12-12 | Hughes Aircraft Company | Method of fabricating metallized substrates using an organic etch block layer |
-
1989
- 1989-01-31 JP JP2295289A patent/JPH02202030A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5474956A (en) * | 1995-03-14 | 1995-12-12 | Hughes Aircraft Company | Method of fabricating metallized substrates using an organic etch block layer |
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