JPS6148771B2 - - Google Patents
Info
- Publication number
- JPS6148771B2 JPS6148771B2 JP10345479A JP10345479A JPS6148771B2 JP S6148771 B2 JPS6148771 B2 JP S6148771B2 JP 10345479 A JP10345479 A JP 10345479A JP 10345479 A JP10345479 A JP 10345479A JP S6148771 B2 JPS6148771 B2 JP S6148771B2
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- layer
- positive resist
- resist layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 62
- 238000010894 electron beam technology Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】
本発明は電子ビームにより半導体基板上のポジ
レジスト層に直接描画を行う電子ビーム露光方法
の改良に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an electron beam exposure method for directly writing on a positive resist layer on a semiconductor substrate using an electron beam.
集積回路等の半導体装置の製造に於いて、集積
度向上とともに多層配線層等を形成するに際して
電子ビームによる直接描画を繰り返えして、配線
パターンやコンタクトホールを半導体チツプ上に
重ねて形成する方法が用いられるようになつて来
た。 In the manufacture of semiconductor devices such as integrated circuits, as the degree of integration increases, when forming multilayer wiring layers, etc., direct drawing with an electron beam is repeated to form wiring patterns and contact holes on semiconductor chips. methods have come into use.
この電子ビームによる直接描画の方法は、エツ
チング凹部等による位置合わせマークを有するチ
ツプ領域が形成された半導体基板にポジレジスト
層を被着し、該基板上の各チツプごとに、電子ビ
ームにより位置合わせマーク上を走査して位置決
めを行つた後、電子ビームにより該チツプ上にパ
ターンの描画を行う方法である。 In this method of direct writing using an electron beam, a positive resist layer is applied to a semiconductor substrate on which a chip region having alignment marks such as etched recesses is formed, and each chip on the substrate is aligned using an electron beam. In this method, a mark is scanned for positioning, and then a pattern is drawn on the chip using an electron beam.
然して該方法に於いては、位置合わせとパター
ン描画を同一強度の電子ビームによつて行うの
で、位置合わせマーク上を電子ビームで走査して
位置合わせを行つた際に、該走査部のポジレジス
トが他の描画部分と同様に電子ビームにより分解
せしめられるので、該基板の現像を行つて前記描
画部のポジレジスト層を溶解除去し基板上のポジ
レジスト層に蝕刻用窓を形成させる際に、前記位
置合わせに際して電子ビームにより分解せしめら
れた位置合わせマーク附近のポジレジスト層も溶
解除去せしめられ、位置合わせマーク上のポジレ
ジスト層に細い窓部が形成される。 However, in this method, alignment and pattern drawing are performed using an electron beam of the same intensity, so when alignment is performed by scanning the alignment mark with the electron beam, the positive resist of the scanning section is is decomposed by the electron beam in the same way as other drawn areas, so when the substrate is developed and the positive resist layer in the drawn area is dissolved and removed to form an etching window in the positive resist layer on the substrate, During the alignment, the positive resist layer near the alignment mark, which has been decomposed by the electron beam, is also dissolved and removed, and a narrow window is formed in the positive resist layer above the alignment mark.
そのために次工程で該基板をエツチングして基
板上に蝕刻パターンを形成させる際に、前記位置
合わせマーク部にも例えば第１図に示すように位
置合わせマーク１に交わる細い蝕刻溝２及び２′
等が形成され、位置合わせマークは変形せしめら
れるので、該基板上に更に堆積させた層に前記蝕
刻パターンに対して精密に重ねられるパターンを
前記位置合わせマークを再度使用して電子ビーム
により描画することは困難になる。 Therefore, when the substrate is etched in the next step to form an etched pattern on the substrate, the alignment mark portions are also etched, for example, as shown in FIG.
etc. are formed, and the alignment mark is deformed. Then, a pattern that is precisely overlapped with the etched pattern is written on a further layer deposited on the substrate using the alignment mark again with an electron beam. things become difficult.
そこで従来は例えば第２図に示すように直接描
画の回数即ち位置合わせの回数に応じた複数組の
位置合わせマーク１ａ，１a′，１ｂ，１b′，１
ｃ，１c′及ぶ１ｄ，１d′を同一チツプ領域３上に
形成しておいて、位置合せのたびごとに異なる位
置合わせマークを使用する方法が行われていた。 Therefore, conventionally, for example, as shown in FIG. 2, multiple sets of alignment marks 1a, 1a', 1b, 1b', and
A method has been used in which marks c, 1c' and 1d, 1d' are formed on the same chip area 3, and a different alignment mark is used each time alignment is performed.
然し該従来方法に於いては同一チツプ上に例え
ば通常多層配線等の形成に於いては４〔組〕（８
〔個〕）以上の位置合わせマークを形成しなければ
ならないので、チツプの実効面積を減少させ、集
積回路等の集積度を低下させるという問題があつ
た。 However, in the conventional method, when forming multilayer wiring, etc. on the same chip, 4 [sets] (8
Since it is necessary to form more than one alignment mark, there is a problem in that the effective area of the chip is reduced and the degree of integration of the integrated circuit, etc. is reduced.
本発明は上記問題点に鑑み、、同一位置合わせ
マークを繰り返えし使用することを可能にする直
接描画方式の電子ビーム露光方法を提供する。 In view of the above problems, the present invention provides a direct writing electron beam exposure method that allows the same alignment mark to be used repeatedly.
即ち本発明は半導体基板面にポジレジスト層を
被着し、該ポジレジスト層に直接描画を行う電子
ビーム露光方法に於いて、該基板面のチツプ領域
内に１〔組〕ずつ形成されているそれぞれのチツ
プの位置合わせマークを用いて、通常の露光強度
の電子ビームによりチツプの位置合わせを行い、
続いて該チツプ上へのパターン描画を完了させて
後、引き続いて前記位置合わせマークを覆う所定
領域のポジレジスト層に電子ビームを強く照射
し、該領域のポジレジスト層をネガ化せしめて、
該領域に位置合わせマークの保護層を形成するこ
とを特徴とする。 That is, the present invention uses an electron beam exposure method in which a positive resist layer is deposited on the surface of a semiconductor substrate and drawing is performed directly on the positive resist layer, and one set of chips is formed in each chip area on the substrate surface. Using the alignment marks on each chip, align the chips with an electron beam of normal exposure intensity.
Subsequently, after completing pattern drawing on the chip, a predetermined area of the positive resist layer covering the alignment mark is irradiated with a strong electron beam to make the positive resist layer in the area negative,
The method is characterized in that a protective layer for the alignment mark is formed in the area.
以下本発明を図示実施例により詳細に説明す
る。 The present invention will be explained in detail below with reference to illustrated embodiments.
第３図ａ乃至ｈは本発明の直接描画方式による
電子ビーム露光方法を含む、多層配線形成方法に
おける一実例の工程説明図である。 FIGS. 3A to 3H are process explanatory diagrams of an example of a multilayer interconnection forming method including an electron beam exposure method using a direct writing method according to the present invention.
本発明の方法を用いて、例えばシリコン集積回
路等の半導体基装置の多層配線層を形成するに際
しては、第３図ａに示すように各種機能素子が形
成され、スクライブ・ラインによりチツプ領域が
形成され、該チツプ領域に凹部からなる位置合わ
せマーク１（２〔個〕１〔組〕）で形成されるが
図には１〔個〕のみ表示する）が形成された表面
に二酸化シリコン（SiO2）層４を有するシリコン
（Si）基板５上に、0.5〜１〔μｍ〕程度の厚さに
ポジレジスト層６を被着して後、該基板を電子ビ
ーム露光装置内に固定し、先ず該基板の位置合わ
せマーク１上を電子ビーム７により通常の描画と
同じ走査スピードで走査して該基板の位置合わせ
を行う。 When forming a multilayer wiring layer of a semiconductor-based device such as a silicon integrated circuit using the method of the present invention, various functional elements are formed as shown in FIG. 3a, and a chip area is formed by scribe lines. Silicon dioxide (SiO 2 ) After depositing a positive resist layer 6 to a thickness of about 0.5 to 1 [μm] on a silicon (Si) substrate 5 having a layer 4, the substrate is fixed in an electron beam exposure device, and first the The substrate is aligned by scanning the alignment mark 1 on the substrate with the electron beam 7 at the same scanning speed as normal drawing.
次に第３図ｂに示すように該基板上のポジレジ
スト層６に位置合わせの際の走査スピードで電子
ビーム７により走査して、電極コンタクト窓パタ
ーン８を描画して後、引続いて前記位置合わせマ
ーク１及びその周囲の位置合わせに際して電子ビ
ームで走査した領域を含むポジレジスト層を、例
えばパターン描画の際の走査スピードの1/2〜1/3
程度の遅い走査スピードで電子ビーム９により走
査し、該領域のポジレズスト層を強く感光させて
ポジレジストのネガ化層１０を形成させる。 Next, as shown in FIG. 3b, an electrode contact window pattern 8 is drawn by scanning the positive resist layer 6 on the substrate with an electron beam 7 at the scanning speed used for alignment. The positive resist layer, including the area scanned by the electron beam during alignment of alignment mark 1 and its surroundings, is heated at, for example, 1/2 to 1/3 of the scanning speed during pattern drawing.
The electron beam 9 is scanned at a relatively slow scanning speed to strongly expose the positive resist layer in the area to form a negative layer 10 of positive resist.
そして次に該基板を現像して通常の走査スピー
ドで電子ビームを走査して描画した電極コンタク
ト窓パターン８部のポジレジスト層を溶解除去
し、第３図ｃに示すように基板上のポジレジスト
層６に電極コンタクト窓形成用のエツチング窓１
１を形成する。 Then, the substrate is developed and the positive resist layer of 8 portions of the drawn electrode contact window pattern is dissolved and removed by scanning the electron beam at a normal scanning speed, and the positive resist layer on the substrate is removed as shown in FIG. 3c. Etching window 1 for forming electrode contact window in layer 6
form 1.
なおこの際前記位置合わせの際に通常の走査ス
ピードの電子ビームによつて走査された位置合わ
せ領域のポジレジスト層は、上記描画工程に於い
てネガ化層１０に変質せしめられているので、現
像により溶解除去されることがない。 At this time, since the positive resist layer in the alignment area scanned by the electron beam at the normal scanning speed during the alignment has been changed into the negative layer 10 in the drawing process, it is difficult to develop it. It will not be dissolved and removed by
次に該基板をふつ酸（HF）等を主成分とする
エツチング液でエツチングして後、基板面のポジ
レジスト層６及びネガ化層１０をプラズマ・アツ
シヤー等により除去して、第３図ｄに示すように
Si基板５上のSiO2層４に電極コンタクト窓１２を
形成する。 Next, after etching the substrate with an etching solution mainly composed of hydrofluoric acid (HF) or the like, the positive resist layer 6 and the negative layer 10 on the substrate surface are removed by a plasma atsher or the like, and as shown in FIG. as shown in
An electrode contact window 12 is formed in the SiO 2 layer 4 on the Si substrate 5.
然して上記エツチングに際して該基板面の位置
合わせ領域はポジレジストのネガ化層で覆われて
いるので位置合わせマーク１は変形されることが
なく、原形のまま基板面に残留する。 However, during the etching process, since the alignment area on the substrate surface is covered with a negative layer of positive resist, the alignment mark 1 is not deformed and remains in its original shape on the substrate surface.
次に第３図ｅに示すように該基板上に5000
〔Å〕程度の厚さのアルミニウム（Al）層１３を
蒸着等により被着して後、該Al層１３上に0.5〜
１〔μｍ〕程度の厚さのポジレジスト層６を被着
させ、該基板を電子ビーム露光装置内に固定し、
前記電極コンタクト窓形成の際の露光の場合と同
様に、先づ該基板上に残留している位置合わせマ
ーク１上を通常の走査スピードの電子ビーム７に
より走査し位置合わせを行う。 Next, as shown in Figure 3e, 5000
After depositing an aluminum (Al) layer 13 with a thickness of about [Å] by vapor deposition or the like, a layer of 0.5~
A positive resist layer 6 with a thickness of about 1 [μm] is deposited, and the substrate is fixed in an electron beam exposure apparatus,
As in the exposure for forming the electrode contact window, first, the alignment mark 1 remaining on the substrate is scanned by the electron beam 7 at a normal scanning speed to perform alignment.
次に第３図ｆに示すようにポジレジスト層６の
電極パターン形成部を除いた領域に通常の走査ス
ピードで電子ビーム７により走査してAl層除去
領域１４の描画を行つて後、引続いて前記位置合
わせマーク１及びその周囲の位置合わせに際して
電子ビームで走査した領域を含むポジレジスト層
を例えばパターン描画の際の走査スピードの1/2
〜1/3程度の遅い走査スピードで電子ビーム９に
より走査し、該領域のポジレジスト層を強く感光
させてポジレジストのネガ化層１０を形成させ
る。 Next, as shown in FIG. 3f, the area of the positive resist layer 6 excluding the electrode pattern forming area is scanned with the electron beam 7 at a normal scanning speed to draw the Al layer removal area 14, and then The positive resist layer including the alignment mark 1 and the region scanned by the electron beam for alignment around the alignment mark 1 is heated at, for example, 1/2 of the scanning speed used for pattern drawing.
The electron beam 9 is scanned at a slow scanning speed of about 1/3 to 1/3 to strongly expose the positive resist layer in the region to form a negative layer 10 of the positive resist.
そして該基板を現像して、第３図ｇに示すよう
に基板面に電極パターン形成領域上のポジレジス
トマスク層１５及び位置合わせマーク領域上のポ
ジレジストのネガ化層１０を残留させ、該基板を
例えばリン酸（H3PO4）等を主成分とするエツチ
ング液に浸漬して、基板面に露出しているAl層
を溶解除去して後、プラズマ・アツシヤー等によ
り基板面のポジレジストマスク層１５及びネガ化
層１０を除去して、第３図ｈに示すようにSi基板
５上のSiO2層４に形成された電極コンタクト窓
１２の部分にAl電極層１６を形成させる。 Then, the substrate is developed to leave the positive resist mask layer 15 on the electrode pattern forming area and the negative resist layer 10 on the alignment mark area on the substrate surface as shown in FIG. For example, the aluminum layer exposed on the substrate surface is dissolved and removed by immersing it in an etching solution mainly composed of phosphoric acid (H 3 PO 4 ), etc., and then a positive resist mask is applied to the substrate surface using a plasma assher or the like. The layer 15 and the negative layer 10 are removed, and an Al electrode layer 16 is formed at the electrode contact window 12 formed in the SiO 2 layer 4 on the Si substrate 5, as shown in FIG. 3h.
然して上記Al層のエツチングに際して位置合
わせマーク領域はポジレジストのネガ化層１０で
覆われており蝕刻されることがないので、ネガ化
層１０を除去した後に、表面にAl層１３が被着
され正確な寸法形状を保つた位置合わせマーク１
が残る。以下の工程は図示しないが、上記と同様
の方法により、同一位置合わせマークを使用して
上記Al電極層上に堆積させた例えばりん珪酸ガ
ラス（PSG）等の絶縁層に対してのコンタクト窓
の形成及び更に上記絶縁層上に被着させたAl層
に対する配線パターンの形成等を行つて、多層配
線構造の集積回路チツプを形成させる。 However, when etching the Al layer, the alignment mark area is covered with the negative layer 10 of the positive resist and is not etched, so after the negative layer 10 is removed, the Al layer 13 is deposited on the surface. Alignment mark 1 that maintains accurate dimensions and shape
remains. Although the following steps are not shown, a contact window is formed on the insulating layer, such as phosphosilicate glass (PSG), deposited on the Al electrode layer using the same alignment mark using the same method as above. A wiring pattern is formed on the Al layer deposited on the insulating layer, and an integrated circuit chip having a multilayer wiring structure is formed.
上記実施例に於いては本発明をシリコン集積回
路の多層配線形成に適用する場合について説明し
たが、本発明の方法は上記に限らず複数回の電子
ビームの直接描画により半導体基板上の各種機能
パターンの形成を行う電子ビーム露光に対しては
総て適用可能である。 In the above embodiments, the present invention is applied to the formation of multilayer wiring of silicon integrated circuits. However, the method of the present invention is not limited to the above. All methods are applicable to electron beam exposure for forming patterns.
以上説明したように本発明の方法によれば、複
数回の直接描画方式の電子ビーム露光により半導
体基板上に各種機能パターンを形成する半導体集
積回路等の製造に於いてチツプ領域には１〔組〕
の位置合わせマークを形成すれば良いので、チツ
プの有効面積が増大し、集積回路等の半導体装置
の集積度を向上せしめることができる。 As explained above, according to the method of the present invention, in the manufacture of semiconductor integrated circuits, etc., in which various functional patterns are formed on a semiconductor substrate by multiple direct writing electron beam exposures, one set of ]
Since it is only necessary to form the alignment marks, the effective area of the chip can be increased, and the degree of integration of semiconductor devices such as integrated circuits can be improved.
第１図は従来の電子ビーム直接描画方法に於け
る位置合わせマークの変形を示す図、第２図は従
来の位置合わせマーク配置図、第３図ａ乃至ｈは
本発明の直接描画方式による電子ビーム露光方法
を含む多層配線形成方法における一実施例の工程
説明図である。
図において、１，１ａ，１ｂ，１ｃ，１ｄ，１
a′，１b′，１c′，１d′は位置合わせマーク、２，
２′は蝕刻溝、３はチツプ領域、４は二酸化シリ
コン層、５はシリコン基板、６はポジレジスト
層、７は通常走査スピードの電子ビーム、８は電
極コンタクトパターン、９は遅い走査スピードの
電子ビーム、１０はネガ化層、１１はエツチング
窓、１２は電極コンタクト窓、１３はアルミニウ
ム層、１４はアルミニウム層除去領域、１５はポ
ジレジストマスク層、１６はアルミニウム電極
層。
Fig. 1 is a diagram showing a modification of the alignment mark in the conventional electron beam direct writing method, Fig. 2 is a diagram showing the arrangement of the conventional alignment mark, and Figs. FIG. 2 is a process explanatory diagram of an embodiment of a multilayer interconnection forming method including a beam exposure method. In the figure, 1, 1a, 1b, 1c, 1d, 1
a', 1b', 1c', 1d' are alignment marks, 2,
2' is an etched groove, 3 is a chip region, 4 is a silicon dioxide layer, 5 is a silicon substrate, 6 is a positive resist layer, 7 is an electron beam at normal scanning speed, 8 is an electrode contact pattern, 9 is an electron beam at slow scanning speed 10 is a negative layer, 11 is an etching window, 12 is an electrode contact window, 13 is an aluminum layer, 14 is an aluminum layer removal area, 15 is a positive resist mask layer, and 16 is an aluminum electrode layer.
Claims (1)
ポジレジスト層に直接描画を行う電子ビーム露光
方法に於いて、該基板面のチツプ領域内に１
〔組〕ずつ形成されているそれぞれのチツプの位
置合わせマークを用いて、通常の露光強度の電子
ビームによりチツプの位置合わせを行い、続いて
該チツプ上へのパターン描画を完了させて後、引
き続いて前記位置合わせマークを覆う所定領域の
ポジレジスト層に電子ビームを強く照射し、該領
域のポジレジスト層をネガ化せしめて、該領域に
位置合わせマークの保護層を形成することを特徴
とする電子ビーム露光方法。[Claims] 1. In an electron beam exposure method in which a positive resist layer is deposited on the surface of a semiconductor substrate and drawing is performed directly on the positive resist layer, 1.
Using the alignment marks for each chip formed in groups, the chips are aligned using an electron beam of normal exposure intensity, and then, after completing pattern drawing on the chip, The positive resist layer in a predetermined area covering the alignment mark is strongly irradiated with an electron beam to make the positive resist layer in the area negative, thereby forming a protective layer for the alignment mark in the area. Electron beam exposure method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10345479A JPS5627929A (en) | 1979-08-14 | 1979-08-14 | Electron beam projection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10345479A JPS5627929A (en) | 1979-08-14 | 1979-08-14 | Electron beam projection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5627929A JPS5627929A (en) | 1981-03-18 |
| JPS6148771B2 true JPS6148771B2 (en) | 1986-10-25 |
Family
ID=14354464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10345479A Granted JPS5627929A (en) | 1979-08-14 | 1979-08-14 | Electron beam projection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5627929A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046845A1 (en) * | 1999-02-02 | 2000-08-10 | Nikon Corporation | Method for detecting alignment mark in charged particle beam exposure apparatus |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5793133U (en) * | 1980-11-28 | 1982-06-08 | ||
| JPS6066428A (en) * | 1983-09-21 | 1985-04-16 | Fujitsu Ltd | Electron beam exposing method |
| JPH0782978B2 (en) * | 1985-01-22 | 1995-09-06 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JPH04101411A (en) * | 1990-08-20 | 1992-04-02 | Matsushita Electric Ind Co Ltd | Method of aligning electron-beam direct writing |
-
1979
- 1979-08-14 JP JP10345479A patent/JPS5627929A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000046845A1 (en) * | 1999-02-02 | 2000-08-10 | Nikon Corporation | Method for detecting alignment mark in charged particle beam exposure apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5627929A (en) | 1981-03-18 |
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