JPH0782978B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0782978B2 JPH0782978B2 JP60010416A JP1041685A JPH0782978B2 JP H0782978 B2 JPH0782978 B2 JP H0782978B2 JP 60010416 A JP60010416 A JP 60010416A JP 1041685 A JP1041685 A JP 1041685A JP H0782978 B2 JPH0782978 B2 JP H0782978B2
- Authority
- JP
- Japan
- Prior art keywords
- position detection
- electron beam
- film
- mark
- detection mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 38
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000001514 detection method Methods 0.000 claims description 39
- 238000010894 electron beam technology Methods 0.000 claims description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 30
- 239000000758 substrate Substances 0.000 description 18
- 239000005360 phosphosilicate glass Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子ビーム露光法を用いる、半導体装置の製
造において、ウエハー上に設けられた、位置検出マーク
の表面処理のプロセスに関する。The present invention relates to a process of surface treatment of a position detection mark provided on a wafer in the manufacture of a semiconductor device using an electron beam exposure method.
半導体装置の集積度の向上に伴って、微細パターンの形
成手段として、電子ビームを用いるリソグラフイが、従
来のフオトリソグラフイに代わって用いられつつある。As the degree of integration of semiconductor devices has improved, lithography using an electron beam is being used instead of conventional photolithography as a means for forming a fine pattern.
電子ビーム露光装置を用いてLSIを製造する場合、例え
ばシリコン基板上の電子ビーム感光材に、所定の図形
を、直接描画した後、現像およびエッチング処理を行
い、再び電子ビーム感光材を塗布して、異なった図形を
電子ビーム露光する方法が屡行われる。When an LSI is manufactured using an electron beam exposure apparatus, for example, a predetermined figure is directly drawn on an electron beam photosensitive material on a silicon substrate, then development and etching processes are performed, and the electron beam photosensitive material is applied again. , A method of electron beam exposure of different figures is often used.
このような数次にわたる露光図形を、正確に所定の位置
に描画するために、通常シリコン基板上に、位置検出用
マークを形成しておき、電子ビームでマークを検出する
ことにより、露光パターンの位置を正確に割り出してい
る。In order to accurately draw such an exposure pattern over several orders at a predetermined position, a position detection mark is usually formed on a silicon substrate, and the mark is detected by an electron beam to form an exposure pattern. The position is accurately determined.
位置検出マークを設ける場所としては、特別に位置検出
用のチップを設けるとか、チップ内の素子形成に影響を
あたえない空場所、あるいはスクライブライン上等が用
いられる。As a place where the position detection mark is provided, a chip for position detection is specially provided, an empty place which does not affect the element formation in the chip, or a scribe line is used.
位置検出用マークの形状は、種々の方法が考えられてい
るが、一般的にシリコン基板上に、エッチングによって
穴または溝を設けるとか、蒸着により山を設けることが
行われている。Although various methods have been considered for the shape of the position detection mark, generally, a hole or groove is provided on the silicon substrate by etching, or a mountain is provided by vapor deposition.
以下図面により具体的に説明する。第２図は一般的な電
子ビーム露光装置の露光部の概略を示す。数段の電子ビ
ーム収束レンズ系、および偏向電極系を経て、電子ビー
ム１は細いビームとなって、シリコン基板２に照射され
る。シリコン基板よりの反射電子、または二次電子は検
知器３によって検知され、信号処理回路を経て電子計算
機４に送られる。A specific description will be given below with reference to the drawings. FIG. 2 shows an outline of an exposure unit of a general electron beam exposure apparatus. The electron beam 1 becomes a narrow beam through the electron beam converging lens system and the deflection electrode system of several stages, and is irradiated onto the silicon substrate 2. Reflected electrons or secondary electrons from the silicon substrate are detected by the detector 3 and sent to the electronic computer 4 via the signal processing circuit.
第３図（ａ），（ｂ）はシリコン基板に設けられた、一
般的な位置検出マークの形状の上面図および断面図で、
この場合、正方形の孔が設けられている。電子ビームが
左から右とＡ−Ａ方向に、掃引したとき検知器には第４
図のごとき雑音を含んだ信号があらわれる。複数回、掃
引を繰り返し、更に微分回路を通すことによって、平均
をとると、第５図のごとき平滑化された信号を得る。3 (a) and 3 (b) are a top view and a cross-sectional view of the shape of a general position detection mark provided on a silicon substrate.
In this case, square holes are provided. When the electron beam is swept from left to right and AA direction
A signal containing noise as shown in the figure appears. The sweep is repeated a plurality of times, and the signal is smoothed as shown in FIG. 5 by taking an average by passing through a differentiating circuit.
位置マークの中心部の位置は、第５図の上下に現れた信
号の中間点、Ｂを求めることにより、一軸方向、例えば
Ｘ座標が決定出来る。このようにマークの中心点の位置
のX,Y座標を、シリコン基板上で最低二個所、検知すれ
ば基板上でのすべてのＸ、Ｙ座標が決定するので、あと
は電子計算機に記録された露光パターンに従って、電子
ビーム露光を行う。The position of the central portion of the position mark can be determined in the uniaxial direction, for example, the X coordinate, by obtaining the intermediate point B of the signals appearing at the top and bottom of FIG. In this way, the X and Y coordinates of the position of the center point of the mark are determined at least at two points on the silicon substrate, and if detected, all the X and Y coordinates on the substrate are determined, so the rest is recorded in the computer. Electron beam exposure is performed according to the exposure pattern.
LSIの製造は、最初の工程から完成するまでの間に、シ
リコン基板の表面に、酸化、不純物導入、薄膜形成等の
工程とレジスト塗布、パターンニング、エッチング等の
リソグラフイ工程が繰り返し何回も行われる。In the manufacturing of LSI, from the first step to the completion, steps such as oxidation, impurity introduction, thin film formation, etc. and lithographic steps such as resist coating, patterning, etching etc. are repeated many times on the surface of the silicon substrate. Done.
これらのリソグラフイ工程を、すべて電子ビーム露光方
法に依存することは、必ずしも効率的でない。パターン
ニングの精度が比較的低い場合は、マスクを用いたフオ
トリソグラフイ法で、精度の高いパターンニングは、電
子ビーム露光法をと、一つの基板の処理において混用し
て用いるのがよい。It is not always efficient to rely on electron beam exposure methods for all these lithographic steps. When the accuracy of patterning is relatively low, it is preferable to use the photolithography method using a mask, and for the patterning with high accuracy, the electron beam exposure method and the electron beam exposure method may be used in combination in the processing of one substrate.
電子ビーム露光用に設けられる、位置検出マークは、最
初の電子ビーム露光法を適用する場合に形成されるが、
それ以後のプロセスにおいて、位置検出マークの形状の
変化のないことが必要である。The position detection marks provided for electron beam exposure are formed when the first electron beam exposure method is applied.
In the subsequent process, it is necessary that the shape of the position detection mark does not change.
特にマークの段差部の形状がシヤープに表れていない
と、検出信号の感度の低下、雑音の混入等により、最終
的な位置情報の精度が低下、あるいは位置検出不能とな
る場合も起こり得る。In particular, if the shape of the step portion of the mark does not appear sharply, the accuracy of the final position information may decrease or the position may not be detected due to a decrease in the sensitivity of the detection signal, the inclusion of noise, and the like.
位置検出マークは、シリコン基板上のICチップの工程に
従って、必要なそれぞれのプロセスの影響を受けるが、
一度位置検出マークとして、電子ビームの露光を受けた
マークは、その後のエッチング工程で、段差部の形状に
変化を受けることが多く、次の電子ビーム露光時の位置
検出マークとしては使用出来ない場合が多い。The position detection mark is affected by each required process according to the process of the IC chip on the silicon substrate,
When a mark that has been exposed to an electron beam as a position detection mark is often changed in the shape of the step in the subsequent etching process, it cannot be used as a position detection mark for the next electron beam exposure. There are many.
従って一般的には複数個の位置マークを、一つのグルー
プとして形成しておいて、次のプロセスの位置検出時に
は、グループ内の次の未使用位置検出マークを用いる方
法が採られている。Therefore, generally, a method is adopted in which a plurality of position marks are formed as one group and the next unused position detection mark in the group is used when the position is detected in the next process.
以上の説明で明らかな如く、半導体集積回路は、基本的
プロセスを繰り返すことによって完成されるが、今、チ
ップの各機能素子部分のプロセスが終わり、Al配線工程
まで進行したときを考えると、チップ部および位置検出
マーク部の断面図は、それぞれ第６図（ａ）および
（ｂ）のような構造となっている。As is clear from the above description, the semiconductor integrated circuit is completed by repeating the basic process. Now, when the process of each functional element part of the chip is completed and the process proceeds to the Al wiring process, the chip is The sectional views of the portion and the position detection mark portion have structures as shown in FIGS. 6 (a) and 6 (b), respectively.
ここで位置検出マーク部のAl被膜７を、Al配線層形成工
程でのエッチング時、除去しない理由は、マーク部のシ
リコン基板を保護するためである。即ちAlのドライエッ
チングに用いられるClを含んだ反応ガスは、マーク部で
Alのみならずシリコン基板にも反応して蝕刻作用を及ぼ
す。Here, the reason why the Al film 7 of the position detection mark portion is not removed during etching in the Al wiring layer forming step is to protect the silicon substrate of the mark portion. That is, the reaction gas containing Cl used for dry etching of Al is
Not only Al but also silicon substrate reacts to exert an etching action.
従って、このようなエッチングされた、シリコン面をも
った位置検出マークは、精度の高い位置検出には利用出
来ない。Al被膜でカバーされたマークは、位置検出マー
クとして充分使用可能であるが、次のPSG形成段階で、A
l被膜の突起の問題が避けられない。Therefore, such an etched position detection mark having a silicon surface cannot be used for highly accurate position detection. The mark covered with the Al film can be sufficiently used as a position detection mark, but in the next PSG formation step,
l The problem of protrusion of the coating is unavoidable.
半導体集積回路は集積度の向上に伴って、Al配線も益々
微細化し、更に二層配線構造をとることも多くなってき
ている。As the degree of integration of semiconductor integrated circuits is improved, Al wirings are becoming finer and more and more often, a two-layer wiring structure is adopted.
第６図で示された、一層目のAl配線７（Al−Ｉ）の上
に、二層目のAl配線（Al−II）を形成するための、絶縁
用PSG（Phospho Silicate Glass）膜８をCVD（Chemical
Vapor Deposition）法で成長させるが、このプロセス
は400℃に近い温度上昇を伴うので、PSG膜成長後の位置
検出マークの断面は、第６図のごとく、アルミ被膜上に
突起９が発生するという問題を生じる。An insulating PSG (Phospho Silicate Glass) film 8 for forming a second-layer Al wiring (Al-II) on the first-layer Al wiring 7 (Al-I) shown in FIG. CVD (Chemical
Vapor Deposition) method is used, but since this process involves a temperature rise close to 400 ° C, the cross section of the position detection mark after PSG film growth has protrusions 9 on the aluminum film as shown in Fig. 6. Cause problems.
このアルミ被膜の突起は、PSGのスルーホール形成、次
いで、二層目Al配線（Al−II）のパターンニング等の、
次段以降の工程での電子ビーム露光時、位置検出信号に
雑音となって表れ、位置精度の低下、位置合わせ不能の
状態が発生する。またチップ部での突起９は配線間耐圧
不良の原因ともなる。The protrusions of this aluminum coating are used for PSG through hole formation, then patterning of the second layer Al wiring (Al-II), etc.
At the time of electron beam exposure in the subsequent steps, the position detection signal appears as noise, which deteriorates the position accuracy and causes a state in which alignment is impossible. In addition, the protrusions 9 on the chip portion also cause a breakdown voltage failure between wirings.
上記に述べた、位置検出マークでのAl被膜の突起は、ス
ルーホール形成、二層目Al配線等の次段以降のパターン
ニング用としては致命的欠陥となる。またチップ側配線
部では、二層配線間の耐圧不良の原因ともなる。The above-described protrusion of the Al film on the position detection mark becomes a fatal defect for patterning the through hole formation, the second layer Al wiring and the like in the next stage and thereafter. Further, in the chip side wiring portion, it may cause a breakdown voltage between the two layers of wiring.
本発明では、Al配線層、およびPSG膜を成長させた後、P
SG膜の平坦化プロセスを行い、更にフオトリソグラフイ
法により、位置検出マーク部でのPSG膜をエッチング除
去、更に、Al被膜のエッチング除去を行う。In the present invention, after the Al wiring layer and the PSG film are grown, P
The SG film is flattened, and then the PSG film at the position detection mark portion is removed by etching by the photolithography method, and further the Al film is removed by etching.
しかるのち、次の工程で直ちに使用する位置検出マーク
を除いて、未使用位置検出マークをフオトレジスト膜に
て保護した後、次のスルーホールの形成、二層目アルミ
配線プロセスと移る方法を提案するものである。After that, after removing the position detection marks used immediately in the next process, protecting the unused position detection marks with a photoresist film, we propose a method of forming the next through hole and moving to the second layer aluminum wiring process. To do.
上記に述べた手段により、Al−Ｉの工程とは分離してマ
ーク部PSG層、およびAl被膜の除去を行うことにより、
スルーホールの形成、Al−II等プロセスにおいて、電子
ビーム露光パターンニング時の、位置合わせは、シヤー
プな二酸化シリコン膜のエッジよりの反射電子を利用す
ることが可能となり、またAl被膜の突起による、粉らわ
しき雑音も無くなるので、マーク検出不能をなくすこと
が可能となった。By the means described above, the mark part PSG layer and the Al coating film are removed separately from the Al-I step,
In the process of forming a through hole, Al-II, etc., alignment during electron beam exposure patterning can use reflected electrons from the edge of the sharp silicon dioxide film, and due to the protrusion of the Al film, Since there is no dusty noise, it is possible to eliminate mark detection failure.
更にPSG膜の平坦化プロセスにより、Al配線間のPSG絶縁
膜厚の精度をあげる効果があり、耐圧不良を防止するこ
とが出来る。Further, the flattening process of the PSG film has the effect of increasing the accuracy of the PSG insulating film thickness between Al wirings, and can prevent breakdown voltage failure.
以下、本発明による一実施例を図面により説明する。一
層目のAl配線（Al−Ｉ）、および最初のPSG膜の成長工
程までは、従来の技術と同様である。従ってここまでの
工程での完成品は第６図と同様である。簡単のためマー
ク部について図示する。An embodiment according to the present invention will be described below with reference to the drawings. The process up to the first-layer Al wiring (Al-I) and the first PSG film growth process is the same as the conventional technique. Therefore, the finished product through the steps up to here is the same as that shown in FIG. For simplicity, the mark portion is shown in the figure.
次いで第１図（ａ）のごとく、基板全面にわたって、ド
ライブプロセスによりPSG膜の平坦化エッチングを、Al
被膜上のPSG膜がほぼ無くなるまで行う。次いで基板全
面にわたって、PSG膜を再度成長させる。このときの膜
厚は配線間の耐圧をもたせるのに充分な0.7μｍ程度の
成長をおこなって第１図（ｂ）を得る。Then, as shown in FIG. 1 (a), the PSG film is planarized and etched over the entire surface of the substrate by a drive process.
Repeat until the PSG film on the film is almost gone. Then, the PSG film is grown again over the entire surface of the substrate. The film thickness at this time is about 0.7 .mu.m, which is sufficient to provide a withstand voltage between the wirings, and the film shown in FIG. 1B is obtained.
次いでフオトレジスト10を全面に塗布して、位置検出マ
ーク部のパターンニングを行い、エッチング処理により
PSG膜８、ついでAl被膜７のエッチング除去を行って、
それぞれ第１図（ｃ）、ついで（ｄ）のごとく二酸化シ
リコン膜のエッジの露出した位置検出マーク部の構造を
得る。Next, the photoresist 10 is applied to the entire surface, patterning of the position detection mark portion is performed, and etching is performed.
The PSG film 8 and then the Al film 7 are removed by etching,
As shown in FIG. 1 (c) and then in FIG. 1 (d), the structure of the position detection mark portion where the edge of the silicon dioxide film is exposed is obtained.
次いで、基板全面にわたって、レジスト除去プロセスを
行い、更に、利用する位置検出マークを除いた、未使用
位置検出マーク部での段差部の形状の変化を防止するた
め、フオトレジスト11にてマーク部を保護する。以上の
工程を経ることにより、位置検出マーク部の断面構造は
第１図（ｅ）ごとくなり、またその時のチップ部の断面
構造として、第１図（ｆ）を得る。Next, a resist removal process is performed over the entire surface of the substrate, and in order to prevent a change in the shape of the stepped portion in the unused position detection mark portion except the position detection mark to be used, the mark portion is formed with the photoresist 11. Protect. Through the above steps, the sectional structure of the position detection mark portion becomes as shown in FIG. 1 (e), and FIG. 1 (f) is obtained as the sectional structure of the chip portion at that time.
以上の位置検出マーク部の処理工程を経て、次のPSG層
に対するスルーホールの形成工程に移るが、この時の位
置検出は先の工程でフオトレジスト塗布を実施しなかっ
たマークを利用して行う。更に二層目のAl配線層のパタ
ーンニングは、未使用の位置検出マークの保護レジスト
を除去して位置検出を行う。After the processing steps of the position detection mark portion described above, the process proceeds to the through hole forming step for the next PSG layer, but the position detection at this time is performed by using the mark that has not been subjected to photoresist coating in the previous step. . Further, in the patterning of the second Al wiring layer, the position detection is performed by removing the protective resist of the unused position detection mark.
以上に説明せる方法を適用することにより、スルーホー
ルの形成、Al−II等の後続のプロセスにおける位置合わ
せ不能はなくなると共に、位置合わせの精度が向上し、
アルミ配線部でのフイールドでの事故も、著しく低減す
ることが可能となった。By applying the method explained above, formation of through holes, alignment failure in subsequent processes such as Al-II, etc. is eliminated, and alignment accuracy is improved,
It is also possible to significantly reduce the number of accidents in the field of the aluminum wiring.
第１図（ａ）〜（ｅ）にて、本発明にかかわる実施例で
の、位置検出マーク部の工程順断面図、第１図（ｆ）は
同じくスルーホール形成前のチップ部での断面図、 第２図は電子ビーム露光装置の構造図、 第３図は位置検出マークの平面図、および断面図、 第４図、第５図は位置検出信号、 第６図は従来の方法による、スルーホール形成、Al−II
工程に移る前の構造断面図、を示す。 図面において、 １は電子ビーム、 ２はシリコン基板、 ３は信号検知器、 ４は電子計算機、 ５はシリコン基板、 ６は二酸化シリコン膜、 ７はアルミニウム膜、 ８はPSG膜、 ９はアルミニウム被膜突起部、 10,11はレジスト被膜 をそれぞれ示す。FIGS. 1A to 1E are cross-sectional views in order of steps of the position detection mark portion in the embodiment according to the present invention, and FIG. 1F is a cross-sectional view of the chip portion before formation of the through hole. Fig. 2 is a structural view of an electron beam exposure apparatus, Fig. 3 is a plan view of a position detection mark, and a sectional view, Figs. 4 and 5 are position detection signals, and Fig. 6 is a conventional method. Through hole formation, Al-II
The structural sectional view before moving to a process is shown. In the drawings, 1 is an electron beam, 2 is a silicon substrate, 3 is a signal detector, 4 is a computer, 5 is a silicon substrate, 6 is a silicon dioxide film, 7 is an aluminum film, 8 is a PSG film, and 9 is an aluminum film protrusion. Parts 10 and 11 are resist coatings, respectively.
Claims (1)
形成し、その後の電子ビーム露光時には、このマークを
逐次使用して位置検出を行う、電子ビーム露光法を用い
る半導体装置の製造において、アルミニウム配線層と、
その上の層間絶縁膜を形成した後、マーク上に積層した
該層間絶縁膜とアルミニウム被膜を除去する工程と、次
の工程で位置検出に利用するマークを除いて、他の未使
用マークを電子ビームに対し非感光性レジストによっ
て、保護する工程を加えたことを特徴とする半導体装置
の製造方法。1. A method of manufacturing a semiconductor device using an electron beam exposure method, wherein a plurality of marks having steps are formed for position detection, and the subsequent electron beam exposure is used to detect the position. An aluminum wiring layer,
After forming an interlayer insulating film on the mark, a step of removing the interlayer insulating film and the aluminum film laminated on the mark, and other unused marks except for the mark used for position detection in the next step. A method of manufacturing a semiconductor device, comprising a step of protecting the beam with a non-photosensitive resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010416A JPH0782978B2 (en) | 1985-01-22 | 1985-01-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60010416A JPH0782978B2 (en) | 1985-01-22 | 1985-01-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61168916A JPS61168916A (en) | 1986-07-30 |
| JPH0782978B2 true JPH0782978B2 (en) | 1995-09-06 |
Family
ID=11749540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60010416A Expired - Fee Related JPH0782978B2 (en) | 1985-01-22 | 1985-01-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0782978B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5627929A (en) * | 1979-08-14 | 1981-03-18 | Fujitsu Ltd | Electron beam projection |
| JPS5989414A (en) * | 1982-11-15 | 1984-05-23 | Mitsubishi Electric Corp | Alignment of semiconductor substrate |
-
1985
- 1985-01-22 JP JP60010416A patent/JPH0782978B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61168916A (en) | 1986-07-30 |
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