JPS6227155B2 - - Google Patents

Info

Publication number
JPS6227155B2
JPS6227155B2 JP54109125A JP10912579A JPS6227155B2 JP S6227155 B2 JPS6227155 B2 JP S6227155B2 JP 54109125 A JP54109125 A JP 54109125A JP 10912579 A JP10912579 A JP 10912579A JP S6227155 B2 JPS6227155 B2 JP S6227155B2
Authority
JP
Japan
Prior art keywords
wiring
film
photoresist
dry etching
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54109125A
Other languages
Japanese (ja)
Other versions
JPS5635774A (en
Inventor
Katsumi Ogiue
Yoshinori Kureishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP10912579A priority Critical patent/JPS5635774A/en
Publication of JPS5635774A publication Critical patent/JPS5635774A/en
Publication of JPS6227155B2 publication Critical patent/JPS6227155B2/ja
Granted legal-status Critical Current

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  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 この発明はドライエツチング技術に関し、主と
してプラズマエツチによるA配線加工を対象と
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to dry etching technology, and is primarily directed to A wiring processing using plasma etching.

LSI,IC等の半導体装置の高集積化に伴ない、
プラズマ放電を利用したドライエツチング技術が
配線の微細加工の主要な手段となりつつある。ド
ライエツチは一般にホトレジスト(感光性耐食
材)で形成したマスクを通して行なう。被エツチ
ング材がA(アルミニウム)の場合、ホトレジ
ストAのエツチング速度比(エツチング選択比
とも呼ぶ)は1:2〜3倍である。微細加工を行
なうためには、ホトレジストの膜厚を薄くする必
要があり、被エツチング材が例えば、LSIの内線
配線を行うためのAlである場合Al配線膜も薄く
しなければならない。しかし、配線材料は許容電
流密度及び配線抵抗の限界からある厚さ以上は薄
くできない。又LSIにおいては第1図に示すよう
に基板表面に例えばフイールド絶縁部として酸化
膜等を形成するためにできた凹凸2があり、その
段差部上に第1のAl配線3、層間絶縁膜4、第
2のAl配線5等を積層してホトレジスト6によ
り第2のAl配線の一部をエツチしようとする場
合、上記段差部で被エツチング材(第2のAl配
線)が薄くなり、またホトレジストの膜厚が薄く
なつて同図Aに示すようにエツチングが深部に進
行し、この部分で断線するという事態を生じるこ
とがある。また、この対策として、ホトレジスト
のの粘度をあげ、ホトレジストの膜厚を厚くした
場合、上記段差部での膜厚が厚くなり、段差部で
の配線シヨートを引き起すおそれもある。
With the increasing integration of semiconductor devices such as LSI and IC,
Dry etching technology using plasma discharge is becoming a major means for microfabrication of interconnects. Dry etching is generally performed through a mask made of photoresist (a photosensitive material resistor). When the material to be etched is A (aluminum), the etching rate ratio (also called etching selection ratio) of photoresist A is 1:2 to 3 times. In order to perform microfabrication, it is necessary to reduce the thickness of the photoresist film, and if the material to be etched is, for example, Al for internal wiring of an LSI, the Al wiring film must also be made thin. However, the wiring material cannot be made thinner than a certain thickness due to limits in allowable current density and wiring resistance. In addition, in LSI, as shown in FIG. 1, there are irregularities 2 on the substrate surface, which are formed to form, for example, an oxide film as a field insulating part, and on the stepped part, a first Al wiring 3 and an interlayer insulating film 4 are formed. When trying to etch a part of the second Al wiring with the photoresist 6 after laminating the second Al wiring 5, etc., the material to be etched (the second Al wiring) becomes thinner at the step part, and the photoresist As the film thickness becomes thinner, etching progresses to a deeper part as shown in FIG. Furthermore, if the viscosity of the photoresist is increased and the film thickness of the photoresist is made thicker as a countermeasure against this problem, the film thickness at the step portion becomes thicker, and there is a possibility that wiring shorts may occur at the step portion.

本発明は上記した問題点を解決するためになさ
れたものであり、その一つの目的はドライエツチ
ングによる微細加工であり、他の目的は薄いホト
マスクによる微細Al配線加工の実現にある。
The present invention has been made to solve the above-mentioned problems, and one purpose thereof is to perform fine processing using dry etching, and another purpose is to realize fine Al wiring processing using a thin photomask.

上記目的を達成するために、本発明のアルミニ
ウムのドライエツチング法によれば、アルミニウ
ム層の表面にシリコン窒化膜を形成し、このシリ
コン窒化膜にその上に形成した感光耐食材マスク
を通してエツチンングにより開孔し、しかる後、
上記感光耐食材マスクと上記シリコン窒化膜をマ
スクとして、上記アルミニウムのドライエツチを
行なうことを特徴とする。
In order to achieve the above object, according to the aluminum dry etching method of the present invention, a silicon nitride film is formed on the surface of an aluminum layer, and the silicon nitride film is opened by etching through a photosensitive material mask formed thereon. After drilling and scolding,
The method is characterized in that the aluminum is dry-etched using the photosensitive food-resistant mask and the silicon nitride film as masks.

第2図a〜cは本発明をAl配線のドライエツ
チに適用した場合の実施例の趣要プロセスを示
す。
FIGS. 2a to 2c show the essential processes of an embodiment in which the present invention is applied to dry etching of Al wiring.

(a) 同図において、1はSi基板、2は段差部、3
は第1層Al配線、4は層間絶縁膜、例えば
CVD(気相化学反応堆積)によるPSG(リ
ン・シリケート・ガラス)膜、5は被エツチ材
となる第2層Al配線である。この第2層Al配
線5の表面にプラズマSi3N4膜7を膜厚1500Å
程度に形成し、その上にホトレジストを塗布し
て周知の露光現象処理によりホトマスク6を形
成する。
(a) In the same figure, 1 is the Si substrate, 2 is the stepped part, and 3 is the Si substrate.
is the first layer Al wiring, 4 is the interlayer insulating film, e.g.
A PSG (phosphorus silicate glass) film is formed by CVD (vapor phase chemical reaction deposition), and 5 is the second layer Al wiring which is the material to be etched. A plasma Si 3 N 4 film 7 with a thickness of 1500 Å is deposited on the surface of this second layer Al wiring 5.
A photomask 6 is formed by applying a photoresist thereon and performing a well-known exposure process.

(b) 上記ホトマスクをマスクとしてSi3N4膜7を
エツチ(ドライエツチ又はウエツトエツチ)し
開孔する (c) 上記ホトマスク及び開孔したホトマスクをマ
スクとしてAl膜5をドライエツチして所要の
Al配線のパターンを得る。この後、ホトマス
クを溶解除去し、Si3N4膜は表面保護膜として
残存させてよい。
(b) Using the above photomask as a mask, the Si 3 N 4 film 7 is etched (dry etching or wet etching) to open a hole. (c) Using the above photomask and the opened photomask as a mask, the Al film 5 is dry etched to form the required size.
Obtain the Al wiring pattern. Thereafter, the photomask may be dissolved and removed, leaving the Si 3 N 4 film as a surface protective film.

上記実施例で述べた構成によれば下記理由で前
記目的が達成できる。
According to the configuration described in the above embodiment, the above object can be achieved for the following reasons.

Si3N4とAlとの選択比は1:7〜10程度であ
り、又Si3N4とホトレジストの選択比は1:3〜
5程度である。したがつて薄いホトレジ膜をマス
クとして薄いSi3N4膜をドライエツチングにより
開孔し、しかるのちに、ホトレジストとSi3N4
をマスクとして、Alをドライエツチングするこ
とにより、従来法に比してホトレジストの厚さを
1/2程度にせしめることが可能となり、微細パタ
ーンの加工が容易となつた。例えば従来、膜厚2
μmのホトレジストを使用し、Al配線の膜厚2.5
μm、Al配線の幅9μm、配線間隔(エツチ
幅)4μm程度が限界であつたが、本発明方法に
よれば7000Åのホトレジストを使用し、Al配線
の膜厚2.5μm、Al配線幅6μm、配線間隔2μ
m程度の微細加工が容易にできるようになつた。
The selectivity ratio between Si 3 N 4 and Al is about 1:7 to 10, and the selectivity ratio between Si 3 N 4 and photoresist is about 1:3 to 1:3.
It is about 5. Therefore, by dry etching the thin Si 3 N 4 film using the thin photoresist film as a mask, and then dry etching the Al using the photoresist and the Si 3 N 4 film as a mask, the etching process was improved compared to the conventional method. and the thickness of the photoresist
It became possible to reduce the size to about 1/2, making it easier to process fine patterns. For example, conventionally, film thickness 2
Using µm photoresist, the film thickness of Al wiring is 2.5
However, according to the method of the present invention, a 7000 Å photoresist is used, the Al wiring thickness is 2.5 μm, the Al wiring width is 6 μm, and the wiring width is 6 μm. Spacing 2μ
Microfabrication of the order of m in size has become possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のドライエツチの形態を示す半導
体装置の断面図、第2図a〜cは本発明によるド
ライエツチのプロセスの各工程を示す半導体装置
の各断面図である。 1……Si基板、2……段差部(酸化膜)、3…
…第1層Al配線、4……層間絶縁膜、5……第
2層Al配線、6……ホトレジストマスク、7…
…Si3N4膜。
FIG. 1 is a sectional view of a semiconductor device showing a conventional dry etch process, and FIGS. 2A to 2C are sectional views of a semiconductor device showing each step of the dry etch process according to the present invention. 1... Si substrate, 2... Step portion (oxide film), 3...
...First layer Al wiring, 4... Interlayer insulating film, 5... Second layer Al wiring, 6... Photoresist mask, 7...
... Si3N4 film .

Claims (1)

【特許請求の範囲】 1 アルミニウム層の表面にシリコン窒化膜を形
成し、このシリコン窒化膜にその上に形成した感
光耐食材マスクを通してエツチングにより開孔
し、しかる後、上記感光耐食材マスクと上記シリ
コン窒化膜をマスクとして、上記アルミニウムの
ドライエツチを行なうことを特徴とするアルミニ
ウムのドライエツチ法。 2 前記シリコン窒化膜はドライエツチの後でア
ルミニウムの表面保護膜として残しておくことを
特徴とする特許請求の範囲第1項記載のアルミニ
ウムのドライエツチ法。
[Scope of Claims] 1. A silicon nitride film is formed on the surface of the aluminum layer, a hole is formed in the silicon nitride film by etching through a photosensitive material-resistant mask formed thereon, and then the photosensitive material-resistant mask and the above-mentioned A dry etching method for aluminum, characterized in that the dry etching of aluminum is performed using a silicon nitride film as a mask. 2. The method of dry etching aluminum according to claim 1, wherein the silicon nitride film is left as a surface protection film for aluminum after dry etching.
JP10912579A 1979-08-29 1979-08-29 Dry etching method Granted JPS5635774A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10912579A JPS5635774A (en) 1979-08-29 1979-08-29 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10912579A JPS5635774A (en) 1979-08-29 1979-08-29 Dry etching method

Publications (2)

Publication Number Publication Date
JPS5635774A JPS5635774A (en) 1981-04-08
JPS6227155B2 true JPS6227155B2 (en) 1987-06-12

Family

ID=14502188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10912579A Granted JPS5635774A (en) 1979-08-29 1979-08-29 Dry etching method

Country Status (1)

Country Link
JP (1) JPS5635774A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522899A (en) * 1991-07-10 1993-01-29 Akiko Uchiumi Generation of electricity by means of rotation of wheels of automobile

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432143A (en) * 1977-08-17 1979-03-09 Hitachi Ltd Etching process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432143A (en) * 1977-08-17 1979-03-09 Hitachi Ltd Etching process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522899A (en) * 1991-07-10 1993-01-29 Akiko Uchiumi Generation of electricity by means of rotation of wheels of automobile

Also Published As

Publication number Publication date
JPS5635774A (en) 1981-04-08

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