JPS5933833A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor wafer from generation of a reaction with plasma gas by a method wherein a second insulating film of upper layer is patterned according to plasma etching using a first insulating film as the etching obstructing film, and the first insulating film is etched using the pattern of the second insulating film as the mask. CONSTITUTION:The first insulating film 20 of 5,000-10,000Angstrom film thickness consisting of a silicon oxide film is adhered, and moreover the S-I-N film 16 is adhered thereon at 5,000-10,000Angstrom film thickness as the second insulating film. Then, the S-I-N film 16 of the second insulating film is etched by plasma according to CF4/O2/N2 mixed gas to remove the S-I-N film 16 on a dicing line 13 and to open a through hole 17. At this time, the first insulating film 20 acts as the etching obstructing film against plasma etching, and a silicon substrate 11 under the dicing line 13 is prevented from exposure even when etching is performed having sufficient scope. After then, the wafer thereof is immersed in an etching liquid of fluoric acid, and using the S-I-N film 16 as the mask, the exposed part of the first insulating film 20 is etched to be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device that is subjected to turning by plasma etching.

[Technical background of the invention]

Conventionally, phosphorus-doped silicon oxide films (PSG films) have been used as surface protection films for semiconductor devices or as interlayer films for multilayer wiring, but PSG films cannot provide sufficient moisture resistance and device stability. Therefore, recently, a silicon nitride film (SIN film) has been used instead of the PSG film.

The manufacturing process of a semiconductor device using such an 81N film as an interlayer film of multilayer wiring is as shown in FIGS. 1(a) to 1(c). Reference numeral 11 is a silicon substrate on which predetermined regions are formed through a diffusion process, etc., and 12 is an insulating layer, such as a field silicon oxide film, formed on this substrate 11. Further, the region shown in the figure to which the insulating layer 12 is not applied becomes the dicing line 13 of this semiconductor wafer, and is the location where the wafer is cut by a dicing machine after the insulating film formation on the wafer and the wiring process are completed.

Furthermore, the other opening is a contact hole 14,
The first electrode layer 15 is connected to the semiconductor substrate 11 through this contact hole 14 .

First, on the upper surface of such a semiconductor wafer, a SIN film 16, which is to become an interlayer film of the multilayer wiring described above, is deposited.

Next, as shown in FIG. 1(b), a through hole 17 opening to the first electrode layer 15 is formed in the S+N film 16 by photolithography using plasma etching, and
The dicing line 13 is also opened.

After that, the first electrode layer 15 is inserted through the through hole 17.
A second pole layer 18 is deposited and the wafer is cut into semiconductor chips along dicing lines 13, for example by blade dicing.

[Problems with background technology]

The plasma etching of the SIN film 16 described above is performed using CF4 (
Etching is carried out in a gas plasma containing a mixed gas (fluorocarbon) 102 (oxygen). At this time, etching of the SiN film 16 progresses, and when the SIN film 16 covering the dicing line 13 is removed and the silicon substrate 11 is exposed. , the silicon (sB) of this substrate 11 and the above mixed gas react, and the composition of the plasma gas changes slightly, causing a change in the plasma gas reaction.For this reason, from the time the substrate 11 is exposed, the dicing lines 13 and Etching of the SIN film 16, such as the through holes 17, proceeds rapidly.

Here, the etching accuracy of the dicing line 13 is not required so much, but the through hole 17 connecting the first electrode layer 15 and the second electrode layer 1g is located at the position shown in the plan view example of FIG. The alignment and the opening area of the through hole 17 are important, as shown at 17' in FIG. 2(b).
When excessive overetching progresses, the margin for mask alignment becomes very small, resulting in a decrease in yield and reliability.

In order to prevent the silicon from reacting with the plasma gas, it is possible to open only the through holes 17 by plasma etching while leaving the insulating layer 16 on the dicing line unetched. However, it is necessary to remove the insulating layer 16 by photolithography, which is a complicated process.

[Purpose of the invention]

This invention was made in view of the above points, and it is possible to prevent plasma gas from reacting with parts exposed by plasma etching through a simple process without adding a photoetching process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables plasma etching of an insulating film with high precision and contributes to the yield and reliability of semiconductor products.

5- [Summary of the Invention] That is, in the semiconductor device according to the present invention, a first insulating film and a second insulating film are laminated and deposited in order from the bottom layer on a semiconductor wafer in which each predetermined region is formed, and Using the insulating film as a plasma etching stopper film for the semiconductor wafer, the second insulating film M in the upper layer is patterned by plasma etching, and then the first insulating film L in the lower layer is etched using the pattern of the second insulating film as a mask. The second insulating film is manufactured by including a semiconductor wafer and plasma gas is manufactured to prevent a reaction between the semiconductor wafer and the plasma gas during plasma etching of the second insulating film.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 3(a) to 3(f) are diagrams showing cross sections of seven recon wafers in the order of the manufacturing process, and the same components as in FIG. 1 are given the same reference numerals, and some explanations are omitted. Figure 3 (,) shows the first
A wafer similar to that shown in Figure (a) has an insulating layer 12 made of silicon oxide on a silicon substrate 11, and a contact hole 1.
A first electrode layer 15 is formed which is connected to the substrate 11 through 4 and 6, and the semiconductor substrate 11 is exposed above the dicing line 13.

As shown in FIG. 3(b), a first insulating film 20f of 500 to 20,000, for example, made of a silicon oxide film is deposited on the entire surface of the wafer, and a second insulating film 20f is deposited thereon as shown in FIG. 3(c). As shown in the figure, the SiN film 16 is
Deposit with a film thickness of oooi.

Next, as shown in FIG. 3(d), CF4102/N2
The SJN film 16 as the second insulating film is plasma etched using a mixed gas to form the SIN film 1 on the dicing line 13.
6 and the through hole 17 is opened. Here, the plasma etching rate ratio of the silicon oxide film and the Six film using the above mixed gas is about 5 to 15 times, so the SI
The first insulating film 20 under the N film 16 serves as an etching stopper film for this plasma etching, and even if etching is performed with sufficient margin, exposure of the silicon substrate 11 below the dicing line 13 is prevented.

After this, the wafer is immersed in hydrofluoric acid etching.
As shown in FIG. 3(e), the exposed portion of the first insulating film 20 is removed by etching using the SIN film 16 as a mask.

After this, as shown in FIG. 3(f), a second electrode layer 18 connected to the first electrode layer 15 is formed through the through hole 17 reaching the first electrode layer 15, and a dicing line (not shown) is formed. The wafer is cut along lines 13 into semiconductor chips.

As described above, in the etching of the Six film according to this embodiment, the lower first insulating film 20 acts as an etching stopper film, and prevents the silicon substrate 1 from being exposed on the dicing line 13. Therefore, abnormal overetching of the S+N film 16 due to the reaction between silicon and plasma gas can be prevented. FIG. 4 is a graph showing the relationship between etching time and etching amount when a Six film is plasma etched, where A shows the case where the silicon substrate is exposed and B shows the case where etching was performed using the method according to this example. . As is clear from this figure, when the silicon substrate is covered with the first insulating layer, etching progresses slowly and the amount of etching can be controlled with high accuracy.

Although this embodiment has been described with reference to the case where the SIN film 16 is formed as an interlayer film between electrode layers, the present invention is applicable not only to cases where the silicon substrate at the dicing line portion may be exposed, but also to the polysilicon layer 16. It can be applied to various cases such as forming a Six film pattern on a silicon substrate, etc., or forming a Six film pattern on a silicon substrate.
The first insulating film, which serves as a plasma etching stopper film, is not limited to silicon oxide, but may be made of a metal oxide such as alumina.

Further, the second insulating film is not limited to the Six film, but may be combined with the first insulating film so that the first insulating film can be etched by using the second insulating film as a mask because it reacts with the etching gas. Other materials can also be used.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent the reaction between the part exposed by plasma etching and the plasma gas through a simple process without performing an additional photoetching process, and the plasma etching of the insulating film can be prevented. It is possible to provide a method for manufacturing a semiconductor device that can be performed with high precision and improves the yield and reliability of semiconductor products.

[Brief explanation of the drawing]

Figures 1 (,) to (c) are diagrams showing the manufacturing process of a conventional semiconductor device, Figure 2 (6) to (b) are diagrams explaining the etching of through holes in multilayer wiring, and Figures 3 (a) to (f) is a diagram showing the manufacturing process of a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a graph showing the etching speed of etching according to the conventional method and etching according to the present invention. 1. Silicon substrate, 13. Dicing line, J 6-8iN film, 17-7', #-hole, 2°.
...First insulating film. Applicant's agent Patent attorney Takehiko Suzue 10-

Claims (3)

[Claims] (1) Made of a material that can act as an etching stopper film in the plasma etching of the second insulating film that is performed later on the semiconductor wafer on which each predetermined region has been formed, and that can be etched using the second insulating film as a mask. A step of depositing a first insulating film, a step of depositing a second insulating film on the first insulating film, and a step of depositing a second insulating film by plasma etching the second insulating film.
A method of manufacturing a semiconductor device, comprising the steps of forming an insulating film pattern and etching the first insulating film using the second insulating film pattern as a mask. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is mainly composed of silicon oxide or alumina, and the second insulating film is silicon nitride. (3) Claim 1 or 2, wherein the first and second insulating films are interlayer films of multilayer wiring.
Method for manufacturing a semiconductor device described in Section 0