JPH01130546A - Electrode wiring forming method - Google Patents
Electrode wiring forming methodInfo
- Publication number
- JPH01130546A JPH01130546A JP29134687A JP29134687A JPH01130546A JP H01130546 A JPH01130546 A JP H01130546A JP 29134687 A JP29134687 A JP 29134687A JP 29134687 A JP29134687 A JP 29134687A JP H01130546 A JPH01130546 A JP H01130546A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode wiring
- lower electrode
- film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims description 15
- 230000010354 integration Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は電極配線の形成方法に関するものであり、特
に、大規模集積回路装置における電極配線の形成方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming electrode wiring, and particularly to a method of forming electrode wiring in a large-scale integrated circuit device.
［従来の技術］
第２Ａ図、第２Ｂ図、第２Ｃ図および第２Ｄ図は、従来
の、電極配線パターンの形成方法の主要製造工程を示し
たものである。以下、これらの図を用いて、従来の電極
配線パターンの形成方法について説明する。[Prior Art] FIGS. 2A, 2B, 2C, and 2D show the main manufacturing steps of a conventional method for forming an electrode wiring pattern. Hereinafter, a conventional method for forming an electrode wiring pattern will be described using these figures.
シリコン基板１の主面全体に絶縁膜たとえばシリコン酸
化膜２を熱酸化、ＣＶＤ法等により形成する。そしてそ
の上に、下層電極配線膜（たとえばポリシリコン）をＣ
ＶＤ法、スパッタ法等により形成する。そして、さらに
、写真製版、エツチング法により、所定の下層電極配線
パターン３を形成する（以上第２Ａ図）。An insulating film, such as a silicon oxide film 2, is formed over the entire main surface of a silicon substrate 1 by thermal oxidation, CVD, or the like. Then, on top of that, a lower electrode wiring film (for example, polysilicon) is
It is formed by a VD method, a sputtering method, or the like. Further, a predetermined lower layer electrode wiring pattern 3 is formed by photolithography and etching (see FIG. 2A).
次に、上記下層配線電極パターン３を含む半導体基板１
の表面全体に絶縁膜７（たとえばリンガラス）をＣＶＤ
法、スパッタ法により形成する（第２Ｂ図）。Next, the semiconductor substrate 1 including the lower layer wiring electrode pattern 3 is
An insulating film 7 (for example, phosphor glass) is deposited on the entire surface of the
(FIG. 2B).
そして、写真製版とエツチング法を用いて、下地基板１
との電気的接触を必要とするところの絶縁膜７を除去し
、コンタクトホール、と呼ばれる孔１０を設ける（第２
Ｃ図）。Then, using photolithography and etching, the base substrate 1 is
The insulating film 7 that requires electrical contact with the
Figure C).
次に、上記コンタクトホール１０を含む半導体基板１の
表面全体に上層電極配線膜６を形成し、写真製版とエツ
チング法を用いて、所定のパターンを得る（第２Ｄ図）
。Next, an upper electrode wiring film 6 is formed on the entire surface of the semiconductor substrate 1 including the contact hole 10, and a predetermined pattern is obtained using photolithography and etching (FIG. 2D).
.
［発明が解決しようとする問題点］
従来の電極配線パターンの形成方法は以上のように構成
されている。したがって、隣接する下層電極配線パター
ン３．３間に、写真製版によって、コンタクトホールを
形成するため、写真製版工程において、非常に微細なパ
ターンを形成する必要があり、マスクの位置合わせに高
い精度が要求されていた。また、位置合わせ誤差により
、下層配線と上層配線が短絡するため、それを未然に防
止するため、下層配線の間隔をある程度広くしなければ
ならなかった。このことは、半導体装置の集積度を上げ
る際に大きな問題点となっていた。[Problems to be Solved by the Invention] The conventional method for forming an electrode wiring pattern is configured as described above. Therefore, in order to form a contact hole by photolithography between adjacent lower electrode wiring patterns 3.3, it is necessary to form a very fine pattern in the photolithography process, which requires high accuracy in mask alignment. It was requested. Furthermore, alignment errors cause short circuits between the lower layer wiring and the upper layer wiring, so in order to prevent this from occurring, it is necessary to increase the interval between the lower layer wiring to some extent. This has been a major problem when increasing the degree of integration of semiconductor devices.
この発明は、上記のような問題点を解決するためになさ
れたもので、半導体装置の集積度を容易に上げることの
できる、電極配線の形成方法を提供することを目的とす
る。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming electrode wiring that can easily increase the degree of integration of a semiconductor device.
［問題点を解決するための手段］
この発明に係る電極配線の形成方法は、半導体基板表面
全体に下層電極配線膜を形成し、さらにその上全体に第
１の絶縁膜を形成し、
その後、上記下層電極配線膜と上記第１の絶縁膜をエツ
チングし、上記第１の絶縁膜の部分がその上に残された
ままの所定の下層電極配線パターンを形成し、
次に、上記電極配線パターンを含む上記半導体基板の表
面全体に第２の絶縁膜を形成し、その後、上記第１の絶
縁膜の部分の表面が露出するまで、上記第２の絶縁膜を
全面にエツチングし、上記第２の絶縁膜の部分を上記電
極配線パターンの側壁に残し、
引き続き、コンタクトホールを形成する工程を含む。[Means for Solving the Problems] A method for forming an electrode wiring according to the present invention includes forming a lower electrode wiring film over the entire surface of a semiconductor substrate, further forming a first insulating film over the entire surface of the lower electrode wiring film, and then, The lower electrode wiring film and the first insulating film are etched to form a predetermined lower electrode wiring pattern with a portion of the first insulating film remaining thereon, and then the electrode wiring pattern is etched. A second insulating film is formed on the entire surface of the semiconductor substrate including the first insulating film, and then the second insulating film is etched over the entire surface until the surface of the first insulating film is exposed. The method includes a step of leaving a portion of the insulating film on the side wall of the electrode wiring pattern and subsequently forming a contact hole.
［作用］
この発明に係る電極配線の形成方法は、下層電極配線パ
ターンの上部と側壁に、絶縁膜を形成するので、自己整
合的に上層電極配線と下地基板の電気的接触がとれる。[Operation] Since the method for forming an electrode wiring according to the present invention forms an insulating film on the upper part and sidewall of the lower electrode wiring pattern, electrical contact can be made between the upper electrode wiring and the base substrate in a self-aligned manner.
［実施例］ 以下、この発明の一実施例を図について説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.
第１Ａ図〜第１Ｆ図はこの発明の製造工程を示したもの
である。1A to 1F show the manufacturing process of this invention.
半導体基板たとえばシリコン基板１の主面上に、絶縁膜
２（たとえばシリコン酸化膜）を熱酸化、ＣＶＤ法等に
より形成する。その後、その上に下層電極配線膜３′
（たとえばポリシリコン）をＣＶＤ法、スパッタ法等に
より形成する。さらにその全体に、絶縁膜４′ （たと
えばシリコン窒化膜）をＣＶＤ法、スパッタ法等により
形成する（以上第１Ａ図）。An insulating film 2 (for example, a silicon oxide film) is formed on the main surface of a semiconductor substrate, for example, a silicon substrate 1, by thermal oxidation, CVD, or the like. After that, a lower electrode wiring film 3' is placed on top of it.
(for example, polysilicon) by CVD, sputtering, or the like. Furthermore, an insulating film 4' (for example, a silicon nitride film) is formed over the entire surface by CVD, sputtering, or the like (see FIG. 1A).
その後、写真製版とエツチング法によって、上記下層電
極配線膜３′と上記第１の絶縁膜４′をエツチングし、
上記第１の絶縁膜４′の部分４がその上に残されたまま
の所定の下層電極配線パターン３を形成する（第１Ｂ図
）。Thereafter, the lower electrode wiring film 3' and the first insulating film 4' are etched by photolithography and etching,
A predetermined lower electrode wiring pattern 3 is formed on which the portion 4 of the first insulating film 4' remains (FIG. 1B).
次に、上記下層電極配線パターン３を含む上記半導体基
板１の表面全体に第２の絶縁膜５′（たとえばシリコン
酸化膜）をＣＶＤ法、スパッタ法等により形成する。こ
のとき、下層電極配線パターン３の両側面では、絶縁膜
５′が厚く形成される（第１Ｃ図中、参照符号を参照）
。そして、下層電極配線パターン３の間には四部が形成
される。Next, a second insulating film 5' (for example, a silicon oxide film) is formed over the entire surface of the semiconductor substrate 1, including the lower electrode wiring pattern 3, by CVD, sputtering, or the like. At this time, a thick insulating film 5' is formed on both sides of the lower electrode wiring pattern 3 (see reference numerals in FIG. 1C).
. Then, four parts are formed between the lower electrode wiring patterns 3.
次に、上記第１の絶縁膜の部分４の表面が露出するまで
、上記第２の絶縁膜５′を全面に均等にエツチングする
。すると、上記第２の絶縁膜の部分５が下層電極配線パ
ターン３の側壁に残される（第１Ｄ図）。そして、下層
電極配線パターン３の間に位置する絶縁膜２は露出する
。Next, the second insulating film 5' is etched uniformly over the entire surface until the surface of the portion 4 of the first insulating film is exposed. Then, the portion 5 of the second insulating film is left on the side wall of the lower electrode wiring pattern 3 (FIG. 1D). Then, the insulating film 2 located between the lower electrode wiring patterns 3 is exposed.
次に、写真製版とエツチング法を用いて、下地基板との
電気的接触を必要とするところの絶縁膜２を除去し、コ
ンタクトホール１０を開ける（第１Ｅ図）。このとき、
下層電極配線パターン３の上部と側壁にはそれぞれ第１
の絶縁膜の部分４と第２の絶縁膜の部分５が残されてい
るので、これらの部分がマスクとなって、下層電極配線
パターン３を、コンタクトホールを開ける際のエツチン
グから守る。したがって、コンタクトホールの形成にあ
たって、マスクの位置合わせに高い精度を要求しない。Next, using photolithography and etching, the insulating film 2 that requires electrical contact with the underlying substrate is removed, and a contact hole 10 is opened (FIG. 1E). At this time,
The upper and side walls of the lower electrode wiring pattern 3 are each provided with a first electrode.
Since a portion 4 of the second insulating film and a portion 5 of the second insulating film remain, these portions serve as a mask to protect the lower electrode wiring pattern 3 from etching when forming the contact hole. Therefore, when forming contact holes, high accuracy is not required for mask alignment.
なお、第１Ｅ図において、下層電極配線パターン３の両
側にコンタクトホール１０を形成する場合には、写真製
版を行なう必要がなく、即エツチングすればよい。In addition, in FIG. 1E, when contact holes 10 are formed on both sides of the lower electrode wiring pattern 3, there is no need to perform photolithography, and etching may be performed immediately.
その後、上記コンタクトホール１０を含む半導体基板１
Φ表面全体に上層電極配線膜６を形成し、写真製版とエ
ツチング法により所定のパターンを形成する（第１Ｆ図
）。このとき、下層配線パターン３は絶縁膜４．５で覆
われているので、上層電極配線６と電気的に短絡するこ
とはない。そのため、この場合においても、写真製版で
形成するコンタクトホールは、下層電極配線パターン３
の間隔よりも広くてもよい。逆にいうと、本実施例に係
る電極配線の形成方法を採用する限り、下層電極配線パ
ターン３の間隔を相当小さくすることができる。これに
よって、半導体装置の集積度を容易に上げることができ
る。After that, the semiconductor substrate 1 including the contact hole 10 is
An upper electrode wiring film 6 is formed on the entire Φ surface, and a predetermined pattern is formed by photolithography and etching (FIG. 1F). At this time, since the lower layer wiring pattern 3 is covered with the insulating film 4.5, there will be no electrical short circuit with the upper layer electrode wiring 6. Therefore, in this case as well, the contact hole formed by photolithography is
may be wider than the interval between. In other words, as long as the electrode wiring formation method according to this embodiment is employed, the spacing between the lower electrode wiring patterns 3 can be made considerably smaller. Thereby, the degree of integration of the semiconductor device can be easily increased.
なお、上記実施例では、絶縁膜２が１層である場合につ
いて説明したが、この発明はこれに限られるものでなく
、絶縁膜２はシリコン酸化膜・シリコン窒化膜等の積層
膜であってもよい。In the above embodiment, the case where the insulating film 2 is a single layer has been described, but the present invention is not limited to this, and the insulating film 2 may be a laminated film such as a silicon oxide film or a silicon nitride film. Good too.
また、上記実施例では第１の絶縁膜４と第２の絶縁膜５
の材質が異なる場合について説明したが、両者は同一材
料であってもよい。Further, in the above embodiment, the first insulating film 4 and the second insulating film 5
Although the case has been described in which the materials are different, the two may be made of the same material.
さらに、上記実施例では、第２の絶縁膜５と絶縁膜２と
を同一の材料で形成した場合について説明したが、この
発明はこれに限られるものでなく、それらは異なった材
料であってもよい。Further, in the above embodiment, the second insulating film 5 and the insulating film 2 are formed of the same material, but the present invention is not limited to this, and they may be formed of different materials. Good too.
［発明の効果］
以上説明したとおり、この発明によれば、下層電極配線
パターンの上部および側壁部に絶縁膜を形成したので、
コンタクトホールを形成するにあたって、マスク位置合
わせに高い精度は要求されない。そのため、コンタクト
ホールを容易に形成できるという効果を奏する。また、
コンタクトホールを形成するための位置合わせに高い精
度が要求されない結果として、下層配線パターンの間隔
をより小さくすることが可能となり、半導体装置の集積
度をより一層上げられるという効果を奏する。[Effects of the Invention] As explained above, according to the present invention, since the insulating film is formed on the upper part and side wall part of the lower electrode wiring pattern,
When forming contact holes, high accuracy is not required for mask alignment. Therefore, there is an effect that contact holes can be easily formed. Also,
As a result of not requiring high precision in positioning for forming contact holes, it is possible to further reduce the spacing between the lower layer wiring patterns, which has the effect of further increasing the degree of integration of the semiconductor device.
第１Ａ図、第１Ｂ図、第１Ｃ図、第１Ｄ図、第１Ｅ図お
よび第１Ｆ図はこの発明の一実施例による、電極配線の
形成方法の工程を示す断面図である。第２Ａ図、第２Ｂ
図、第２Ｃ図および第２Ｄ図は従来の、電極配線の形成
方法を示す断面図である。
図において、１はシリコン半導体基板、３′は下層電極
配線膜、３は下層電極配線パターン、４′は第１の絶縁
膜、４は第１の絶縁膜の部分、５′は第２の絶縁膜、５
は第２の絶縁膜の部分、１０はコンタクトホールである
。
なお、各図中、同一符号は同一または相当部分を示す。FIGS. 1A, 1B, 1C, 1D, 1E, and 1F are cross-sectional views showing steps of a method for forming electrode wiring according to an embodiment of the present invention. Figure 2A, Figure 2B
2C and 2D are cross-sectional views showing a conventional method of forming electrode wiring. In the figure, 1 is a silicon semiconductor substrate, 3' is a lower electrode wiring film, 3 is a lower electrode wiring pattern, 4' is a first insulating film, 4 is a portion of the first insulating film, and 5' is a second insulating film. membrane, 5
is a portion of the second insulating film, and 10 is a contact hole. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
にその上全体に第１の絶縁膜を形成し、その後、前記下
層電極配線膜と前記第１の絶縁膜をエッチングし、前記
第１の絶縁膜の部分がその上に残されたままの所定の下
層電極配線パターンを形成し、 次に、前記下層電極配線パターンを含む前記半導体基板
の表面全体に第２の絶縁膜を形成し、その後、前記第１
の絶縁膜の部分の表面が露出するまで、前記第２の絶縁
膜を全面にエッチングし、前記第２の絶縁膜の部分を前
記下層電極配線パターンの側壁に残し、 引き続き、コンタクトホールを形成する工程を含む、電
極配線の形成方法。[Scope of Claims] A lower electrode wiring film is formed over the entire surface of a semiconductor substrate, a first insulating film is further formed over the entire surface of the semiconductor substrate, and then the lower electrode wiring film and the first insulating film are etched. , forming a predetermined lower electrode wiring pattern on which a portion of the first insulating film remains, and then forming a second insulating film over the entire surface of the semiconductor substrate including the lower electrode wiring pattern. and then the first
etching the second insulating film over the entire surface until the surface of the insulating film portion is exposed, leaving the second insulating film portion on the side wall of the lower electrode wiring pattern, and subsequently forming a contact hole. A method for forming electrode wiring, including a process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29134687A JPH01130546A (en) | 1987-11-17 | 1987-11-17 | Electrode wiring forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29134687A JPH01130546A (en) | 1987-11-17 | 1987-11-17 | Electrode wiring forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01130546A true JPH01130546A (en) | 1989-05-23 |
Family
ID=17767734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29134687A Pending JPH01130546A (en) | 1987-11-17 | 1987-11-17 | Electrode wiring forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01130546A (en) |
-
1987
- 1987-11-17 JP JP29134687A patent/JPH01130546A/en active Pending
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