JPS60198862A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the formation of a through hole on an interlayer insulating film and a shallow diffusion layer by a method wherein all connections between a wiring layer and a high impurity density active region are performed through the intermediary of a polycrystalline Si layer which was formed on the active region simultaneously with a gate electrode. CONSTITUTION:The polycrystalline Si 5, to be used for connection of a polycrystalline Si 4 for the gate electrode formed through the intermediary of a gate oxide film 3, and the polycrystalline Si 7 to be located on the Si oxide film 2 of an element isolation region are formed simultaneously on the surface of an Si substrate 1, and an interlayer insulating film 8 is provided thereon. Then, an etching is performed on the film 8 located on the Si 5 and 7. Subsequently, a wiring metal 9 is formed on the film 8, and the Si 5 on a high impurity density active region 6 is connected to the Si 7 on the film 2. According to this constitution, the difference in height of the Si 7 located on the film 2 is reduced by attaching the Si 5 on the region 6, and the formation of a through hole on the film 8 is made easier, because the difference in thickness of the film 8 to be formed at the upper part is equalized. Also, as a connection is performed between the metal 9 and the Si 5, a shallow diffusion layer 6 can be formed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly relates to a connection between a wiring layer and a high impurity concentration active region formed on the surface of a semiconductor substrate.

In general, in a semiconductor integrated circuit device, elements that are connected to wiring layers include a highly impurity-concentrated active region formed on the surface of a semiconductor substrate, a wiring layer of a polycrystalline silicon film formed above an element isolation region, and the like. To connect wiring layers in different areas, the interlayer insulating film is etched at the same time using a photo-etching mask, and then wiring material is formed and connections are made. The difference in height is different, the height difference is different, and the thickness of the interlayer insulating film is also different. For this reason, in order to form a through hole in the first interlayer insulating film, it is difficult to control the resolution in the process of exposing the photoresist using a photolithographic mask, and in the process of etching the five interlayer insulating films. The disadvantage is that it is difficult to control etching.

In addition, as integrated circuit devices have become smaller in recent years, the depth of the diffusion layer on semiconductor substrates has become shallower, but the depth of the diffusion layer is limited because the eutectic of the wiring material and semiconductor penetrates through the diffusion layer. There is a drawback that

An object of the present invention is to provide a semiconductor integrated circuit device that facilitates the formation of through holes in interlayer insulating films and also facilitates the formation of leaky diffusion layers.

In the semiconductor integrated circuit device of the present invention, all connections between the wiring layer and the high impurity concentration active region (diffusion layer) formed on the surface of the semiconductor substrate are attached to the high impurity concentration active region (diffusion layer). This is a semiconductor integrated circuit device characterized in that the gate electrode is formed through a polycrystalline silicon layer formed at the same time as the gate electrode.

The semiconductor integrated circuit device of the present invention has polycrystalline silicon r deposited on a high impurity concentration active region (diffusion layer) formed on the surface of a semiconductor substrate. In order to form a through hole in the interlayer insulating film, the difference in height between the silicon film and the silicon film becomes small, and the difference in the thickness of the interlayer insulating film formed on top becomes equal. The resolution can be easily controlled in the step of exposing the photoresist using a mask, and the etching can be easily controlled in the step of etching the interlayer insulating film to form through holes.

In addition, since the connection is made between the wiring metal and the polycrystalline silicon film, the eutectic of the wiring metal and the semiconductor substrate does not pass through the diffusion layer formed on the substrate, making it possible to easily form an extremely shallow diffusion layer. .

Next, embodiments of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views for explaining one embodiment of the present invention.

FIG. 1 shows polycrystalline silicon for a gate electrode formed on the surface of a silicon substrate 10 via a gate oxide film, polycrystalline silicon 5 for connection to a diffusion layer and wiring layer, and polycrystalline silicon for wiring on an element isolation region. Forming the shape of crystalline silicon 7 at the same time,
An interlayer insulating film 8 is provided on this. Next, the interlayer insulating film on the polycrystalline silicon 5 and 7 was etched using a photomask and a photoresistor, as shown in FIG.

Furthermore, a wiring metal 9 such as aluminum is formed on the interlayer insulating film and is connected to the polycrystalline silicon 5 on the diffusion layer and the polycrystalline silicon 7 on the element isolation region as shown in FIG.

According to this embodiment, it is possible to easily form through holes in the interlayer insulating film and also to form shallow diffusion layers.

[Brief explanation of the drawing]

1 to 3 are cross-sectional views showing embodiments of the present invention. In addition, in the figure, 1... silicon substrate, 2...
...Silicon oxide film, 3...Gate oxide film%4#5#7...Polycrystalline silicon, 6...
...Diffusion layer, 8...Interlayer insulating film, 9...
...Wiring materials.

Claims (1)

[Claims] A semiconductor integrated circuit characterized in that a polycrystalline silicon layer formed simultaneously with a gate electrode is provided on a high impurity concentration active region formed on a surface of a semiconductor substrate, and a metallization layer is connected to the polycrystalline silicon layer. Device.