JPH0442558A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0442558A JPH0442558A JP15014790A JP15014790A JPH0442558A JP H0442558 A JPH0442558 A JP H0442558A JP 15014790 A JP15014790 A JP 15014790A JP 15014790 A JP15014790 A JP 15014790A JP H0442558 A JPH0442558 A JP H0442558A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- resist
- oxide film
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241000628997 Flos Species 0.000 description 1
- GVOIQSXBMLNCLC-UHFFFAOYSA-N OOOS Chemical compound OOOS GVOIQSXBMLNCLC-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の素子分離構造の改良に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to improvements in element isolation structures of semiconductor devices.
従来の半導体装置の素子分離構造は、第２図の７０−の
様に、半導体基板９上に熱酸化法により薄い酸化膜１０
を形成した後（α）、シリコン窒化膜１１をＯＶＤ法に
より形成しくｂ）、フォトリソグラフィー法及びエツチ
ング法により素子分離領域のシリフン窒化膜を除去し、
能動領域１５にのみシリコン窒化膜を残す（Ｃ）。続い
て選択酸化により素子分離領域にのみ厚〜・酸化膜１４
を形成しくｄ）。 最期にシリコン窒化膜１５を除去（
ｅ）する事により、上部に不要な段差を持った素子分離
構造が形成されるものであった。In the conventional element isolation structure of a semiconductor device, a thin oxide film 10 is formed on a semiconductor substrate 9 by a thermal oxidation method, as shown at 70- in FIG.
After forming (α), a silicon nitride film 11 is formed by an OVD method, and b) the silicon nitride film in the element isolation region is removed by a photolithography method and an etching method.
The silicon nitride film is left only in the active region 15 (C). Next, by selective oxidation, a thick oxide film 14 is formed only in the element isolation region.
d). Finally, remove the silicon nitride film 15 (
By doing e), an element isolation structure with an unnecessary step at the top was formed.
しかし、前述の従来技術では不要な段差を上部に有する
素子分離構造であったために、フォトリソグラフィー法
による上層の配線形成時において段差が厳しいため、レ
ジストが段差下部で厚くなり配線形成に必要な適正露光
時間ではレジスト残りが発生し、配線間がショートして
しまう。また、上層配線が多層になって（ると、より段
差が厳しくなり、配線材料が段差下部まで十分につきま
わらず断線を引き起こすという課題を有していたそこで
本発明はこのような課題を解決するためにＬＯＯＯ３上
部の段差を無くすことによって平担化を行い、上層の配
線の配線間のショートや断線を防止することを目的とし
ている。However, since the above-mentioned conventional technology had an element isolation structure with an unnecessary step at the top, the step was severe when forming the upper layer wiring using the photolithography method, and the resist became thicker at the bottom of the step, making it difficult to properly form the wiring. During the exposure time, resist remains and short circuits occur between wiring lines. In addition, when the upper layer wiring becomes multilayered, the level difference becomes more severe, and there is a problem that the wiring material does not sufficiently reach the bottom of the level difference, causing disconnection.The present invention solves this problem. Therefore, the purpose is to flatten the upper layer of LOOO3 by eliminating the step difference, and to prevent short circuits and disconnections between the upper layer wirings.
本発明の半導体装置は、ＬＯＯＯＳの上部に段差が無い
構造を有することを特徴とする。The semiconductor device of the present invention is characterized in that it has a structure in which there is no step above the LOOOS.
第１図のフロスは本発明の実施例における断面図である
。半導体基板１上に熱酸化法により薄い酸化膜２を形成
した後（α）、シリコン窒化膜３をＣＶＤ法により形成
しくｂ）、フォトリソグラフィー法により素子分離４の
シリコン窒化膜を除去し、能動領域５にのみシリコン窒
化膜を残す（Ｃ）。 続いて選択酸化により素子分離領
域にのみ厚い酸化膜６を形成しくｄ）、シリコン窒化膜
を除去（ｅ）した上にレジストアを塗布して（１）全面
異方性エツチングをする。 このときレジストと厚い醸
化膜のエツチング速度を等しくして、レジストが無（な
るまで（ｇ）エツチングする。 こうしてＬＯＯＯｊ９
上部が平担な、段差が無い構造を形成することを可能に
した。The floss in FIG. 1 is a cross-sectional view of an embodiment of the present invention. After forming a thin oxide film 2 on the semiconductor substrate 1 by a thermal oxidation method (α), a silicon nitride film 3 is formed by a CVD method b), and the silicon nitride film of the element isolation 4 is removed by a photolithography method, and the active layer is removed. The silicon nitride film is left only in region 5 (C). Subsequently, a thick oxide film 6 is formed only in the element isolation region by selective oxidation (d), the silicon nitride film is removed (e), a resist is applied, and (1) the entire surface is anisotropically etched. At this time, the etching speed of the resist and the thick fostered film are set to be the same, and etching is continued until there is no resist ((g). In this way, LOOOj9
This made it possible to create a structure with a flat top and no steps.
なお、第１図の実施例においては厚い酸化膜の上にレジ
ストを塗布してエツチングしたが、これは平担化が可能
なものならレジスト塗布以外の方法でも可能である。ま
た、選択酸化を行なう際にシリコン窒化膜をマスクとし
て用いたが、選択酸化が可能であればマスクとしてシリ
コン窒化膜以外の材料を用いることが可能である。Incidentally, in the embodiment shown in FIG. 1, a resist was applied on the thick oxide film and etching was performed, but this can be done by other methods than resist application as long as planarization is possible. Further, although a silicon nitride film was used as a mask when performing selective oxidation, it is possible to use a material other than the silicon nitride film as a mask if selective oxidation is possible.
以上述べたように、本発明によれば厚い酸化膜をもつシ
リコン基板表面上にレジストを塗布してレジストと厚い
酸化膜のエツチング速度を等しくしてレジストが無（な
るまでエツチングして段差の無い平担な構造を有するＬ
ＯＯＯＳを形成することによって、段差による配線間の
シヲートや断線を防止することが可能な半導体装置の船
級を可能にさせる効果を有する。As described above, according to the present invention, a resist is applied on the surface of a silicon substrate having a thick oxide film, and the etching speed of the resist and the thick oxide film are made equal to each other, so that the etching process is performed until the resist is completely removed. L with a flat structure
The formation of OOOS has the effect of making it possible to classify semiconductor devices by preventing gaps between wiring lines and disconnections due to differences in level.
第１図（α）〜（！ｌ）は本発明の一実施例の主要断面
図であり、第２図（α）〜（−）は従来例の主要断面図
である。
１・−・・・・・・・半導体基板
２・・・・・・・・・シリコン酸化膜
３・−・・−・・・・シリコン窒化膜
４−−− ・・・−・・素子分離領域
５ ・−・・−・能動領域
６−・ ・・・ ・・・ ＬＯＧ！Ｏ８７・・・・・・
・・・レジスト
８−・・−・−上部に段差の無いＬＯＯＯＳ９− ・−
・、、・半導体基板
１０・・・−・・−シリコン酸化膜
１１−−− ・−シリコン窒化膜
１２−・−・・−・素子分離領域
１５− ・−・−能動領域
１ ４ −−−−・−Ｌ Ｏ００Ｓ
第１図
（ａ）
（ｅ）
第２図FIGS. 1(α) to (!l) are main sectional views of an embodiment of the present invention, and FIGS. 2(α) to (-) are main sectional views of a conventional example. 1.--...Semiconductor substrate 2.--Silicon oxide film 3.--.Silicon nitride film 4--..Element isolation Area 5 --- Active area 6 --- LOG! O87...
...Resist 8---LOOOS9-- with no step on the top--
・・・・Semiconductor substrate 10 --- Silicon oxide film 11 --- ・- Silicon nitride film 12 --- Element isolation region 15 -- ・-- Active region 1 4 --- -・-L O00S Figure 1 (a) (e) Figure 2
Claims (1)
部に段差がない構造を有することを特徴とする半導体装
置。A semiconductor device characterized by having a structure in which there is no step above a LOCOS in element isolation of a MOS-FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15014790A JPH0442558A (en) | 1990-06-08 | 1990-06-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15014790A JPH0442558A (en) | 1990-06-08 | 1990-06-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442558A true JPH0442558A (en) | 1992-02-13 |
Family
ID=15490525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15014790A Pending JPH0442558A (en) | 1990-06-08 | 1990-06-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442558A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052784A (en) * | 1995-12-07 | 1997-07-29 | 김주용 | Field oxide film planarization method of semiconductor device |
-
1990
- 1990-06-08 JP JP15014790A patent/JPH0442558A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970052784A (en) * | 1995-12-07 | 1997-07-29 | 김주용 | Field oxide film planarization method of semiconductor device |
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