JPS59211249A - Wirings forming method - Google Patents

Wirings forming method

Info

Publication number
JPS59211249A
JPS59211249A JP8625983A JP8625983A JPS59211249A JP S59211249 A JPS59211249 A JP S59211249A JP 8625983 A JP8625983 A JP 8625983A JP 8625983 A JP8625983 A JP 8625983A JP S59211249 A JPS59211249 A JP S59211249A
Authority
JP
Japan
Prior art keywords
wiring
wirings
insulating film
forming
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8625983A
Other languages
Japanese (ja)
Inventor
Kenjiro Tanase
棚瀬 健次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8625983A priority Critical patent/JPS59211249A/en
Publication of JPS59211249A publication Critical patent/JPS59211249A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the operating speed of a semiconductor device of multilayer wiring structure by forming a high melting point metal layer contacted with the first wirings in a contacting hole, thereby reducing the contacting resistance between the first wirings and the second wirings. CONSTITUTION:An impurity region 2 is formed on the surface of a silicon substrate 1, the first insulating film 3 is formed, the first contacting hole 4 is opened, and the first aluminum wirings 5 are formed. The second insulating film 6 is formed, with a resist 7 as a mask the second contacting hole 8 is opened, and Mo layer 9 is formed. The resist 7 is removed, the layer 9 is allowed to remain only in the hole 8, and the second wirings 10 which are contacted with the layer 9 are formed. Even if the substrate is heated to improve the step coverage at the time of forming the second wirings, no aluminum oxidized film is formed on the surface of the first wirings, and the contacting resistance between the first wirings and the second wirings can be reduced.

Description

【発明の詳細な説明】 ィ)産業上の利用分野 本発明は、基板上に形成さnたA4よりなる第1の配線
上に絶縁膜χ設け、該絶縁膜に穿ったコンタクトホール
を介して適宜上記第1の配線と接続さnる第2の配線ン
この絶縁膜上に形成する配線形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention provides an insulating film χ on a first wiring formed on a substrate and made of A4, and a contact hole formed in the insulating film. The present invention relates to a wiring formation method for forming a second wiring, which is appropriately connected to the first wiring, on this insulating film.

口)従来技術 近年、半導体装置の小型集積化に伴い、半導体基板上に
形成さ几る配線も多層構造が採ら几るようになってきて
いる。
BACKGROUND ART In recent years, as semiconductor devices have become smaller and more integrated, interconnections formed on semiconductor substrates have also become more compact.

このような多層配線を半導体基板上に形成するに際し、
従来は半導体基板上に第1の絶縁膜を介して下層配線と
なる第1の配線馨Alで設け、この第1の配線を含む基
板表面に第2の絶縁膜を形成し、上記第1の配線上の第
2の絶縁膜に適宜コンタクトホールを穿った後、このコ
ンタクトホール部で上記第1の配線と所望の接続状態で
接続されるように上記第2の絶縁膜上にスパタリング法
を用いてAI等の導電性金属よりなる第2の配線を形成
していた◇ ところで、このような第2の配線を形成するときは、第
1の配線との又差部等に存在する段部でノ配線金属の被
偵性(ステップカバレッジ)を良くするために、基板全
体音加熱しながら第2の配線形成のためのスパタリング
乞行っていた。
When forming such multilayer wiring on a semiconductor substrate,
Conventionally, a first wiring layer (Al) serving as a lower layer wiring is provided on a semiconductor substrate via a first insulating film, a second insulating film is formed on the substrate surface including the first wiring, and the first wiring is After appropriately forming a contact hole in the second insulating film on the wiring, a sputtering method is used on the second insulating film so that the contact hole is connected to the first wiring in a desired connection state. ◇ By the way, when forming such a second wiring, it is important to avoid the step part that exists at the difference between it and the first wiring. In order to improve the step coverage of the metal wiring, sputtering for forming the second wiring was performed while heating the entire board.

このため、第2の配線形成時、hlで形成さルた第1の
配線も加熱さ几、コンタクトホール部において露出して
いる第1の配線表面部が酸化さ几第1の配線と第2の配
線とのコンタクト抵抗が高くなり、半導体装置の動作速
度の低下につながる危険性があった。
Therefore, when forming the second wiring, the first wiring formed by HL is also heated, and the surface portion of the first wiring exposed in the contact hole portion is oxidized. There was a risk that the contact resistance with the wiring would increase, leading to a decrease in the operating speed of the semiconductor device.

ハ)発明の目的 本発明はこのような点に鑑みて為さfl、7′Cもので
あって、下層配線となる第1の配線と上層配線とこと2
目的とする。
C) Purpose of the Invention The present invention has been made in view of the above points, and includes a first wiring serving as a lower layer wiring and an upper layer wiring.
purpose.

二)発明の構成 本発明は、基板上に設けられたAlよりなる第1の配線
上に絶縁膜を形成するとともに、この絶縁膜上に所望の
レジストパターン2設け、このレジスト?!?マスクと
して上記絶縁膜に上記第1の配線上面を露出させるコン
タクトホールに穿ち、上記レジスト7用いたリフトオフ
技術によりコンタクトホール内にのみに高融点金属層乞
設けた後、上記コンタクトホール内の高融点金属層に接
する第2の配線?形成する構成を採っている。
2) Structure of the Invention In the present invention, an insulating film is formed on a first wiring made of Al provided on a substrate, and a desired resist pattern 2 is provided on this insulating film. ! ? A contact hole exposing the upper surface of the first wiring is formed in the insulating film as a mask, and a high melting point metal layer is formed only in the contact hole by a lift-off technique using the resist 7. The second wiring in contact with the metal layer? The structure is designed to form a structure.

ホ)実施例 第1図乃至第8図は本発明配線形成方法を工程順に示し
た断面図であって、これらの図乞用いて本発明を詳述す
る。まず、第1図のように一導電型半導体基板、例えば
P型のシリコン基板(1)表面に熱拡散法、イオン注入
法等を用いて抵抗、ダイオード、トランジスタ等の半導
体素子の構成要素となるN型の不純物領域(2)ン設け
た後、基板111全面に熱酸化法、CVO法等により、
SiO2よりなる第1の絶縁膜(3)を形成する。次に
上記不純物領域(2)上の第1の絶縁膜(3)適所に第
1のコンタクトホール(4)を穿ち(第2図)、スパタ
リング法を用いてこのコンタクトホール(4)を介して
上記不純物領域12)に接する第1の配線(51vAl
で形成する(第6図)。続いて、CVD法を用いて上記
第1の配線(5)を含む基板(1)全面1c S i 
02等の第2の絶縁膜t6120[J口〜5000A厚
程度に形成する(第4図)、その後、第1の配線(5)
上の第2の絶縁膜161Vciコンタクトホールな開設
するためのパターンが設ケらnたレジストmx形成し、
コルシスト(7)ンマスクとしてドライ又はウェットエ
ツチングを施ζして、第1の配線(5)上の第2の絶縁
膜(6)適所に第2のコンタクトホール(8)乞穿設す
る(第5図)。第2のコンタクトホール(8)穿設後、
上記レジス)i71F<残存させた状態でMO等の高融
点金属y1000A厚程度デポジットしてMo層(9)
ン形成する(第6図)。このときのデポジション条件は
例えばスバタリング法の場合、気圧2×10   To
rr4i力5KWであって、基板11)加熱乞せずに行
なう。次に、硝酸系のエッチャントで第2のコンタクト
ホール(8)側面に付着したM。
E) Embodiment FIGS. 1 to 8 are cross-sectional views showing the wiring forming method of the present invention in the order of steps, and the present invention will be explained in detail with reference to these figures. First, as shown in Figure 1, a thermal diffusion method, an ion implantation method, etc. are used on the surface of a semiconductor substrate of one conductivity type, such as a P-type silicon substrate (1), to form components of semiconductor elements such as resistors, diodes, and transistors. After providing the N-type impurity region (2), the entire surface of the substrate 111 is heated by thermal oxidation, CVO, etc.
A first insulating film (3) made of SiO2 is formed. Next, a first contact hole (4) is formed at a suitable location in the first insulating film (3) on the impurity region (2) (Fig. 2), and a sputtering method is used to form a first contact hole (4) through this contact hole (4). The first wiring (51vAl) in contact with the impurity region 12)
(Figure 6). Subsequently, using the CVD method, the entire surface of the substrate (1) including the first wiring (5) 1c Si
A second insulating film t6120 [J opening ~ 5000A thickness is formed (Fig. 4), and then the first wiring (5) is formed.
A resist mx with a pattern for opening a contact hole in the upper second insulating film 161Vci is formed,
Dry or wet etching is performed as a coruscist mask (7) to form a second contact hole (8) at a suitable location in the second insulating film (6) on the first wiring (5). figure). After drilling the second contact hole (8),
The above resist) i71F<Remaining state, deposit a high melting point metal such as MO to a thickness of about 1000A and Mo layer (9)
(Figure 6). For example, in the case of the subverting method, the deposition conditions at this time are atmospheric pressure 2×10 To
rr4i power is 5KW, and the substrate 11) is carried out without heating. Next, M was attached to the side surface of the second contact hole (8) using a nitric acid-based etchant.

tエツチングするとともに、上記レジスト(7)を除去
して、第2のコンタクトホール(8)内にのみMo層(
9)全残存させる(第7図)。続いて、HF系のエッチ
ャントでMo層(9)表面を洗浄し、基板11)全体を
600℃程度に加熱し良状態でスバタリング法等乞用い
てこの基板11)全面にAlのデポジションを行い、所
望形状にこのAltエツチングして、上記第2のコンタ
クトホール(8)でMo層(9)に接スる第2の配線U
αを形成し、多層配線構造を完成する(第8図)。この
ような第2の配線惺1形成時、基板;1)全体が加熱さ
ルるが第2のコンタクトホール(8)部の第1の配線(
5)はMo層(9)によって覆われているので、第1の
配線(5)上面にhlの酸化膜が形成さnることはない
。また、高融点金属であるMoは600°C程度の温度
では酸化さルることなく、Mo層(9)表面に酸化膜は
形成されない。
At the same time as etching, the resist (7) is removed to form a Mo layer (
9) Leave it all intact (Figure 7). Next, the surface of the Mo layer (9) was cleaned with an HF-based etchant, and the entire substrate 11) was heated to about 600°C, and in good condition, Al was deposited on the entire surface of the substrate 11) using a sputtering method or the like. , this Alt is etched into a desired shape, and a second wiring U is formed in contact with the Mo layer (9) through the second contact hole (8).
α is formed to complete the multilayer wiring structure (FIG. 8). When forming such a second wiring layer 1, the entire substrate (1) is heated, but the first wiring layer (1) in the second contact hole (8) is heated.
5) is covered with the Mo layer (9), no oxide film of hl is formed on the upper surface of the first wiring (5). Moreover, Mo, which is a high melting point metal, is not oxidized at a temperature of about 600° C., and no oxide film is formed on the surface of the Mo layer (9).

(へ)発明の効果 以上述べた如く、本発明配線形成方法は、第1の配線上
の絶縁膜にコンタクトホールを穿ち、このコンタクトホ
ール内に第1の配線に接実る高融点金属層を設けた後、
コンタクトホール内で上記高融点金属層に接する@2の
配線を絶縁膜上に形成しているので、第2の配線形成時
にステップカバレッジを良くするために基板の加熱を行
ってもコンタクトホール部の第1の配線表面[Aj7酸
化膜が形成さ几ることがなく、第1の配線と第2の配線
とのコンタクト抵抗を低減することが出来、この多層配
線形成方法を利用した半導体装置の動作速度の低下が防
止さ几る。さらに本発明はコンタクトホール開設のため
のレジストな用いたリフトオフ技術を利用して上記Mo
層の形成を行っているので、Mo鳩影形成ために全体を
通しての配線形成の工程が復雑になることもない。
(F) Effects of the Invention As described above, in the wiring forming method of the present invention, a contact hole is formed in the insulating film on the first wiring, and a high melting point metal layer that is in contact with the first wiring is provided in the contact hole. After
Since the @2 wiring in contact with the refractory metal layer inside the contact hole is formed on the insulating film, even if the substrate is heated to improve step coverage when forming the second wiring, the contact hole area will not be affected. The first wiring surface [Aj7 oxide film is not formed and the contact resistance between the first wiring and the second wiring can be reduced, and the operation of a semiconductor device using this multilayer wiring formation method is Prevents speed reduction. Furthermore, the present invention utilizes a lift-off technique using a resist to open a contact hole.
Since layers are formed, the process of forming wiring throughout the entire structure does not become complicated due to the formation of Mo dot shadows.

【図面の簡単な説明】[Brief explanation of drawings]

第1因乃至第8図は本発明配線形成方法を工程順に示し
た断面図であって、111は半導体基板、(3)(6)
は絶縁膜、+51ulは配線、(9)はMo層を夫々示
している。
1 to 8 are cross-sectional views showing the wiring forming method of the present invention in the order of steps, in which 111 is a semiconductor substrate, (3) (6)
(9) indicates an insulating film, +51ul indicates a wiring, and (9) indicates a Mo layer.

Claims (1)

【特許請求の範囲】[Claims] 基板−1jc形成さnたAlよりなる第1の配線上に絶
縁膜を設けるとともに、該絶縁膜に穿ったコンタクトホ
ール2介して適宜上記第1の配線と接続される第2の配
線馨この絶縁膜上に形成するに際し、基板上にA、14
w用いて編1の配線を形成する工程と、上記基板上に第
1の配線を覆り絶縁膜を形成する工程と、この絶縁膜上
に所望のレジストパターンを設け、このレジストパター
ンとして第1の配線上の絶縁膜適所にコンタクトホール
を開設する工程と、上記コンタクトホール開設のマスク
となったレジスト乞利用し文リフトオフ技術により、上
記コンタクトホール内にのみ高融点金属層を設ける工程
と、上記基板全面を加熱しながら上記コンタクトホール
内の高融点金属層に接する第2の配線乞上記絶縁膜上に
形成する工程と、から成る配線形成方法。
An insulating film is provided on the first wiring made of Al formed on the substrate 1, and a second wiring is connected to the first wiring as appropriate through a contact hole 2 formed in the insulating film. When forming on the film, A, 14 on the substrate
a step of forming a wiring of the first layer using w, a step of forming an insulating film covering the first wiring on the substrate, a step of forming a desired resist pattern on the insulating film, and forming the first wiring as the resist pattern. a step of opening a contact hole in the appropriate location of the insulating film on the wiring, a step of providing a high-melting point metal layer only in the contact hole using a resist-required lift-off technique that serves as a mask for opening the contact hole; A wiring forming method comprising the steps of: forming a second wiring on the insulating film in contact with the refractory metal layer in the contact hole while heating the entire surface of the substrate.
JP8625983A 1983-05-16 1983-05-16 Wirings forming method Pending JPS59211249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8625983A JPS59211249A (en) 1983-05-16 1983-05-16 Wirings forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8625983A JPS59211249A (en) 1983-05-16 1983-05-16 Wirings forming method

Publications (1)

Publication Number Publication Date
JPS59211249A true JPS59211249A (en) 1984-11-30

Family

ID=13881818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8625983A Pending JPS59211249A (en) 1983-05-16 1983-05-16 Wirings forming method

Country Status (1)

Country Link
JP (1) JPS59211249A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365643A (en) * 1986-09-05 1988-03-24 Nec Corp Manufacture of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374888A (en) * 1976-12-15 1978-07-03 Fujitsu Ltd Manufacture of semiconductor device
JPS5723224A (en) * 1980-07-18 1982-02-06 Nec Corp Manufacture of semiconductor integrated circuit
JPS57208161A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374888A (en) * 1976-12-15 1978-07-03 Fujitsu Ltd Manufacture of semiconductor device
JPS5723224A (en) * 1980-07-18 1982-02-06 Nec Corp Manufacture of semiconductor integrated circuit
JPS57208161A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365643A (en) * 1986-09-05 1988-03-24 Nec Corp Manufacture of semiconductor device

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