JPH0442559A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0442559A JPH0442559A JP15015590A JP15015590A JPH0442559A JP H0442559 A JPH0442559 A JP H0442559A JP 15015590 A JP15015590 A JP 15015590A JP 15015590 A JP15015590 A JP 15015590A JP H0442559 A JPH0442559 A JP H0442559A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- patterning
- silicon substrate
- semiconductor device
- scribe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 7
- 229910052782 aluminium Inorganic materials 0.000 abstract 7
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特にウェハプロセスで形成され
る集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly an integrated circuit formed by a wafer process.
本発明は、半導体装置の製造方法において、スクライブ
領域に選択的にA1配線を形成する事により、スクライ
ブ表面のAlエツチング残りを防止し、次工程でのA1
の離脱による不良を防止するものである。In the method of manufacturing a semiconductor device, the present invention prevents Al etching residue on the scribe surface by selectively forming A1 wiring in the scribe area, and
This prevents defects due to detachment.
従来、スクライブ領域を形成する方法として、第2図に
あるように、スクライブ領域にはシリコン基板が露出し
、スクライブ端部となる部分には絶縁膜101およびパ
ッシベーション膜103で構成されるような工程が用い
られている。Conventionally, as shown in FIG. 2, a method for forming a scribe region involves a process in which a silicon substrate is exposed in the scribe region and an insulating film 101 and a passivation film 103 are formed at the scribe end portion. is used.
しかし、前述の従来の技術においては、プロセスの各工
程においてシリコン基板が露出するようにエツチング加
工を行なう為、スクライブ領域のシリコン基板が各エツ
チング工程で徐々にエツチングされていく、特に、スク
ライブ端部においては絶縁膜の端部がせっぴ状になるほ
どシリコン基板がエツチングされてしまう、このような
状況の中で、次工程特にA1配線形成時におけるレジス
ト露光時において、前述のスクライブ端部に塗布された
レジストは、十分に露光されない事がある。However, in the above-mentioned conventional technology, etching is performed to expose the silicon substrate in each step of the process, so the silicon substrate in the scribe area is gradually etched in each etching step, especially at the edges of the scribe. In such a situation, the silicon substrate is etched to the extent that the edges of the insulating film become sparse. Under these circumstances, in the next process, especially during resist exposure during the formation of the A1 wiring, the silicon substrate is coated on the edges of the scribe described above. The resist may not be fully exposed.
その結果として、次工程のレジスト剥離工程において、
このAlが離脱してICチップ表面に付着し、信頼性上
の問題を発生させる事が考えられる。As a result, in the next resist stripping step,
It is conceivable that this Al may detach and adhere to the surface of the IC chip, causing reliability problems.
本発明は、このような従来の半導体装置の問題点を解決
するもので、その目的とするところは、より安定した信
頼性の高い半導体装置を提供するところにある。The present invention solves these problems of conventional semiconductor devices, and its purpose is to provide a more stable and reliable semiconductor device.
本発明の半導体装置の製造方法は、シリコンウェハのス
クライブ領域において、シリコン基板表面に第1の酸化
膜を形成する工程、前記第1の酸化膜のパターンニング
後に第2の金属膜を形成する工程、前記第2の金属膜の
パターンニング後に第3のパッシベーション膜を形成し
、前記第3のパッシベーション膜をパターンニングを行
なう工程から成る事を特徴とする。The method for manufacturing a semiconductor device of the present invention includes a step of forming a first oxide film on the surface of a silicon substrate in a scribe region of a silicon wafer, and a step of forming a second metal film after patterning the first oxide film. , forming a third passivation film after patterning the second metal film, and patterning the third passivation film.
第1図は、本発明の実施例における半導体装置の製造工
程に従う断面図である。FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
まず、第1図(a)にあるように、比抵抗10(Ω−c
m)のN型シリコン基板100上に、二酸化珪素からな
る絶縁膜101を通常の熱酸化法で形成しパターンニン
グを行なう。First, as shown in Figure 1(a), the specific resistance is 10 (Ω-c
An insulating film 101 made of silicon dioxide is formed on the N-type silicon substrate 100 (m) by a normal thermal oxidation method and patterned.
次に、第1図(b)にあるように、A1102を通常の
蒸着あるいはスパッタリングにより形成させる。Next, as shown in FIG. 1(b), A1102 is formed by normal vapor deposition or sputtering.
次に、第1図(e)にあるように、前記のA1をパター
ンニングし、Al配線層を形成させる。Next, as shown in FIG. 1(e), the above-mentioned A1 is patterned to form an Al wiring layer.
このA1配線はシリコン基板100に直接接し、ならび
に絶縁膜101上にオーバーラツプするようなパターン
で構成されている。The A1 wiring is in direct contact with the silicon substrate 100 and has a pattern that overlaps the insulating film 101.
次に、第1図(d)にあるように、前記パターン上にパ
ッシベーション膜103を形成しパターンニングを行な
う。Next, as shown in FIG. 1(d), a passivation film 103 is formed on the pattern and patterning is performed.
以上の工程を経てスクライブ領域が形成される。A scribe area is formed through the above steps.
本実施例においては、A1配線層は1層構造の場合を示
したが、2層以上の多層配線の場合にも前述した工程と
同様な工程を追加する事で実現出来る。また、形成する
AI配線幅は、ダイシング時に影響が出ないような適切
な幅を採用しなければならない。In this embodiment, the A1 wiring layer has a one-layer structure, but a multilayer wiring of two or more layers can also be realized by adding steps similar to those described above. Furthermore, the width of the AI wiring to be formed must be an appropriate width that does not affect the dicing process.
以上述べたように、本発明によれば、スクライブ領域の
Al残りによる不良を防止する対策として、スクライブ
部のA1残りが生じやすい箇所に積極的にAl配線パタ
ーンとして形成させる事により、A1のエツチング残り
を防ぐことができる。As described above, according to the present invention, as a measure to prevent defects due to Al residue in the scribe area, Al wiring patterns are actively formed in areas where Al residue is likely to occur in the scribe area, thereby preventing A1 etching. The rest can be prevented.
その結果、次工程でそのA1等がICチップ上に付着し
て起こす不良を低減する事ができ、より信頼性の高い半
導体装置を提供する事が出来る。As a result, it is possible to reduce defects caused by A1 etc. adhering to the IC chip in the next process, and it is possible to provide a more reliable semiconductor device.
102・・・Al配線 103・・・パッシベーション膜 以 上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木 喜三部 化1名102...Al wiring 103...passivation film that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (1 person)
第1図は、本発明による実施例の半導体装置の断面図で
ある。
第2図は、従来の半導体装置の構造を示す断面図である
。
100・・・N型シリコン基板
101・・・絶縁膜FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device. 100...N-type silicon substrate 101...Insulating film
Claims (1)
基板表面に第1の酸化膜を形成する工程、前記第1の酸
化膜のパターンニング後に第2の金属膜を形成する工程
、前記第2の金属膜のパターンニング後に第3のパッシ
ベーション膜を形成し、前記第3のパッシベーション膜
をパターンニングを行なう工程から成る事を特徴とする
半導体装置の製造方法。A step of forming a first oxide film on the surface of a silicon substrate in a scribe region of a silicon wafer, a step of forming a second metal film after patterning the first oxide film, and a patterning of the second metal film. A method for manufacturing a semiconductor device, comprising the steps of subsequently forming a third passivation film and patterning the third passivation film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15015590A JPH0442559A (en) | 1990-06-08 | 1990-06-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15015590A JPH0442559A (en) | 1990-06-08 | 1990-06-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0442559A true JPH0442559A (en) | 1992-02-13 |
Family
ID=15490707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15015590A Pending JPH0442559A (en) | 1990-06-08 | 1990-06-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0442559A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326697A (en) * | 1992-05-23 | 1993-12-10 | Sony Corp | Manufacture of semiconductor device |
-
1990
- 1990-06-08 JP JP15015590A patent/JPH0442559A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326697A (en) * | 1992-05-23 | 1993-12-10 | Sony Corp | Manufacture of semiconductor device |
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