JPH0457342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0457342A JPH0457342A JP16660990A JP16660990A JPH0457342A JP H0457342 A JPH0457342 A JP H0457342A JP 16660990 A JP16660990 A JP 16660990A JP 16660990 A JP16660990 A JP 16660990A JP H0457342 A JPH0457342 A JP H0457342A
- Authority
- JP
- Japan
- Prior art keywords
- grid line
- interlayer insulating
- film
- passivation film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 abstract description 27
- 239000002184 metal Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000956 alloy Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001007 puffing effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、多層配線形成工程を有する半導体装置の製
造方法に係り、特に多層配線形成工程時におけるグリッ
ドライン部での処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring formation process, and particularly relates to processing at a grid line portion during the multilayer wiring formation process.
（従来の技術）
従来、グリッドライン部は、チップ分割処理（スクライ
ブ処理）時に、チップ内部へのクラック発生防止を目的
に、パターニング工程毎に必ずグリッドライン部上に形
成される膜はエツチング除去され、Ｓｉ基板が露出して
いるのが常であった。(Prior art) Conventionally, the film formed on the grid line portion is removed by etching during each patterning process to prevent cracks from occurring inside the chip during chip division processing (scribing processing). , the Si substrate was usually exposed.
（発明が解決しようとする課題）
しかしながら、多層配線形成工程において上記従来技術
を使用すると、グリッドライン部のアスペクト比が高く
なり、
■ 平坦化技術としてＳｉＯ□系被膜形成用塗布液（Ｓ
ＯＧ材）を使用すると、グリッドライン部でＳＯＧ材溜
りが多くなり、千ンブ上ＳＯＧ材キュア条件下でのグリ
ッドライン部ＳＯＧ材キュアが不充分となり、その後の
熱処理工程にて、当該部よりクラック、ハガレなどが生
じる。(Problems to be Solved by the Invention) However, when the above-mentioned conventional technology is used in the multilayer interconnection forming process, the aspect ratio of the grid line portion becomes high.
When SOG material is used, a large amount of SOG material accumulates at the grid line area, and the SOG material at the grid line area is not cured sufficiently under the SOG material curing conditions on Senbu.In the subsequent heat treatment process, cracks occur from that area. , peeling, etc. may occur.
■ ホトリソ工程でレジスト溜りを生じ、チップ内パタ
ーニング露光・現象条件下でレジスト残りを生じる。当
該部は、その後のエツチングにおいても層間絶縁膜が残
り、スクライプ処理時にチップ内クランクを誘発する。■ Resist pools occur during the photolithography process, and resist remains under the conditions of in-chip patterning exposure and development. In this part, the interlayer insulating film remains even during subsequent etching, which causes cranking within the chip during the scribing process.
また、グリッドライン部のレジストを完全に除去する露
光・現象条件下では、チップ内パターン形成が困難とな
る。Further, under exposure/phenomenal conditions that completely remove the resist in the grid line portion, it becomes difficult to form patterns within the chip.
などの問題が生じ、この問題は多層化が進む程、より顕
著となってくる。Problems such as these arise, and this problem becomes more prominent as the number of layers increases.
この発明は上記の点に鑑みなされたもので、多層配線形
成工程でのグリッドライン部にかかわる上述問題点を解
決し得る半導体装置の製造方法を提供することを目的と
する。The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problems regarding grid line portions in a multilayer wiring formation process.
（課題を解決するための手段）
この発明は、半導体基板上に多層配線を形成するように
した半導体装置の製造方法において、多層配線形成時に
、層間絶縁膜を半導体基板のグリッドライン部上に残し
、その後の工程、すなわち多層配線形成後パッシベーシ
ョン膜を形成し、そのパッシベーション膜をパターニン
グする際に、同時にパッシベーション膜とともに層間絶
縁膜をグリッドライン部上から除去するようにしたちの
である。(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which multilayer wiring is formed on a semiconductor substrate, in which an interlayer insulating film is left on the grid line portion of the semiconductor substrate when forming the multilayer wiring. In the subsequent process, that is, when forming a passivation film after forming multilayer wiring and patterning the passivation film, the interlayer insulating film is simultaneously removed from above the grid line portion along with the passivation film.
（作 用）
層間絶縁膜を半導体基板のグリッドライン部上に残存さ
せ、これをパッシベーション膜のパターニング工程で同
時に除去するようにすれば、パッシベーション膜のパタ
ーニング工程（最終工程）までグリッドライン部上に深
い溝は発生しない。(Function) If the interlayer insulating film is left on the grid line part of the semiconductor substrate and removed at the same time as the passivation film patterning process, the interlayer insulating film will remain on the grid line part until the passivation film patterning process (final process). Deep grooves do not occur.
したがって、グリッドライン部上の高アスペクト比（深
い溝の発生）に原因する多層配線形成工程での諸問題は
解決され、ひいてはスクライブ処理時のクラック発生な
ども回避される。Therefore, various problems in the multilayer wiring formation process caused by the high aspect ratio (occurrence of deep grooves) on the grid line portion are solved, and cracks during the scribing process are also avoided.
（実施例） 以下この発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
第１図（ａ）において、１はＳｉ基板、２はフィールド
酸化膜、３は中間絶縁膜、４は第１層メタル配線であり
、この第１層メタル配線形成工程までは従来技術と同様
に、グリッドライン部上に形成される膜はすべてエツチ
ング除去し、グリッドライン部はＳｉ基板１を露出させ
る。In FIG. 1(a), 1 is a Si substrate, 2 is a field oxide film, 3 is an intermediate insulating film, and 4 is a first layer metal wiring, and the steps up to this first layer metal wiring formation process are the same as in the conventional technology. All the films formed on the grid line portions are removed by etching, and the Si substrate 1 is exposed at the grid line portions.
次に、Ｓｉ基板１上の全面に第１図［有］）に示すよう
に層間絶縁膜５を形成する。そして、この層間絶縁膜５
にメタル配線間の導通をとるために通常のホトリソ・エ
ツチング除去で図示しないスルーホールを形成し、この
時、従来は同時にグリッドライン部から層間絶縁膜を除
去するが、この発明の一実施例では除去せず、第１図い
）に示すように層間絶縁膜５を残す。Next, an interlayer insulating film 5 is formed on the entire surface of the Si substrate 1 as shown in FIG. Then, this interlayer insulating film 5
A through hole (not shown) is formed by normal photolithography and etching removal in order to establish conduction between the metal wirings.At this time, conventionally, the interlayer insulating film is removed from the grid line portion at the same time, but in one embodiment of the present invention, The interlayer insulating film 5 is not removed, but is left as shown in FIG.
次に、メタルの被着とパターニングにより、前記層間絶
縁膜５上に、スルーホールを通して第１層メタル配ｆＩ
４と導通をとって第２層メタル配線６を第１図（Ｃ）に
示すように形成する。さらにその第２層メタル配線上を
含む全面にＰＳＧまたはｐｓｃとＳｉＮまたはＳｉＮ単
層のパッシベーション膜７を形成する。Next, by depositing and patterning a metal, the first layer metal wiring fI is formed through a through hole on the interlayer insulating film 5.
A second layer metal wiring 6 is formed as shown in FIG. Furthermore, a passivation film 7 made of PSG or psc and SiN or a single layer of SiN is formed over the entire surface including the second layer metal wiring.
その後、ポリイミド系樹脂８を１０−程度、第１図（ｄ
ｌに示すようにパッシベーション膜７上の全面に形成し
、最終段温度３５０°Ｃのステップキュアーを行う。次
いで、ポリイミド系樹脂８上の全面にＭ系合金膜９を５
００人無加熱スパッタにより形成する。After that, polyimide resin 8 was applied to about 10-degrees as shown in Fig. 1(d).
As shown in FIG. 1, it is formed on the entire surface of the passivation film 7, and step curing is performed at a final stage temperature of 350°C. Next, 5 M-based alloy films 9 are applied to the entire surface of the polyimide resin 8.
Formed by 00 person non-heating sputtering.
次に、Ｍ系合金膜９上に第１図（ｅ）に示すように通常
のホトリソ工程でレジストパターン１０を形成し、それ
をマスクとして、ＢＣＩｓガスを用いたドライエツチン
グによりポンディングパッド部並びにグリッドライン部
上のＭ系合金膜９を同図に示すように除去する。さらに
、当該部分のポリイミド系樹脂８を０２またはＯ８を用
いたアンンングにより第１図（ｆ）に示すように除去す
る。Next, as shown in FIG. 1(e), a resist pattern 10 is formed on the M-based alloy film 9 by a normal photolithography process, and using this as a mask, dry etching is performed using BCIs gas to form the bonding pad portion and the resist pattern 10. The M-based alloy film 9 on the grid line portion is removed as shown in the figure. Furthermore, the polyimide resin 8 in the area is removed by unwinding using O2 or O8, as shown in FIG. 1(f).
その後、残存Ｍ系合金膜９をマスクに、ボンディングバ
ンド部上のパッシベーション膜７、並びにグリッドライ
ン部上のパッシベーション膜７と層間絶縁膜５を周知の
ドライエツチング技術により前記第１図（ｆ）に示すよ
うに除去する。最後に同第１図（ｆ）に示すように、残
存ポリイミド系樹脂８上のＭ系合金膜９をドライエツチ
ングにより除去する。Thereafter, using the remaining M-based alloy film 9 as a mask, the passivation film 7 on the bonding band portion, the passivation film 7 on the grid line portion, and the interlayer insulating film 5 are etched using a well-known dry etching technique as shown in FIG. 1(f). Remove as shown. Finally, as shown in FIG. 1(f), the M alloy film 9 on the remaining polyimide resin 8 is removed by dry etching.
（発明の効果）
以上詳細に説明したように、この発明の製造方法によれ
ば、層間絶縁膜を半導体基板のグリッドライン部上に残
存させ、これをパッシベーション膜のパターニング工程
で同時に除去するようにしたので、パフシヘーション膜
のパターニング工程（最終工程）までグリッドライン部
上には深い溝が発生しない。したがって、グリッドライ
ン部上の高アスペクト比（深い溝の発生）に原因する多
層配線形成工程での諸問題を解決でき、ひいてはスクラ
イブ処理時のクラック発生なども回避できる。(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, the interlayer insulating film remains on the grid line portion of the semiconductor substrate, and is removed at the same time as the passivation film patterning step. Therefore, deep grooves are not generated on the grid line portion until the puffing film patterning step (final step). Therefore, various problems caused by the high aspect ratio (occurrence of deep grooves) on the grid line portion in the multilayer wiring formation process can be solved, and cracks can also be avoided during the scribing process.
第１図はこの発明の半導体装置の製造方法の一実施例を
示す工程断面図である。
■・・・Ｓｔ基板、４・・・第１層メタル配線、５・・
・層間絶縁膜、６・・・第２層メタル配線、７・・・パ
ノシヘーション膜。FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention. ■... St substrate, 4... 1st layer metal wiring, 5...
- Interlayer insulating film, 6... Second layer metal wiring, 7... Panoscination film.
Claims (1)
装置の製造方法において、 多層配線形成時に、層間絶縁膜を半導体基板のグリッド
ライン部上に残し、その後の工程、すなわち、多層配線
形成後パッシベーション膜を形成し、そのパッシベーシ
ョン膜をパターニングする際に、同時にパッシベーショ
ン膜とともに層間絶縁膜をグリッドライン部上から除去
することを特徴とする半導体装置の製造方法。[Claims] In a method of manufacturing a semiconductor device in which multilayer wiring is formed on a semiconductor substrate, an interlayer insulating film is left on the grid line portion of the semiconductor substrate when forming the multilayer wiring, and subsequent steps, that is, 1. A method of manufacturing a semiconductor device, comprising: forming a passivation film after forming a multilayer wiring; and, when patterning the passivation film, simultaneously removing an interlayer insulating film from above a grid line portion together with the passivation film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16660990A JPH0457342A (en) | 1990-06-27 | 1990-06-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16660990A JPH0457342A (en) | 1990-06-27 | 1990-06-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457342A true JPH0457342A (en) | 1992-02-25 |
Family
ID=15834479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16660990A Pending JPH0457342A (en) | 1990-06-27 | 1990-06-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457342A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019029640A (en) * | 2017-07-26 | 2019-02-21 | 株式会社沖データ | Method for manufacturing driven element chip and driven element chip, exposure device, and image forming apparatus |
-
1990
- 1990-06-27 JP JP16660990A patent/JPH0457342A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019029640A (en) * | 2017-07-26 | 2019-02-21 | 株式会社沖データ | Method for manufacturing driven element chip and driven element chip, exposure device, and image forming apparatus |
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