JP2019029640A - Method for manufacturing driven element chip and driven element chip, exposure device, and image forming apparatus - Google Patents

Abstract

To make it possible to easily manufacture a high-quality driven element chip.SOLUTION: In an image forming apparatus 1, in manufacturing light emitting element chips 73 to be mounted on a print head 33, dummy metals DM are arranged on a semiconductor wafer 100 while avoiding X gap areas 107 to be the boundaries of the light emitting element chips 73. On the semiconductor wafer 100, grooves with a sufficient depth can thus be formed by the DRIE method with an extremely high position accuracy compliant with a process rule, while reducing the number of processes and the types of gases to be used without the need to remove a metal material. The image forming apparatus 1 comprising the print head 33 on which the light emitting element chips 73 can thus form an extremely high-quality image.SELECTED DRAWING: Figure 13

Description

  The present invention relates to a driven element chip manufacturing method, a driven element chip, an exposure apparatus, and an image forming apparatus, and is suitable for application to, for example, an electrophotographic printer (hereinafter also referred to simply as a printer).

  As a conventional printer, light is selectively applied to the surface of the photosensitive drum from an exposure apparatus in which a plurality of light emitting elements such as LEDs (Light Emitting Diodes) and light emitting thyristors are arranged and arranged on the surface of the photosensitive drum. An image that prints an image by forming an electrostatic latent image, and further developing the toner image by attaching toner to the electrostatic latent image is widely used.

  Among them, in the exposure apparatus, a plurality of light emitting elements (hereinafter also referred to as driven elements) and a light emitting element chip (hereinafter also referred to as driven element chips) provided with a plurality of drive circuits for driving each light emitting element, etc. Are mounted in a state of being aligned on a predetermined circuit board.

  As a light-emitting element chip, a chip in which a plurality of epitaxial films (hereinafter also referred to as epifilms) that are sheet-like semiconductor thin films are attached to the surface has been proposed (for example, see Patent Document 1). In this light emitting element chip, after the light emitting element is formed in advance on the epifilm, the epifilm is attached to the surface.

JP2007-81081A (FIG. 5 etc.)

  By the way, in the light emitting element chip, a wiring layer (hereinafter also referred to as a metal layer) in which a wiring pattern made of a metal such as aluminum is formed is formed over a plurality of layers at a location relatively close to the inner surface. Yes. For this reason, the surface of the light emitting element chip may have a shape in which the portion where the wiring pattern is formed is raised more than the other portion.

  In such a case, in the light emitting element chip, it is difficult to stably adhere the epifilm to the surface, and the optical axis of the light emitted from the light emitting element may be inclined, leading to a decrease in quality. In addition, in the light emitting element chip, when an epifilm is attached to the surface, there is a possibility that a gap is generated between the surface and the epifilm. There is also a risk that the surface of the chip will be cut unnecessarily.

  Therefore, in the light emitting element chip, an electrically insulated metal piece (hereinafter referred to as a dummy metal or a dummy) made of the same thickness and material as the wiring pattern or the like in a portion where the wiring pattern or the like is not formed in the wiring layer. In some cases, a method of arranging a conductor) is used. In this case, in the light emitting element chip, the difference in surface height between the part where the wiring pattern is formed and the other part becomes extremely small, and it is possible to increase the smoothness and stably attach the epifilm. Become.

  In the manufacturing process, such a light emitting element chip is manufactured by performing an exposure process or the like on the surface of a semiconductor wafer made of silicon or the like, like a general semiconductor element. This semiconductor wafer is cut into a grid by performing a dividing process such as dicing after a light emitting element and a drive circuit are simultaneously formed by aligning a plurality of light emitting element chips in a grid by an exposure process or the like. Thus, the light emitting element chips are divided.

  In particular, when a dummy metal is disposed, in dicing, a method of cutting with a cutter that rotates a thin disk-shaped blade at a high speed is common. However, in a cutter that rotates a blade, generally, a certain amount of “blur” occurs in the rotating blade, and the accuracy of the cutting position is reduced.

  In other words, in the case of a light emitting element chip, when a dummy metal is arranged for the purpose of smoothing the surface in order to stably adhere an epifilm, it is difficult to cut accurately during dicing at the time of manufacture, which may lead to a decrease in quality. There was a problem that there was.

  The present invention has been made in consideration of the above points, and a method of manufacturing a driven element chip capable of easily manufacturing a high quality driven element chip, a high quality driven element chip, an exposure apparatus, and an image forming apparatus Is to try to propose.

  In order to solve this problem, the driven element chip manufacturing method of the present invention is a driven element chip manufacturing method in which a semiconductor wafer is divided to manufacture a plurality of driven element chips. Includes a chip base having an arrangement surface, a group of driven elements provided on the arrangement surface, in which a plurality of driven elements are aligned along the alignment direction, and arranged inside the chip base. A conductive layer having a wiring portion electrically connected to a component that drives a driven element and a dummy conductor disposed in a portion of the conductive layer where the wiring portion is not disposed are provided, and the semiconductor wafer is driven When the dummy conductor is disposed in the conductive layer, avoiding the gap between the element chips, and when divided into a plurality of the driven element chips, it becomes at least the side surface on the alignment direction side in the arrangement surface. The portion was so groove by etching process is formed.

  In the driven element chip of the present invention, a chip base having an arrangement surface, a driven element group provided on the arrangement surface, in which a plurality of driven elements are aligned along the alignment direction, and the inside of the chip base And a conductive layer having a wiring portion electrically connected to a driven element or a component that drives the driven element, and a dummy conductor arranged in a portion of the conductive layer where the wiring portion is not arranged, The side surface of the chip substrate, which is at least the side surface on the alignment direction side of the arrangement surface, is formed by an etching process.

  Further, in the exposure apparatus of the present invention, the plurality of driven element chips described above and a substrate attached with the plurality of driven element chips arranged in the main scanning direction are provided.

  Furthermore, in the image forming apparatus of the present invention, the above-described exposure apparatus and a control unit that supplies a signal corresponding to the image to be formed to the exposure apparatus are provided.

  According to the present invention, since the dummy conductor is arranged avoiding the portion where the groove is to be formed in the semiconductor wafer, the arranged elements can be smoothly formed and the driven elements can be arranged in an orderly manner. In addition to this, the present invention can easily form a groove without the need to remove the dummy conductors by etching treatment on the semiconductor wafer, so that each driven element can be easily and highly accurately in accordance with the process rule. Can be divided into chips.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the driven element chip | tip which can manufacture a high quality driven element chip | tip easily, and a high quality driven element chip | tip, exposure apparatus, and image forming apparatus are realizable.

1 is a schematic diagram illustrating an overall configuration of an image forming apparatus. It is a basic diagram which shows the structure of an image forming unit. 1 is a schematic diagram illustrating a block configuration of an image forming apparatus. FIG. 2 is a schematic circuit diagram illustrating a circuit configuration of a print head. It is a basic diagram which shows the structure of a gate drive circuit. It is a basic diagram which shows the structure of a light emitting thyristor. It is a basic diagram which shows the light emission operation | movement of a print head. It is a basic diagram which shows the turn-on operation | movement of a light emitting thyristor. It is a basic diagram which shows the structure of a print head. It is a rough-line perspective view which shows the structure of a printed wiring board and a light emitting element chip. It is a basic diagram which shows attachment of the light emitting element chip | tip with respect to the printed wiring board in 1st Embodiment. It is a basic diagram which shows the structure of a light emitting element chip | tip. It is a basic diagram which shows the structure of the semiconductor wafer by 1st Embodiment. It is a basic diagram which shows formation of the groove | channel by DRIE method. It is a basic diagram which shows the time change of the gas supply amount in DRIE method. It is a basic diagram which shows the structure of a virtual semiconductor wafer. It is a basic diagram which shows the dicing by the blade of a cutter. It is a basic diagram which shows the structure of the semiconductor wafer by 2nd Embodiment. It is a basic diagram which shows attachment of the light emitting element chip | tip with respect to the printed wiring board in 2nd Embodiment. It is a basic diagram which shows the structure of the semiconductor wafer by 3rd Embodiment. It is a basic diagram which shows the structure of the semiconductor wafer by 4th Embodiment. It is a rough-line circuit diagram which shows the circuit structure of the light emitting element chip | tip by 5th Embodiment. It is a basic diagram which shows the structure of the semiconductor wafer by other embodiment. It is a rough-line circuit diagram which shows the circuit structure of the light emitting element chip | tip by other embodiment.

  Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[1. First Embodiment]
[1-1. Configuration of image forming apparatus]
As shown in FIG. 1, the image forming apparatus 1 according to the first embodiment is a so-called MFP (Multi Function Peripheral), and has a printer function for forming (that is, printing) an image on a sheet as a medium. It has a function as an image scanner for reading an image and a communication function. Therefore, the image forming apparatus 1 can operate as a printer, a copying machine (copying machine), a facsimile machine or the like by combining these functions. When the image forming apparatus 1 functions as a printer, a desired color image can be printed on a sheet P having a size such as A3 size or A4 size.

  In the image forming apparatus 1, various components are arranged inside a printer housing 2 formed in a substantially box shape. In the following description, the right end portion in FIG. 1 is defined as the front surface of the image forming apparatus 1, and the vertical direction, the horizontal direction, and the front-rear direction when viewed from the front are defined and described.

  The image forming apparatus 1 is configured to perform overall control by the control unit 3. The control unit 3 is connected to a host device (not shown) such as a computer device wirelessly or by wire. The control unit 3 executes print processing for forming a print image on the surface of the paper P when image data representing an image to be printed is given from the host device and printing of the image data is instructed.

  A paper storage cassette 4 that stores paper P is provided at the bottom of the printer housing 2. A paper feeding unit 5 is provided in front of and above the paper storage cassette 4. The paper supply unit 5 includes a hopping roller 6 disposed on the front upper side of the paper storage cassette 4, a conveyance guide 7 that guides the paper P upward along the conveyance path W, and registration rollers 8 that face each other across the conveyance path W. And a pinch roller 9 and the like.

  The paper feeding unit 5 picks up and conveys the paper P stored in the paper storage cassette 4 while separating them one by one by appropriately rotating each roller based on the control of the control unit 3. The guide 7 is advanced forward and upward along the conveyance path W, and is then folded back and upward to come into contact with the registration roller 8 and the pinch roller 9. The rotation of the registration roller 8 is appropriately suppressed. By applying a frictional force to the paper P between the registration roller 8 and the pinch roller 9, a so-called skew is performed in which the side of the paper P is inclined with respect to the traveling direction. Correct and make the top and bottom edges side to side, then send it back.

  On the rear side of the registration roller 8 and the pinch roller 9, a conveyance path W is formed substantially along the front-rear direction, and the middle conveyance unit 10 is disposed below the conveyance path W. The middle conveyance unit 10 includes a conveyance belt 14 formed of an endless belt around a front roller 11 disposed on the front side, a rear roller 12 disposed on the rear side, and a lower roller 13 disposed on the lower side. It has been configured. In addition, an adsorption roller 15 is provided on the upper side of the front roller 11 at a position opposed to the conveyance belt 14.

  When a driving force is transmitted to a rear roller 12 from a predetermined belt drive motor (not shown), the middle conveyance unit 10 drives the conveyance belt 14 by rotating the rear roller 12 in the arrow R2 direction. Let As a result, the conveyor belt 14 travels the upper portion along the conveyance path W, that is, the portion stretched between the front roller 11 and the rear roller 12 in the backward direction. At this time, when the sheet P is delivered from the sheet feeding unit 5, the middle conveying unit 10 holds the sheet P together with the conveying belt 14 between the suction roller 15 and the front roller 11, and places the sheet P on the upper side of the conveying belt 14. In this state, the paper P is advanced backward as the conveyor belt 14 travels.

  Four image forming units 16C, 16M, 16Y and 16K are sequentially arranged from the rear side to the front side on the upper side of the middle conveyance unit 10 and on the opposite side of the middle conveyance unit 10 across the conveyance path W. ing. The image forming units 16C, 16M, 16Y, and 16K (hereinafter collectively referred to as the image forming unit 16) correspond to cyan (C), magenta (M), yellow (Y), and black (K), respectively. However, only the colors are different, and both are configured similarly.

  As shown in the schematic side view of FIG. 2, the image forming unit 16 includes an image forming unit 31, a toner cartridge 32, and a print head 33, and a transfer roller 17 disposed below the image forming unit 31. The conveying belt 14 is sandwiched between the two. Incidentally, the image forming unit 16 and each component constituting the image forming unit 16 have a sufficient length in the left-right direction according to the length in the left-right direction of the paper P (hereinafter also referred to as the main scanning direction). For this reason, many parts are relatively long in the left-right direction with respect to the length in the front-rear direction and the up-down direction, and are formed in an elongated shape along the left-right direction.

  The toner cartridge 32 contains toner as a developer, is disposed above the image forming unit 31, and is attached above the image forming unit 31. The toner cartridge 32 supplies the stored toner to the toner storage unit 34 of the image forming unit 31. In addition to the toner accommodating portion 34, the image forming portion 31 incorporates a supply roller 35, a developing roller 36, a regulating blade 37, a photosensitive drum 38, and a charging roller 39.

  The supply roller 35 is formed in a cylindrical shape having a central axis along the left-right direction, and an elastic layer made of a conductive urethane rubber foam or the like is formed on the peripheral side surface thereof. The developing roller 36 is formed in a cylindrical shape having a central axis along the left-right direction, and an elastic layer having elasticity, a surface layer having conductivity, and the like are formed on the peripheral side surface thereof. The regulating blade 37 is made of, for example, a stainless steel plate having a predetermined thickness, and a part thereof is brought into contact with the peripheral side surface of the developing roller 36 in a slightly elastically deformed state. The photosensitive drum 38 is formed in a cylindrical shape with the central axis extending in the left-right direction, and a thin-film charge generation layer and a charge transport layer are sequentially formed on the peripheral side surface so that the photosensitive drum 38 can be charged. . The charging roller 39 is formed in a cylindrical shape with the central axis extending in the left-right direction, and a conductive elastic body is coated on the peripheral side surface thereof, and the peripheral side surface is brought into contact with the peripheral side surface of the photosensitive drum 38. ing.

  Further, a static elimination light source 20 is provided at a position on the front lower side of the image forming unit 31 and upstream of the contact portion between the photosensitive drum 38 and the conveyance belt 14. The static elimination light source 20 is adapted to remove charged static electricity by irradiating the photosensitive drum 38 with predetermined light.

  The image forming unit 31 is supplied with a driving force from a drum motor (not shown) to rotate the supply roller 35, the developing roller 36, and the charging roller 39 in the direction indicated by the arrow R2 (counterclockwise in the drawing), and also to perform photosensitivity. The body drum 38 is rotated in the direction of arrow R1 (clockwise in the figure). Further, the image forming unit 31 applies a predetermined bias voltage to the supply roller 35, the developing roller 36, the regulating blade 37, and the charging roller 39 to charge each of them.

  The supply roller 35 attaches the toner in the toner accommodating portion 34 to the peripheral side surface by charging, and causes the toner to adhere to the peripheral side surface of the developing roller 36 by rotation. The developing roller 36 abuts the peripheral side surface against the peripheral side surface of the photosensitive drum 38 after excess toner is removed from the peripheral side surface by the regulating blade 37.

  On the other hand, the charging roller 39 contacts the photosensitive drum 38 in a charged state, thereby uniformly charging the peripheral side surface of the photosensitive drum 38. The print head 33 has a plurality of light emitting element chips arranged in a straight line along the left-right direction (details will be described later), and has a light emission pattern based on an image data signal supplied from the control unit 3 (FIG. 2). The photosensitive drum 38 is exposed by emitting light at predetermined time intervals. Thereby, an electrostatic latent image is formed on the peripheral side surface of the photosensitive drum 38 in the vicinity of the upper end thereof.

  Subsequently, the photosensitive drum 38 is rotated in the direction of the arrow R <b> 1 to bring the portion where the electrostatic latent image is formed into contact with the developing roller 36. As a result, toner adheres to the peripheral side surface of the photosensitive drum 38 based on the electrostatic latent image, and the toner image based on the image data is developed.

  The transfer roller 17 is positioned directly below the photosensitive drum 38, and the upper portion of the conveyance belt 14 is sandwiched between the vicinity of the upper end of the peripheral side surface and the vicinity of the lower end of the photosensitive drum 38. A predetermined bias voltage is applied to the transfer roller 17 and a driving force is supplied from a drum motor (not shown) to rotate in the direction of the arrow R2. As a result, the image forming unit 16 can transfer the toner image developed on the peripheral side surface of the photosensitive drum 38 to the paper P when the paper P is being transported along the transport path W.

  In this way, each image forming unit 16 advances backward while sequentially transferring and superimposing toner images of respective colors on the paper P conveyed from the front along the conveyance path W.

  A cleaning unit 19 is provided below the lower roller 13 in the middle conveyance unit 10 (FIG. 1). When the image forming process is performed, the cleaning unit 19 cleans the toner adhering to the conveyance belt 14 due to the conveyance failure of the paper P by scraping off the surface of the conveyance belt 14. As a result, in the middle transport unit 10, the toner adheres to the back surface of the next sheet P to be transported, that is, the surface facing downward in the transport path W and to which the toner image is not transferred, and is contaminated. The reflection can be prevented.

  A fixing unit 21 is provided in the vicinity of the rear end of the middle conveyance unit 10. The fixing unit 21 includes a heating roller 21 </ b> A and a pressure roller 21 </ b> B that are arranged to face each other with the conveyance path W interposed therebetween. The heating roller 21A is formed in a cylindrical shape with a central axis directed in the left-right direction, and a heater is provided inside. The pressure roller 21B is formed in a cylindrical shape similar to the heating roller 21A, and presses the upper surface against the lower surface of the heating roller 21A with a predetermined pressing force.

  The fixing unit 21 heats the heating roller 21A and rotates the heating roller 21A and the pressure roller 21B in predetermined directions based on the control of the control unit 3, respectively. As a result, the fixing unit 21 applies heat and pressure to the paper P received from the middle conveyance unit 10, that is, the paper P on which the four color toner images are transferred, to fix the toner, and further to the rear.

  A paper discharge unit 22 is disposed behind the fixing unit 21. The paper discharge unit 22 is configured by a combination of a guide for guiding the paper P, a plurality of transport rollers, and the like, like the paper supply unit 5. The paper discharge unit 22 rotates the respective conveyance rollers appropriately according to the control of the control unit 3, thereby conveying the paper P delivered from the fixing unit 21 rearward and upward and then folding it forward. It discharges to the discharge tray 2T formed on the upper surface.

  Further, paper sensors 25, 26, 27 and 28 for detecting the paper P are appropriately provided at a plurality of locations along the transport path W in the printer housing 2. The sheet sensor 25 and the like detect the presence or absence of the sheet P in the transport path W and notify the control unit 3 of the obtained detection result. In response to this, the control unit 3 appropriately controls the rotation of each conveyance roller, the travel of the conveyance belt 14 in the middle conveyance unit 10, and the like.

  Next, the block configuration of the image forming apparatus 1 will be described with reference to FIG. The control unit 3 receives a control signal S1 from a host device (not shown) such as a computer device, and starts a printing operation based on a print instruction included in the control signal S1.

  Specifically, the control unit 3 first determines whether or not the fixing unit 21 is within a predetermined temperature range by a fixing device temperature sensor 21C (FIG. 3) provided in the fixing unit 21 (FIG. 1). To do. At this time, if the temperature of the fixing unit 21 is less than this temperature range, the control unit 3 energizes and heats the heating roller 21A (FIG. 1) to adjust the temperature of the fixing unit 21 to this temperature range.

  The control unit 3 rotates the development / transfer process motor 44 through the driver 43 and operates the charging high-voltage power supply 41, thereby rotating the charging roller 39 and the like in the image forming unit 16 (FIG. 2). Charge.

  Further, the control unit 3 rotates the paper feed motor 46 via the driver 45 to rotate the hopping roller 6 and the like of the paper feed unit 5 (FIG. 1). The paper is sent out while being separated and conveyed along the conveyance path W. Further, the control unit 3 recognizes the position of the paper P, the state of conveyance, and the like based on the detection result obtained from the paper sensors 25 to 28 and adjusts the conveyance speed.

  On the other hand, the image processing unit 48 performs predetermined image processing on the image data supplied from the host device to generate image forming data for each page. Based on the detection result by the paper sensor 26, the control unit 3 sends a timing signal S3 to the image processing unit 48 when the paper P reaches a printable position, for example, immediately before the image forming apparatus 16K (FIG. 1). Send. The timing signal S3 includes a main scanning synchronization signal, a sub scanning synchronization signal, and the like.

  In response to this, the image processing unit 48 generates a video signal S2 obtained by separating the generated image forming data for each line, and transmits the video signal S2 to the control unit 3. The control unit 3 generates a print data signal S4 based on the video signal S2, and transmits it to the print head 33 of the image forming unit 16 (FIG. 2). As a result, the print head 33 emits light with a light emission pattern based on the image data, and an electrostatic latent image can be formed on the peripheral side surface of the photosensitive drum 38 line by line.

[1-2. Printhead circuit configuration]
[1-2-1. Connection of each part in the print head]
Next, regarding the circuit configuration of the print head 33, the connection of each part will be described with reference to FIG. The print head 33 as an exposure apparatus includes a plurality of light emitting thyristors LT (LT1, LT2,...), A plurality of flip-flops FF (FF1, FF2,...), And a plurality of gate drive circuits GD (GD1, GD2,. It is comprised by.

  Among these, each flip-flop FF and each gate drive circuit GD are provided in the shift register 33R. For convenience of explanation, a circuit constituted by a combination of each light emitting thyristor LT, flip-flop FF, and gate driving circuit GD is also referred to as a light emitting driving circuit LDC (LDC1, LDC2,...). Hereinafter, the gate drive circuit GD and the flip-flop FF are collectively referred to as a drive circuit.

  Incidentally, as will be described later, the shift register 33R is manufactured on a semiconductor wafer such as silicon using a known CMOS (Complementary Metal Oxide Semiconductor) structure. The shift register 33R can also be manufactured on a glass substrate using a well-known TFT (Thin Film Transistor) technique.

  On the other hand, the control unit 3 is provided with a drive control circuit 50 that drives and controls each light emission drive circuit LDC of the print head 33. The drive control circuit 50 is supplied with a DRV ON-P signal from the outside, and has a serial data terminal 50I for outputting various signals, a clock terminal 50CK, and a data terminal 50D.

  The drive control circuit 50 generates a clock signal SCK that is a rectangular wave having a predetermined clock frequency, and supplies this to the clock terminal 33CK of the print head 33 from the clock terminal 50CK. Further, the drive control circuit 50 generates a serial data signal SI corresponding to the image data, and supplies this to the serial data terminal 33I of the print head 33 from the serial data terminal 50I. Further, the drive control circuit 50 applies a potential obtained by inverting the supplied DRV ON-P signal to the data terminal 50D. The data terminal 50D is connected to the data terminal 33D of the print head 33.

  Incidentally, the print head 33 is supplied with a predetermined power supply voltage VDD from a power supply circuit (not shown) via a power supply terminal (not shown), and is connected to the ground via a ground terminal (not shown). Therefore, the print head 33 has five electrical connection lines to the outside, such as the drive control circuit 50 and a power supply circuit (not shown).

  On the other hand, in the print head 33, the clock terminal 33CK, the serial data terminal 33I, and the data terminal 33D are connected to the light emission drive circuit LDC. Among these, the clock terminal 33CK is connected to the clock input terminal of each flip-flop FF, and supplies the clock signal SCK supplied from the drive control circuit 50 to each flip-flop FF. Therefore, each flip-flop FF operates at a timing synchronized with the clock signal SCK.

  The serial data terminal 33I is connected to the input terminal D of the first stage flip-flop FF1. The output terminal Q of the flip-flop FF1 is connected to the input terminal D of the flip-flop FF2 at the next stage and to the input terminal Q of the gate drive circuit GD1. Therefore, the flip-flop FF1 generates an output signal SQ1 at a timing according to the clock signal SCK based on the serial data signal SI supplied from the serial data terminal 33I, and outputs the output signal SQ1 to the gate drive circuit GD1 and the next-stage flip-flop. Supply to FF2.

  Incidentally, the second and subsequent flip-flops FF (FF2, FF3,...) Follow the clock signal SCK based on the output signal SQ (SQ1, SQ2,...) Supplied from the output terminal Q of the preceding flip-flop FF. The output signals SQ (SQ2, SQ3,...) Are generated at the same timing, and are supplied to the gate drive circuit GD and the next-stage flip-flop FF, respectively. That is, each flip-flop FF sequentially shifts the serial data signal SI to the subsequent stage for each cycle of the clock signal SCK.

  Each gate drive circuit GD has an output terminal K connected to the cathode terminal of the light emitting thyristor LT and the data terminal 33D, and an output terminal G connected to the gate terminal of the light emitting thyristor LT. Further, the light-emitting thyristor LT is supplied with the power supply voltage VDD at the anode terminal.

[1-2-2. Configuration and basic operation of gate drive circuit]
On the other hand, the gate drive circuit GD (FIG. 4) has one input terminal Q and two output terminals G and K, as shown by symbols in FIG. This gate drive circuit GD has an electrical characteristic equivalent to that of the equivalent circuit 51 shown in FIG. The equivalent circuit 51 includes an inverter 52, PMOS transistors 53 and 54, and an analog switch 55. Among these, the analog switch 55 has a circuit configuration in which the source terminals and the drain terminals of the NMOS transistor and the PMOS transistor are connected in parallel. Hereinafter, one of the source terminal and the drain terminal is referred to as a first terminal, and the other is referred to as a second terminal.

  The input terminal Q is connected to the input terminal of the inverter 52 and the gate terminal of the analog switch 55 on the PMOS transistor side. The output terminal of the inverter 52 is connected to the gate terminal on the NMOS transistor side of the analog switch 55 and the gate terminal of the PMOS transistor 53.

  The source terminal of the PMOS transistor 53 is connected to a power supply circuit (not shown), and a predetermined power supply voltage VDD is supplied. The drain terminal of the PMOS transistor 53 is connected to the source terminal of the PMOS transistor 54. The drain terminal of the PMOS transistor 54 is connected to its own gate terminal, the output terminal G, and the first terminal of the analog switch 55. The second terminal of the analog switch 55 is connected to the output terminal K.

  With this configuration, when a high level signal is supplied to the input terminal Q, the gate drive circuit GD has the output signal of the inverter 52 at a low level and both the PMOS transistors 53 and 54 are turned on. The output signal SG output from G becomes high level. At this time, the analog switch 55 is turned off and electrically disconnects the first terminal and the second terminal. That is, the output terminal K is electrically disconnected from the output terminal G.

  In addition, when a low level signal is supplied to the input terminal Q of the gate drive circuit GD, the analog switch 55 is turned on to electrically connect the first terminal and the second terminal. That is, the output terminal K is electrically connected to the output terminal G. At this time, in the gate drive circuit GD, both the PMOS transistors 53 and 54 are turned off.

[1-2-3. Configuration and basic operation of light-emitting thyristor]
Next, the configuration and basic operation of the light emitting thyristor LT will be described. The light emitting thyristor LT as a driven element has a configuration similar to a general light emitting diode (LED), and functions as a so-called light emitting element that emits light when a current is supplied. The light emitting thyristor LT has three terminals such as an anode (A), a cathode (K), and a gate (G) as shown by a circuit symbol in FIG. The light emitting thyristor LT is a three-terminal switch element having a control electrode (that is, a gate terminal) whose threshold voltage or threshold current can be controlled from the outside.

  The light-emitting thyristor LT has a configuration in which a plurality of layers each formed of a plurality of materials having different properties are stacked, as shown in a schematic cross-sectional view in FIG. For example, the light emitting thyristor LT is manufactured by using a GaAs wafer base material and epitaxially growing a predetermined crystal on the upper side thereof by a well-known MO-CVD (Metal Organic-Chemical Vapor Deposition) method.

  Specifically, the light-emitting thyristor LT is formed by epitaxially growing a predetermined buffer layer or sacrificial layer (not shown) on a GaAs wafer substrate, and then adding an N-type layer 61 containing an N-type impurity in the AlGaAs substrate. Then, a P-type layer 62 formed by containing a P-type impurity and an N-type layer 63 containing an N-type impurity are sequentially stacked. Thus, the light emitting thyristor LT is first configured as a wafer having a three-layer structure of “NPN”.

  Next, in the light-emitting thyristor LT, a part of the uppermost N-type layer 63 is subjected to a well-known photolithography method, thereby selectively forming a P-type region 64 containing P-type impurities. The Further, the light emitting thyristor LT is subjected to a well-known dry etching method to form a predetermined groove portion. As a result, element isolation is performed and the light emitting thyristor LT is separated into each light emitting thyristor LT. In the light-emitting thyristor LT, a part of the lowermost N-type layer 61 is exposed in the above-described etching process, and a metal wiring is formed in the exposed region to form a cathode (K) electrode. Further, in the light emitting thyristor LT, an anode (A) electrode and a gate (G) electrode are formed on the P-type layer 62 and the P-type region 64, respectively.

  Note that the light-emitting thyristor LT can be manufactured by a method partially different from that in FIG. 6B, as shown in FIG. Specifically, the light-emitting thyristor LT has an “NPN” three-layer structure in which an N-type layer 61, a P-type layer 62, and an N-type layer 63 are sequentially stacked, as in the method shown in FIG. 6B. Configured as a wafer. Further, the light emitting thyristor LT is formed as a wafer having a four-layer structure of “PNPN” from the upper side by forming a P-type layer 65 containing a P-type impurity on the upper side of the N-type layer 63.

  Next, the light emitting thyristor LT is subjected to a known dry etching method to form a predetermined groove portion, and as a result, element isolation is performed. Similarly to the case of FIG. 6B, the light-emitting thyristor LT has a portion of the lowermost N-type layer 61 exposed in the above-described etching process, and metal wiring is formed in the exposed region. A cathode electrode is formed. Further, in the light-emitting thyristor LT, a part of the P-type layer 65 which is the uppermost layer is exposed to form an anode electrode, and a part of the P-type layer 62 is exposed to form a gate electrode.

  The light-emitting thyristor LT (FIGS. 6B and 6C) manufactured in this way has electrical characteristics equivalent to those of the equivalent circuit 66 shown in FIG. The equivalent circuit 66 has a configuration in which a PNP transistor 67 and an NPN transistor 68 are combined. That is, in the equivalent circuit 66, the emitter terminal of the PNP transistor 67 corresponds to the anode terminal of the light emitting thyristor LT, the base terminal of the NPN transistor 68 corresponds to the gate terminal of the light emitting thyristor LT, and the emitter terminal of the NPN transistor 68 corresponds to the light emitting thyristor LT. Corresponds to the cathode terminal. In the equivalent circuit 66, the collector terminal of the PNP transistor 67 is connected to the base terminal of the NPN transistor 68, and the base terminal of the PNP transistor 67 is connected to the collector terminal of the NPN transistor 68.

  With this configuration, when a predetermined power supply voltage is applied to the anode terminal and the potential of the cathode terminal is low and the potential of the gate terminal is high, the light emitting thyristor LT has a trigger current that flows between them. A current flows between the terminal and the cathode terminal, and a light emitting state is obtained. Further, in this light emitting state, the light emitting thyristor LT is turned off when the potential of the cathode terminal is increased to the same level as that of the anode terminal and the potential difference between the two disappears. Further, the light emitting thyristor LT is not in the light emitting state and remains in the light-off state because the trigger current does not flow even if a potential difference occurs between the anode terminal and the cathode terminal if the potential of the gate terminal is low. To do.

  The light-emitting thyristor LT is not limited to a structure in which an AlGaAs layer is formed on a GaAs wafer, and may be a material using, for example, GaP, GaAsP, AlGaInP, or the like. Alternatively, a film formed of the above material may be used.

[1-3. Print head firing]
[1-3-1. Basic light emission operation of light emission drive circuit]
First, basic operations of the gate driving circuit GD and the light emitting thyristor LT, which are part of the light emitting driving circuit LDC (FIG. 4), will be described. When the drive command signal DRV ON-P signal supplied from outside becomes low level, the drive control circuit 50 of the control unit 3 sets the data terminal 50D to high level, and the cathode terminal of the light emitting thyristor LT is substantially equal to the power supply voltage VDD. Set to potential.

  In the light emission drive circuit LDC, the potential difference between the anode and cathode terminals in the light emission thyristor LT is almost 0 [V], and so-called gate current is not generated, so the current Iout flowing into the data terminal 50D of the drive control circuit 50 is also almost 0 [A]. ]. As a result, in the light emission drive circuit LDC, the light emitting thyristor LT does not emit light (that is, is extinguished) and enters a non-light emitting state.

  On the other hand, in the drive control circuit 50, when the drive command signal DRV ON-P signal becomes high level, the data terminal 50D becomes low level, and a sufficient potential difference is generated between the power supply voltage VDD. Thus, in the light emission drive circuit LDC, a sufficient potential difference is generated between the anode and cathode terminals in the light emission thyristor LT.

  In this state, in the light emission drive circuit LDC, when the serial data signal SI supplied from the drive control circuit 50 is at high level, the output signal SQ of the flip-flop FF becomes high level at the timing according to the clock signal SCK. In response to this, in the light emission drive circuit LDC, the output terminal G of the gate drive circuit GD becomes high level, so that a trigger current is generated at the gate terminal of the light emission thyristor LT, and the light emission thyristor LT emits light (that is, lighted). It becomes a state.

  Incidentally, in the light emission drive circuit LDC, the current flowing through the cathode terminal of the light emission thyristor LT at this time becomes the current Iout flowing into the data terminal 50D of the drive control circuit 50. Therefore, the light emitting thyristor LT emits light with an amount of light emission corresponding to the magnitude of the current Iout.

  Thus, the light emission drive circuit LDC outputs the clock signal SCK only when the data terminal 50D is at low level and the serial data signal SI is at high level because the drive command signal DRV ON-P signal is at high level. The light emitting thyristor LT is in a light emitting state at the same timing, and in a non-light emitting state in other cases.

[1-3-2. Light emission in print head]
Next, the light emission operation in the print head 33 will be described with reference to the timing chart of FIG. Here, as in the case of FIG. 4, attention is paid to the eight light emission drive circuits LDC1 to LDC8, and a case is assumed in which each of these emits light.

  When the image forming apparatus 1 (FIG. 1) is turned on, the control unit 3 (FIG. 4) performs a reset process of the shift register 33R in the print head 33 as a preliminary operation. In this reset process, the drive control circuit 50 of the control unit 3 supplies the serial data signal SI as a low level, and supplies the clock signal SCK to the number of stages of the shift register 33R, that is, the number of flip-flops FF (in this case, 8). Generated) clock pulses. As a result, in the print head 33, the output signals SQ1 to SQ8 of the flip-flops FF in the shift register 33R all become low level.

  On the other hand, the drive control circuit 50 of the control unit 3 raises the serial data signal SI from the low level to the high level at a predetermined time t1 (FIG. 7) when the image data print command or the like is acquired from the host device, and thereafter At time t2, a first pulse CP1 having a relatively short pulse width is generated in the clock signal SCK. When the clock signal SCK rises to a high level, the flip-flop FF1 as the first stage of the shift register 33R takes in the serial data signal SI and raises the output signal SQ1 to a high level at a slightly later timing. Further, the drive control circuit 50 causes the serial data signal SI to fall from the high level to the low level at time t3 after time t2.

  When the output signal SQ1 rises to the high level in this way, the gate drive circuit GD (FIGS. 4 and 6) sets the output signal SG1 output from the output terminal G to the high level as described above, and sets the output terminal K to the high level. It is electrically disconnected from the output terminal G. As a result, the potential of the gate terminal of the light emitting thyristor LT1 rises.

  Subsequently, at time t4 (FIG. 7), the drive control circuit 50 sets the drive command signal DRV ON-P signal supplied from the outside to the high level, and accordingly sets the data terminal 50D to the low level. As a result, a potential difference is generated between the gate terminal and the cathode terminal of the light-emitting thyristor LT1, so that a trigger current flows between the two and the light-emitting thyristor LT1 is turned on (lighted) to enter a light-emitting state.

  At a time t5 when a predetermined light emission period TD1 has elapsed from this time t4, the drive control circuit 50 causes the drive command signal DRV ON-P signal supplied from the outside to become a low level, and the data terminal 50D is made high accordingly. Level. As a result, the potential difference between the anode terminal and the cathode terminal of the light-emitting thyristor LT1 is substantially 0 [V], so that no current flows between them, and the light-emitting thyristor LT1 is turned off (extinguished) to enter a non-light-emitting state.

  Here, the amount of light emitted from the light-emitting thyristor LT, that is, the intensity of the emitted light is mainly caused by the magnitude of the current flowing between the anode terminal and the cathode terminal. For this reason, in the image forming apparatus 1, by adopting a drive circuit having a constant current characteristic as the drive control circuit 50 (FIG. 4) of the control unit 3, the magnitude of the current Iout flowing through the data terminal 50D is maintained substantially constant. be able to. In this case, for example, in each light-emitting thyristor LT, even if there is some variation in the potential difference between the anode terminal and the cathode terminal, the magnitude of the drive current that flows can be made almost constant, so the amount of light emission is almost constant. Can be aligned.

  In addition, the drive control circuit 50 causes the light-emitting thyristor LT1 of the light-emitting drive circuit LDC1 to emit light by lowering the data terminal 50D to the low level at time t4 and to the high level at time t5. Therefore, if the data terminal 50D is kept at the high level at times t4 and t5, the drive control circuit 50 prevents the light emitting thyristor LT1 of the light emission driving circuit LDC1 from emitting light, that is, maintains the non-light emitting state. be able to. In this way, the drive control circuit 50 can control whether or not the light emitting thyristor LT1 of the light emission driving circuit LDC1 emits light by switching the data terminal 50D to a high level or a low level.

  Eventually, the drive control circuit 50 causes the clock signal SCK to rise again at time t6. At this time, since the serial data signal SI is at the low level, the flip-flop FF1 causes the output signal Q1 to fall to the low level at a slightly later timing from this time t6. On the other hand, the flip-flop FF2 at the next stage raises the output signal Q2 to high level because the high-level output signal Q1 is input to the input terminal D at time t6.

  Subsequently, at time t7, similarly to time t4, the drive control circuit 50 sets the drive command signal DRV ON-P signal supplied from the outside to a high level, and accordingly sets the data terminal 50D to a low level. As a result, a potential difference is generated between the gate terminal and the cathode terminal of the light-emitting thyristor LT2, so that a trigger current flows between the two and the light-emitting thyristor LT2 is turned on (lighted) to enter a light-emitting state.

  At a time t8 when a predetermined light emission period TD2 has elapsed from this time t7, the drive control circuit 50 makes the drive command signal DRV ON-P signal supplied from the outside become a low level in response to this, similarly to the time t5. Thus, the data terminal 50D is set to the high level. As a result, the potential difference between the anode terminal and the cathode terminal of the light-emitting thyristor LT2 is substantially 0 [V], so that no current flows between them, and the light-emitting thyristor LT2 is turned off (extinguished) to enter a non-light-emitting state.

  In this way, in the print head 33 (FIG. 4), the serial data signal SI is at a high level only for a short period from time t1 to time t3. Therefore, each time the clock signal SCK (FIG. 12) rises, each flip-flop FF1. While sequentially switching the output signals SQ1 to SQ8 of the FF8, only one of them is temporarily set to the high level and the other is set to the low level.

  Therefore, in the print head 33, if the potential of the data terminal 50D in the drive control circuit 50 is low level, the output signal SQ is high level among the light emitting thyristors LT1 to LT8 respectively corresponding to the output signals SQ1 to SQ8. Only the light-emitting thyristor LT that is formed can selectively emit light.

  With this configuration, when the light emitting thyristor LT is turned on (emits light), the print head 33 gives a gate current by applying a potential difference that biases the PN junction between the gate and the cathode of the light emitting thyristor LT in the forward direction. What is necessary is just to supply. In the print head 33, when the light emitting thyristor LT is left in the non-light emitting state, the potential difference between the gate and the cathode may be set to be equal to or less than the forward voltage, so that the potential difference is set to zero or the voltage is applied in the reverse direction. You can also

  In the print head 33, when the output signal SQ of the flip-flop FF is at a low level, the analog switch 55 is turned on in the equivalent circuit 51 (FIG. 6B) of the gate drive circuit GD, and the PMOS transistors 53 and 54 are turned on. Are turned off. Therefore, in the print head 33, no voltage is applied between the gate and the cathode of the light emitting thyristor LT, and no gate current is generated. Therefore, the light emitting thyristor LT can be maintained in an off state (non-light emitting state).

  In the print head 33, the light emission times TD (TD1, TD2,...) Of the respective light emitting thyristors LT (LT1, LT2,...) May be unified or different from each other. For example, in the print head 33, when the light emission efficiency of each light emitting thyristor LT varies, the light emission time TD is adjusted according to each light emission efficiency, so that a constant exposure energy can be obtained from each light emitting thyristor LT. You can also

[1-3-3. Light-emitting thyristor turn-on operation]
Next, the turn-on operation in the light emitting thyristor LT will be described in detail. FIG. 8A is a circuit diagram corresponding to FIG. 6A and shows only the light emitting thyristor LT. In the light emitting thyristor LT, an anode-cathode voltage Va, a gate-cathode voltage Vgk, an anode current Ia flowing through the anode terminal, and a gate current Ig flowing through the gate terminal are defined.

  8B is a circuit diagram in which the light-emitting thyristor LT is represented by an equivalent circuit 66 as in FIG. 6D. In FIG. 8B, the terminals corresponding to the anode terminal, the cathode terminal, and the gate terminal of the light emitting thyristor LT are simply referred to as an anode terminal (A), a cathode terminal (K), and a gate terminal (G), respectively. Among these, a predetermined power supply voltage VDD is applied to the anode terminal from a power supply circuit (not shown). The cathode terminal is connected to a data terminal D of a drive circuit (not shown) corresponding to the data terminal 50D of the drive control circuit 50 (FIG. 4).

  In the equivalent circuit 66, in addition to the voltages and currents defined in FIG. 8A, the voltage Vag corresponding to the voltage between the anode and the cathode in the light-emitting thyristor LT and the base current Ib flowing through the base terminal of the NPN transistor 68 are obtained. Define. The equivalent circuit 66 defines a cathode current Ik that flows through the emitter terminal of the NPN transistor 68 corresponding to the cathode terminal of the light emitting thyristor LT.

  Here, let us focus on the process in which the light-emitting thyristor LT is turned on (lighted), and consider the case where the gate terminal is at a high level in the equivalent circuit 66 of FIG. At this time, the data terminal D is assumed to be at a low level.

  In this case, in the equivalent circuit 66, a gate current Ig flowing from the gate terminal toward the cathode terminal is generated. This gate current Ig is generated in the forward direction between the PN junction between the gate and cathode in the light emitting thyristor LT (FIG. 8A), that is, between the emitter and base of the NPN transistor 68 in the equivalent circuit 66 (FIG. 8B). It will flow as current.

  In the equivalent circuit 66 of FIG. 8B, the gate current Ig corresponds to the base current Ib of the NPN transistor 68. For this reason, when this base current Ib flows, the NPN transistor 68 starts to shift to the ON state and generates a collector current at the collector terminal. In the equivalent circuit 66, since this collector current becomes the base current of the PNP transistor 67, the PNP transistor 67 is also turned on. The collector current generated at this time increases the base current Ib of the NPN transistor 68 and accelerates the transition of the NPN transistor 68 to the on state.

  On the other hand, in the equivalent circuit 66, after the PNP transistor 67 is completely turned on, the collector-emitter voltage of the PNP transistor 67, that is, the anode-cathode voltage Vag in the light-emitting thyristor LT decreases, and the gate terminal potential is reduced. Rises. Here, in the equivalent circuit 66, when the gate terminal potential becomes equal to or higher than the high level voltage of the data terminal D in the drive circuit (not shown), the gate current Ig flowing from the data terminal D to the gate terminal of the light emitting thyristor LT is substantially 0 [A ]. As a result, in the light emitting thyristor LT, the cathode current Ik having a magnitude substantially equal to the anode current Ia flows to the cathode terminal, and is completely turned on, that is, in the light emitting state.

  Here, when the relationship between the cathode current Ik (FIG. 8B) and the anode-cathode voltage Va (FIG. 8A) in the light emitting thyristor LT is graphed, a characteristic curve as shown in FIG. 8C is obtained. It can be expressed as U1. In FIG. 8C, the origin at coordinates (0, 0) represents a state in which the light-emitting thyristor LT is turned off, and the cathode current Ik is approximately 0 [A].

  When the light emitting thyristor LT starts to turn on, in the equivalent circuit 66, the cathode current Ik increases and eventually becomes the current Ikp. At the same time, in the equivalent circuit 66, since the potential of the cathode terminal decreases, the anode-cathode voltage Va increases and eventually reaches the voltage Vap. A point on the characteristic curve U1 represented by the coordinates (Ikp, Vap) at this time is defined as a characteristic point U1p. That is, the characteristic curve U1 has a characteristic of coordinates (Ikp, Vap) while drawing a curve with a relatively steep inclination angle from the origin (0, 0) at which the light-emitting thyristor LT started to turn on, as indicated by an arrow wu1. The point U1p is reached.

  In the equivalent circuit 66, when the voltage Vap is applied between the anode terminal and the cathode terminal, the gate current Ig flows. The gate current Ig is equal to the base current Ib of the NPN transistor 68. In FIG. 8C, the characteristic point U1p at which the anode-cathode voltage Va becomes the voltage Vap corresponds to the boundary between the off region RA and the on transition region RB in the cathode current Ik axis direction. The off region RA is a region where the light emitting thyristor LT is in a non-light emitting state. Further, the ON transition region RB is a region where the light emitting thyristor LT transitions from the non-light emitting state to the light emitting state.

  Subsequently, in the equivalent circuit 66, the cathode current Ik increases from the current Ikp to become the current Ikv, while the anode-cathode voltage Va decreases to become the voltage Vav. At this time, a point on the characteristic curve U1 represented by the coordinates (Ikv, Vav) is defined as a characteristic point U1v. This characteristic point U1v corresponds to the boundary between the on transition region RB and the on region RC with respect to the cathode current Ik axis direction. The ON region RC is a region where the light emitting thyristor LT is in a light emitting state. At this time, in the equivalent circuit 66, the gate current Ig is reduced to almost 0 [A], and is in a state substantially equivalent to the case where the data terminal D of the drive circuit (not shown) is disconnected from the gate terminal of the light emitting thyristor LT. ing.

  Eventually, in the equivalent circuit 66, as indicated by the arrow wu2, the cathode current Ik further increases from the current Ikv to the current Ike, and the anode-cathode voltage Va starts to rise again to become the voltage Vae. At this time, a point on the characteristic curve U1 represented by the coordinates (Ike, Vae) is defined as a characteristic point U1e. This characteristic point U1e is the final operating point when the light emitting thyristor LT is driven to emit light. At this time, in the light emitting thyristor LT, a current Ike that is equal to a driving current (corresponding to the current Iout in FIG. 4) supplied from a driving circuit (not shown) flows and emits light with a predetermined light intensity.

  FIG. 8D corresponds to FIG. 8C and represents a characteristic curve U2 in which the relationship between the cathode current Ik and the gate current Ig in the light-emitting thyristor LT is graphed. In the equivalent circuit 66, when the light emitting thyristor LT starts to turn on, the cathode current Ik increases and the gate current Ig also increases.

  Eventually, in the equivalent circuit 66, after the gate current Ig becomes the current Igp when the cathode current Ik becomes the current Ikp, the cathode current Ik continues to increase while the gate current Ig decreases. For this reason, the characteristic curve U2 is such that the characteristic point U2p peaks when the cathode current Ik becomes the current Ikp and the gate current Ig becomes the current Igp.

  As described above, the light-emitting thyristor LT monotonously increases the cathode current Ik in the turn-on operation, but alternately increases and decreases the anode-cathode voltage Va, and increases and decreases the gate current Ig. It is like that.

[1-4. Printhead configuration]
Next, the configuration of the print head 33 will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view of the print head 33. For convenience of explanation, FIG. 9 shows a state in which the print head 33 in FIG. 2 is half-rotated on the paper surface, that is, a state in which the vertical direction and the front-back direction are both reversed. Hereinafter, the upper direction in FIG. 9 is also referred to as an irradiation direction, and the lower direction is also referred to as a counter-irradiation direction.

  The print head 33 is configured around a base member 71. The base member 71 is formed in a flat rectangular parallelepiped shape or a plate shape having a short length in the front-rear direction and a shorter length in the vertical direction than the length in the left-right direction, and has sufficient strength. doing. A printed wiring board 72 is provided on the irradiation direction side (that is, the lower side) of the base member 71. Compared with the base member 71, the printed wiring board 72 has substantially the same length in the left-right direction and the front-rear direction, and is slightly shorter in the vertical direction. The printed wiring board 72 is made of, for example, glass epoxy resin, and predetermined circuit patterns are formed on the upper and lower surfaces.

  FIG. 10 shows a schematic perspective view and FIG. 11 shows a schematic cross-sectional view. On the irradiation direction side of the printed wiring board 72, for example, a large number of 26 light emitting element chips 73 are provided. Attached with the paste 74 in a state of being aligned in one row along the left-right direction. FIG. 11 is a cross-sectional view taken along line A1-A2 in FIG.

  The light emitting element chip 73 as a driven element chip is an epitaxial film that is elongated in the left-right direction and short in the up-down direction (that is, thin) on the surface in the irradiation direction (that is, the lower side) of the plate base 73B configured in a plate shape. 73F is attached. For convenience of explanation, in the following, the left-right direction is also referred to as an alignment direction, and the front-rear direction intersecting with the left-right direction is also referred to as a crossing direction.

  In the epitaxial film 73F as the element film, for example, a large number of light emitting thyristors LT such as 192 are formed in a state of being aligned in the left-right direction. The epitaxial film 73F is bonded to the surface of the chip base 73B (hereinafter also referred to as an arrangement surface) by, for example, an epitaxial film bonding method disclosed in Patent Document 1, and then the connection terminals provided on each of the epitaxial films 73F are photo-connected. By wiring using a lithography method, the chip base 73B is electrically connected. For convenience of explanation, the light-emitting thyristor LT is hereinafter also referred to as a driven element, and the plurality of light-emitting thyristors LT are also referred to as driven element groups.

  Thus, since 26 light emitting element chips 73 are arranged on the printed wiring board 72 and each light emitting element chip 73 is provided with 192 light emitting thyristors LT, a total of 4992 light emitting thyristors LT are provided. ing. In addition, the print head 33 (FIGS. 2 and 4) has, for example, a length in the left-right direction substantially equal to the length of the short side (210 [mm]) in the A4 size, and 4992 pieces within this length range. The light emitting thyristors LT are arranged at equal intervals. Accordingly, the print head 33 can generate an electrostatic latent image having a resolution of 600 [dpi] on the peripheral side surface of the photosensitive drum 38 (FIG. 2).

  Incidentally, in the print head 33, from the viewpoint of generating an electrostatic latent image having a constant resolution, the interval between the adjacent light emitting thyristors LT at the boundary portion of each light emitting element chip 73 is set within one light emitting element chip 73. It is desirable to make it equal to the interval between the light emitting thyristors LT. For this reason, in each light emitting element chip 73, the distance from the left and right ends of the chip base 73B to the light emitting thyristor LT located on the most end side in the left and right is extremely short in the left-right direction.

  Further, the drive control circuit 50 (FIG. 4) described above has 192 light emission drive circuits LDC provided in one light emitting element chip 73 as one group, and each light emission drive circuit LDC in this group is sometimes assigned. Each of them is driven by division. For this reason, the control unit 3 is provided with 26 drive control circuits 50 that are the same number as the light emitting element chips 73, and each drive control circuit 50 is connected in parallel to each light emitting drive circuit of each light emitting element chip 73. Each LDC is driven. However, in FIG. 4, only one drive control circuit 50 is shown for convenience of explanation, and the others are omitted.

  A plurality of terminal pads are provided on the surface of each light emitting element chip 73 (FIG. 10) on the irradiation direction side (that is, the lower side), and a plurality of bonding wires 75 between the terminal pads and the printed wiring board 72 are electrically connected. Connected.

  Further, in the print head 33 (FIG. 4), the base member 71 and the printed wiring board 72 described above are attached to the holder 76. The holder 76 as a whole has a shape obtained by removing a side surface on the side opposite to the irradiation direction from a hollow rectangular column formed along the left-right direction, and its cross section is inverted upside down from the uppercase letter “U”. The shape is such that the side opposite to the irradiation direction is opened.

  A support portion 76 </ b> A that supports the printed wiring board 72 is formed on the inner surface of the holder 76 on the irradiation direction side. The print head 33 is inserted in a state where the printed wiring board 72 and the base member 71 are overlapped in the holder 76 when the print head 33 is manufactured, and clamp members 77 and 78 are attached. The clamp members 77 and 78 are both made of metal, and are fixed in a state where the irradiation direction surface of the printed wiring board 72 is in contact with the support portion 76 </ b> A of the holder 76 through the base member 71 by the action of elastic force. . As a result, the positional relationship between the light emitting element of the light emitting element chip 73 attached to the printed wiring board 72 and the holder 76 is determined.

  Further, an attachment hole 76H that is an elongated long hole extending in the left-right direction and penetrates in the vertical direction is formed near the center of the irradiation direction side portion of the holder 76, and the rod lens array 79 is attached to the attachment hole 76H. The rod lens array 79 has a configuration in which a plurality of minute lenses having optical axes along the vertical direction are arranged in the horizontal direction, and the focus of each lens is adjusted to each light emitting thyristor LT of the light emitting element chip 73. As such, the mounting position is fixed in an adjusted state.

[1-5. Configuration of light-emitting element chip]
Next, the configuration of the light emitting element chip 73 will be described. As shown in the schematic plan view of FIG. 12, the light emitting element chip 73 is generally configured in a rectangular shape that is long in the X direction representing the horizontal direction in the figure and short in the Y direction representing the vertical direction in the figure. . For convenience of explanation, the direction toward the front of the page in FIG. 12 is referred to as the Z direction.

  The light-emitting element chip 73 is a so-called self-scanning type, and as described above, is mainly configured by a plate-shaped chip base 73B and a film-shaped epitaxial film 73F. The chip base 73B is a semiconductor whose main material is silicon, for example, and an epitaxial film 73F is attached to the chip base surface 73BS which is the surface on the irradiation direction side. In the chip base 73B, a plurality of conductive layers each having a predetermined circuit pattern formed of a conductive material are formed in a portion close to the chip base surface 73BS in the inside (details will be described later).

  The chip base 73B is formed in a rectangular shape as a whole when viewed from the Z direction, and the vicinity of the apex on the X direction side and the −Y direction side is in the range of about ½ of the long side and about 1 of the short side. It is cut out in a rectangular shape over a range of / 3 to about 1/4. That is, the chip base 73B has a long side on the Y direction side that is linear, whereas the −Y direction side is bent in a crank shape. For convenience of explanation, hereinafter, the length of the long side is referred to as length LX, the length of the short side of the longer side is referred to as length LY1, and the length of the shorter side is referred to as length LY2.

  The light emitting element chip 73 is provided with a light emitting element group 81 and a drive circuit group 82 as driven element groups. The light emitting element group 81 is 192 light emitting thyristors LT (FIG. 4) provided on the above-described epitaxial film 73F. The light-emitting thyristors LT constituting the light-emitting element group 81 are aligned and arranged linearly along the X direction and at equal intervals over almost the entire range of the chip base surface 73BS in the X direction.

  The drive circuit group 82 has a configuration in which drive circuits that drive the respective light emitting thyristors LT, that is, flip-flops FF and gate drive circuits GD (FIG. 4) are arranged linearly along the X direction. 4 corresponds to the shift register 33R. The chip base 73B includes a plurality of terminal pads 84 that function as electrodes, a micro via row 85 that connects circuit patterns between the chip base surface 73BS and other layers, and a light emitting element chip 73 that is adjacently disposed. A position mark 86 or the like is provided for aligning the positions.

[1-6. Manufacturing of light-emitting element chip]
Next, manufacture of the light emitting element chip 73 will be described. The light emitting element chip 73 is manufactured based on a semiconductor wafer 100 made of silicon or the like, as well as a well-known semiconductor chip and integrated circuit, as shown partially in FIG. 13A. The semiconductor wafer 100 is manufactured in a state in which a large number of light emitting element chips 73 are arranged using a known exposure technique, etching technique, or the like. Incidentally, the thickness of the semiconductor wafer 100, that is, the length in the Z direction is about 600 [μm], for example.

[1-6-1. Arrangement of each part on semiconductor wafer]
Specifically, in the semiconductor wafer 100, two light emitting element chips 73 are made into one set, one of which is half-rotated in the XY plane with respect to the other, and one portion protruding in the Y direction is cut out from the other. It is arranged so as to get into the part. For convenience of explanation, the two light emitting element chips 73 forming one set are hereinafter referred to as a light emitting element chip set 101. Incidentally, between the two light emitting element chips 73 forming the light emitting element chip set 101, a chip set gap 102 having a length dy0 is formed in the Y direction.

  In the semiconductor wafer 100, the light-emitting element chip sets 101 are arranged in a lattice pattern so as to be periodically arranged for each length PX in the X direction and periodically for each length PY in the Y direction. Here, in the semiconductor wafer 100, the light emitting element chip set 101 is formed in the Y chip region 103 in the Y direction, and the Y gap region 104 is formed between the Y chip regions 103. The length in the Y direction of the Y chip region 103 is equivalent to a value obtained by adding the lengths LY1, LY2, and dy0. The length dy1 of the Y gap region 104 is substantially equal to the length dy0 of the chip assembly gap 102. Incidentally, the length PY is an added value of the lengths LY1, LY2, dy0, and dy1.

  On the other hand, in the semiconductor wafer 100, in the X direction, the light emitting element chip set 101 is formed in the X chip region 105, the X margin region 106 is disposed between the X chip regions 105, and the X chip region 105 and X gap regions 107 are formed between the X margin regions 106, respectively.

  The length of each part in the X direction in the semiconductor wafer 100 is such that the X chip region 105 has the same length LX as the light emitting element chip 73 (FIG. 12), and the X margin region 106 is sufficiently shorter than the length LX. The length cx, and the X gap region 107 has a length dx substantially equal to the lengths dy0 and dy1.

  Further, as shown in FIG. 13B, the semiconductor wafer 100 has a plurality of conductive layers formed in a portion close to the chip base surface 73BS in a part of the B1-B2 cross-sectional view in FIG. Yes. Specifically, on the semiconductor wafer 100, the first conductive layer 111, the second conductive layer 112, and the third conductive layer 113 are sequentially stacked in the Z direction side with respect to the base layer 110 closest to the −Z direction side. In addition, a passivation protective film 114 is formed.

  Incidentally, a non-conductive insulating layer is formed between the first conductive layer 111 and the second conductive layer 112 and between the second conductive layer 112 and the third conductive layer 113, respectively. Similar to the base layer 110, the insulating layer is mainly composed of silicon.

  The first conductive layer 111, the second conductive layer 112, and the third conductive layer 113 (hereinafter collectively referred to as the conductive layer 120) are made of a conductive metal material such as aluminum (Al), for example. Thus, a predetermined circuit pattern (hereinafter also referred to as a wiring portion) connected to each light emitting thyristor LT and the like is formed.

  In addition, in the conductive layer 120, a plurality of dummy metals DM are appropriately disposed in a portion where a circuit pattern is not formed. The dummy metal DM as the dummy conductor is formed in, for example, a minute rectangular parallelepiped shape, is made of the same metal material as the circuit pattern, and has a length (that is, thickness) in the Z direction equal to that of the circuit pattern. Yes. The dummy metal DM is electrically separated from the circuit pattern.

  In the semiconductor wafer 100, for example, as shown in FIG. 18C, which is a schematic plan view of the third conductive layer 113, a plurality of dummy metals DM, for example, bricks and tiles, They are arranged in a lattice shape along the XY plane. However, in the semiconductor wafer 100, the dummy metals DM are arranged so that the positions of the gaps between the dummy metals DM differ by half a period, that is, in a so-called staggered pattern, for each row along the Y direction. Yes.

  In the semiconductor wafer 100, a plurality of dummy metals DM are also arranged in a substantially lattice pattern in the second conductive layer 112 and the first conductive layer 111, as in the third conductive layer 113. However, in the semiconductor wafer 100, as shown in FIG. 13B, generally, the gap between the dummy metals DM is set between the adjacent conductive layers 120 in the X direction or the Y direction as in the case where bricks are stacked. Each dummy metal DM is arranged so as to be shifted by half a period in the direction.

  Further, in the semiconductor wafer 100, as shown in FIGS. 18B and 18C, in each conductive layer 120, specifically, a chip assembly gap 102 and a Y gap are provided at the boundary of each light emitting element chip 73. The dummy metal DM is not arranged in the region 104 and the X gap region 107. In other words, in the semiconductor wafer 100, the dummy metal DM is disposed in each conductive layer 120 so as to avoid the formed circuit pattern and the chip assembly gap 102, the Y gap area 104, and the X gap area 107. . In addition, the semiconductor wafer 100 is arranged so that the side surfaces of the dummy metal DM are aligned with the boundary between the X chip region 105 and the X gap region 107 in the X direction. Therefore, in the semiconductor wafer 100, if the inside of the X gap region 107 traces in the −Z direction from the surface, each conductive layer 120 does not collide with the metal material, and along the side surface of the dummy metal DM. It progresses in the material which has as a main component.

[1-6-2. Dicing of light emitting element chip]
Next, a process of dividing the semiconductor wafer 100 into a plurality of light emitting element chips 73 (that is, dividing into pieces) will be described. In the present embodiment, by combining the technique disclosed in Patent Document 2 and the detailed report disclosed in Patent Document 3, the individual light-emitting element chips 73 are separated using the etching process. .

JP 2004-193241 A (FIG. 3 etc.) JP 2004-296474 A (FIG. 3 etc.)

  Specifically, the semiconductor wafer 100 first uses a well-known exposure technique, etching technique, etc., so that the flip-flop FF, the gate drive circuit GD of the shift register 33R (FIG. 4), each circuit pattern, the dummy metal DM, etc. It is formed. In addition, an epitaxial film 73F in which a light emitting thyristor LT or the like is formed by a technique disclosed in Patent Document 1 is attached to the chip base 73B, and both terminals are wired by a photolithography method. That is, the light emitting element chip 73 is a composite chip having both the light emitting element and the driving element.

  Next, the semiconductor wafer 100 has a portion that becomes a boundary of each light emitting element chip 73 from the Z direction side to the depth of about 300 [μm] in the −Z direction, that is, the chip assembly gap 102, the Y gap area 104, and the X gap area 107. Grooves are formed in (FIG. 13A and the like). At this time, the semiconductor wafer 100 has grooves formed by a technique called a DRIE (Deep Reactive Ion Etching) method, which is a kind of etching process, instead of using, for example, a cutter that rotates a thin disk-shaped blade at high speed. The In this DRIE method, a groove is formed by using two types of processes such as “etching mode” and “passivation mode”.

  Incidentally, a resist film is previously formed on the semiconductor wafer 100 by a known photolithography method or the like, except for a portion that becomes a boundary between the light emitting element chips 73 (that is, the X gap region 107 and the like, hereinafter also referred to as a chip boundary portion). Has been. The semiconductor wafer 100 is installed between parallel plate electrodes in a chamber of an RIE apparatus (not shown).

In the etching mode, as schematically shown in FIG. 14A corresponding to FIG. 13B, SF ₆ (sulfur fluoride gas) is supplied into the chamber, and this SF ₆ is ionized and turned into plasma. The Thereby, in the semiconductor wafer 100, the surface of silicon (Si) is scraped by radicalized F + ions at the bottom portion of the chip boundary portion 122 where the resist film 121 is not formed, and is discharged as SiF ₄ .

  At this time, in the semiconductor wafer 100, since the dummy metal DM is not disposed at the chip boundary portion 122 at the depth corresponding to each conductive layer 120 (FIG. 13C), the dummy metal DM is obstructed. The groove can be deepened in the −Z direction by the progress of etching. Further, in the semiconductor wafer 100, radicalized F + ions do not react with the metal material constituting each conductive layer 120. Therefore, when the side surface of the dummy metal DM is exposed at the side surface portion of the chip boundary portion 122 in the conductive layer 120. , The progress of etching in the X direction and the Y direction is stopped. As a result, the semiconductor wafer 100 is etched so that the bottom portion of the chip boundary portion 122 is cut off and the side of the dummy metal DM is used as the inner side of the groove, and the groove is deeply dug.

On the other hand, in the passivation mode, a C ₄ F ₈ gas is supplied into the chamber, as schematically shown in FIG. 14B corresponding to FIG. As a result, in the semiconductor wafer 100, a fluorocarbon deposition layer 123, which is a polymeric substance, is generated on the surface (that is, the inner surface) of the groove.

Further, in the DRIE method, as shown in FIG. 15, the supply amount of each gas according to the passage of time is alternately repeated between an etching mode in which SF ₆ is supplied and a passivation mode in which C ₄ F ₈ is supplied. It is. As a result, in the semiconductor wafer 100, the deepening of the groove by the etching mode and the protection of the surface of the groove by the passivation mode are repeated alternately, and a groove having a sufficient depth is formed in the chip boundary portion 122 eventually.

  Thereafter, a predetermined adhesive film is attached to the front surface side (that is, the Z direction side) of the semiconductor wafer 100, and the opposite side (that is, the −Z direction side) is ground to follow the chip boundary portion 122. It is divided into a plurality of light emitting element chips 73, that is, in a diced state.

  As shown in FIG. 14, the light-emitting element chip 73 diced in this manner is in a state in which the side surface portion of the dummy metal DM is exposed on the side surfaces on the X direction side and the −X direction side. In the side surface portion of the dummy metal DM (hereinafter also referred to as a chip substrate side surface), the side surface portion when the dummy metal DM is formed by the process processing in the semiconductor wafer 100 is exposed as it is.

  Incidentally, the dicing is performed on the semiconductor wafer 100, and in addition to the plurality of light emitting element chips 73, the remaining chip 108 (FIG. 13A) is also divided from the Y chip area 103 and the X remaining area 106. Is done.

[1-7. Operation and effect]
In the above configuration, in the first embodiment, the light emitting element chip 73 mounted on the print head 33 of the image forming apparatus 1 is manufactured by a semiconductor process based on the semiconductor wafer 100 (FIG. 13).

  Here, as shown in FIGS. 16 (A), (B), and (C) corresponding to FIGS. 13 (A), (B), and (C), for comparison with the present embodiment, virtual A light-emitting element chip 173 and a virtual semiconductor wafer 200 used for manufacturing the light-emitting element chip 173 are assumed. Note that FIG. 16B is a cross-sectional view taken along line C1-C2 in FIG.

  Although the semiconductor wafer 200 is configured in many parts in the same manner as the semiconductor wafer 100, the X margin region 106 and the X gap region 107 are not provided, and an X margin region 206 is formed instead. ing. Further, in the semiconductor wafer 200, as shown in FIG. 16C, the dummy metal DM is continuously arranged without leaving a boundary between the X chip region 105 and the X margin region 206 in the X direction. .

  In the semiconductor wafer 200, grooves are formed in the chip assembly gap 102 and the Y gap area 104 by etching. On the other hand, as shown in FIG. 17, each light emitting element chip is cut by a cutter that rotates a thin disk-shaped blade BD at high speed. A groove along the short side portion of 173 is formed. For this reason, in the semiconductor wafer 200, the metal material forming the dummy metal DM can be cut in addition to silicon by the cutter. However, in the semiconductor wafer 200, the cutter blade BD may sway in the direction of the surface of the disk, that is, in the X direction. This reduces the accuracy of the position where the groove is formed in the X direction, and each light emission is divided. In the element chip 173, the distance from the short side to the light emitting thyristor LT may vary.

  Then, in the print head 33 on which the light emitting element chip 173 is mounted, the interval between the light emitting thyristors LT is not constant at the boundary portion between the light emitting element chips 173, and the image quality of the formed electrostatic latent image is greatly reduced. Fear arises. Further, since it is necessary to set a relatively large margin in the light emitting element chip 173, there is a possibility that the resolution of the electrostatic latent image cannot be increased.

  Furthermore, it is conceivable to form a groove on the semiconductor wafer 200 by the same DRIE method as that for the semiconductor wafer 100. However, in the semiconductor wafer 200, the dummy metal DM is continuously arranged over the X chip region 105 and the X margin region 206 in the X direction. For this reason, in the semiconductor wafer 200, it is necessary to perform etching by switching to a gas corresponding to the metal material, and it is necessary to form a resist film corresponding to this gas in advance. There is a risk of a sudden rise.

  On the other hand, in the semiconductor wafer 100 according to the present embodiment, the dummy metal DM is not disposed in the X gap region 107 or the like that becomes the boundary between the light emitting element chips 73 (FIG. 13). Therefore, in the semiconductor wafer 100, it is not necessary to remove the metal material by etching by the DRIE method, and a groove having a sufficient depth can be formed with a relatively small number of steps (FIGS. 14 and 15).

  In particular, in the semiconductor wafer 100, the groove on the short side portion of each light emitting element chip 73 can be formed by etching with a positional accuracy according to a semiconductor process rule (for example, 0.35 [μm]). For this reason, in the light emitting element chip 73 manufactured from the semiconductor wafer 100, the distance from the light emitting thyristor LT positioned at the left and right ends to the short side can be adjusted to the design value with extremely high accuracy. Thereby, in the print head 33 (FIGS. 9 to 11 and the like) on which the light emitting element chip 73 is mounted, it is possible to generate an extremely high quality electrostatic latent image in which the intervals between the pixels are accurately aligned. . Further, the image forming apparatus 1 on which the print head 33 is mounted can form an extremely high quality image.

  In the semiconductor wafer 100 (FIG. 13), grooves can be simultaneously formed in the chip assembly gap 102, the Y gap area 104, and the X gap area 107 by the DRIE method. For this reason, the light emitting element chip 73 has a simplified manufacturing facility and the number of processes compared to the case where grooves are formed on the semiconductor wafer 200 by using both etching and a cutter as in the case of the light emitting element chip 173. Can be reduced, and the manufacturing cost can be reduced and the time required for the manufacturing can be shortened.

  Further, in the semiconductor wafer 100, a dummy metal DM is disposed at a place where a circuit pattern is not formed, except for a part where grooves such as a chip assembly gap 102, a Y gap area 104, and an X gap area 107 are formed (FIG. 13). For this reason, in the light emitting element chip 73 manufactured based on the semiconductor wafer 100, the smoothness of the chip base surface 73BS can be remarkably improved, and the epitaxial film 73F can be adhered stably and accurately.

  In other words, the light emitting element chip 73 has a higher level of smoothing and etching of the chip base surface 73BS by arranging the dummy metal DM avoiding the X gap region 107 and the like serving as the boundary between the light emitting element chips 73. Forming the groove with positional accuracy can be achieved at a high level.

  According to the above configuration, in the image forming apparatus 1 according to the first embodiment, when the light emitting element chip 73 to be mounted on the print head 33 is manufactured, the semiconductor wafer 100 becomes a boundary between the light emitting element chips 73. The dummy metal DM was disposed avoiding the X gap region 107 and the like. For this reason, in the semiconductor wafer 100, a trench having a sufficient depth is formed with extremely high positional accuracy according to the process rule while suppressing the number of steps and the type of gas used by the DRIE method without the need to remove the metal material. it can. Thereby, the image forming apparatus 1 having the print head 33 on which the light emitting element chip 73 is mounted can form an extremely high quality image.

[2. Second Embodiment]
The image forming apparatus 301 (FIG. 1) according to the second embodiment is different from the image forming apparatus 1 according to the first embodiment in that it includes a print head 333 instead of the print head 33 (FIG. 2). However, the other points are similarly configured. The print head 333 is different from the print head 33 according to the first embodiment in that it has a light emitting element chip 373 instead of the light emitting element chip 73 (FIG. 9), but the other points are similarly configured. Has been.

  The light emitting element chip 373 is manufactured based on a semiconductor wafer 400 instead of the semiconductor wafer 100 as shown in FIGS. 18A and 18B corresponding to FIGS. 13A and 13B, respectively. Incidentally, FIG. 18B is a cross-sectional view along D1-D2 in FIG. The semiconductor wafer 400 is configured in substantially the same manner as the semiconductor wafer 100, but the X gap region 107, the X gap region 407 instead of the first conductive layer 111 and the second conductive layer 112, the first conductive layer 411 and the second conductive layer The difference is that the conductive layer 412 is provided.

  As with the second conductive layer 112 (FIG. 13) according to the first embodiment, the second conductive layer 412 is formed with a predetermined circuit pattern, and avoids the circuit pattern, the X gap region 407, and the like. A dummy metal DM is arranged. However, in the second conductive layer 412, as compared with the first conductive layer 111 located on the irradiation direction side, the boundary line between the X chip region 105 and the X gap region 407, that is, the side surface portion of the dummy metal DM is the light emitting element chip. 373 is shifted from the center side. In other words, in the second conductive layer 412, the width (length) of the X gap region 407 in the X direction is larger than the length dx in the first conductive layer 111.

  Further, the first conductive layer 411 is arranged such that the boundary line between the X chip region 105 and the X gap region 407, that is, the side surface portion of the dummy metal DM is shifted toward the center side of the light emitting element chip 373 than the second conductive layer 412. Has been. That is, in the third conductive layer 413, the width (length) of the X gap region 407 in the X direction is a length dx2 that is further expanded as compared with the second conductive layer 412. In other words, as shown in FIG. 18B, the X gap region 407 forms a trapezoidal outline that has a shorter irradiation direction side and a longer anti-irradiation direction side.

  For this reason, when a groove is formed in the semiconductor wafer 400 by the DRIE method, the anti-irradiation direction with respect to the irradiation direction side with respect to the X direction depends on the arrangement of the dummy metal DM in the second conductive layer 412 and the first conductive layer 411. A wider groove is formed on the side. As a result, the light emitting element chip 373 diced from the semiconductor wafer 400 has a reverse trapezoidal shape in which the side opposite to the irradiation direction is shorter than the irradiation direction side, as shown in a schematic cross-sectional view in FIG. 19 corresponding to FIG. It becomes.

  For this reason, in the print head 333 on which the light emitting element chip 373 is mounted, a gap having a sufficient volume between the light emitting element chips 373 while sufficiently narrowing the interval between the light emitting thyristors LT at the boundary portion of each light emitting element chip 373. Can be formed. Thereby, in the print head 333, even if the amount of the paste 74 applied to the printed wiring board 72 is excessive, a part of the paste 74 crawls up the gap between the light emitting element chips 373 toward the irradiation direction and emits light. It is possible to prevent the occurrence of a problem such as covering the thyristor LT.

  In other respects, the light-emitting element chip 373 and the print head 333 according to the second embodiment, and the image forming apparatus 301 on which these are mounted can achieve the same functions and effects as those of the first embodiment.

  According to the above configuration, in the second embodiment, when the light emitting element chip 373 is manufactured, the side surface portion of the dummy metal DM that becomes the boundary line between the X chip region 105 and the X gap region 407 in the semiconductor wafer 400. Was arranged so as to shift toward the center side of the light emitting element chip 373 as it proceeded to the −Z direction side. For this reason, in the semiconductor wafer 400, it is not necessary to remove the metal material by the DRIE method, and the depth and the bottom of the semiconductor wafer 400 are sufficiently deep with extremely high positional accuracy according to the process rule while suppressing the number of steps and the type of gas used. A groove having a wide side can be formed. Thereby, in the print head 333 on which the light emitting element chip 373 manufactured based on the semiconductor wafer 400 is mounted, the possibility that the paste 74 can creep up and cover the light emitting thyristor LT can be remarkably reduced. High quality images can be formed.

[3. Third Embodiment]
The image forming apparatus 501 (FIG. 1) according to the third embodiment is different from the image forming apparatus 1 according to the first embodiment in that a print head 533 is substituted for the print head 33 (FIG. 2). However, the other points are similarly configured. The print head 533 differs from the print head 33 according to the first embodiment in that it has a light emitting element chip 573 instead of the light emitting element chip 73 (FIG. 9), but the other points are similarly configured. Has been.

  The light emitting element chip 573 is manufactured based on a semiconductor wafer 600 that replaces the semiconductor wafer 100 as shown in FIGS. 20A and 20B corresponding to FIGS. 13A and 13B, respectively. 20B is a cross-sectional view taken along line E1-E2 in FIG. The semiconductor wafer 600 is configured in the same manner as the semiconductor wafer 100, but is different in that a LOCOS (Local Oxidation of Silicon) film 615 is provided between the base layer 110 and the first conductive layer 111. Yes.

  The LOCOS film 615 is an oxide film that is sufficiently thick (that is, the length in the Z direction is long) compared to the first conductive layer 111 and the like. Further, in the semiconductor wafer 600, a LOCOS film gap 616 in which the LOCOS film 615 is omitted is formed at a position corresponding to the X gap area 107.

  The LOCOS film gap 616 gradually increases as the thickness of the LOCOS film 615 approaches the X gap area 107 at the boundary between the X gap area 107 and the X chip area 105 and the X margin area 106 adjacent thereto. It is formed to be thin. Incidentally, since this portion of the LOCOS film 615 has a shape similar to the “bird's beak” in FIG. 20B, it is also called a “bird's beak” portion.

  The LOCOS film gap 616 has a length dx3 longer than the length dx of the X gap area 107 in the X direction. For this reason, the semiconductor wafer 600 has a sufficient depth so as to penetrate the LOCOS film gap 616 in the −Z direction without switching to a dedicated gas corresponding to the LOCOS film 615 when grooves are formed by the DRIE method. Grooves can be formed.

  In other respects, the light-emitting element chip 573 and the print head 533 according to the third embodiment, and the image forming apparatus 501 equipped with them can achieve the same functions and effects as those of the first embodiment.

  According to the above configuration, in the third embodiment, when manufacturing the light emitting element chip 573, the LOCOS film 615 is formed between the base layer 110 and the first conductive layer 111 in the semiconductor wafer 600, and A LOCOS film gap 616 was formed at a location corresponding to the X gap area 107. For this reason, in the semiconductor wafer 600, it is not necessary to remove the metal material or the LOCOS film 615 by the DRIE method, and the depth is sufficiently high with extremely high positional accuracy according to the process rule while suppressing the number of steps and the type of gas to be used. Can be formed. Thus, the print head 533 on which the light emitting element chip 573 manufactured based on the semiconductor wafer 600 is mounted can form an extremely high quality image by the image forming apparatus 501.

[4. Fourth Embodiment]
The image forming apparatus 701 (FIG. 1) according to the fourth embodiment is different from the image forming apparatus 1 according to the first embodiment in that it includes a print head 733 instead of the print head 33 (FIG. 2). However, the other points are similarly configured. The print head 733 differs from the print head 33 according to the first embodiment in that it has a light emitting element chip 773 instead of the light emitting element chip 73 (FIG. 9), but the other points are similarly configured. Has been.

  The light emitting element chip 773 is a semiconductor that replaces the semiconductor wafer 100 as shown in FIGS. 21A and 21B corresponding to FIGS. 13A and 13B, FIGS. 20A and 20B, respectively. Manufactured based on the wafer 800. Incidentally, FIG. 21B is an F1-F2 cross-sectional view in FIG. Although this semiconductor wafer 800 is configured substantially in the same manner as the semiconductor wafer 100, a LOCOS film 815 is provided between the base layer 110 and the first conductive layer 111, as in the third embodiment. Is different.

  Similar to the LOCOS film 615 in the third embodiment, the LOCOS film 815 is an oxide film that is sufficiently thick (that is, the length in the Z direction is long) compared to the first conductive layer 111 and the like. However, in the semiconductor wafer 800, unlike the third embodiment, the LOCOS film 815 is formed at a position corresponding to the X gap region 107, while the dummy metal DM of the X chip region 105 and the X margin region 106 is formed. A LOCOS film gap 816 in which the LOCOS film 815 is omitted is formed at a position corresponding to the disposed portion.

  Incidentally, in the light emitting element chip 773, the length of the X gap region 107 is the length dx in the X direction, whereas the portion of the LOCOS film 615 that is relatively thick (that is, the length in the Z direction is sufficiently long). Is equal to the length dx. Therefore, in the light emitting element chip 773, the length of the LOCOS film 815 including the bird's beak portion is longer than the length dx.

  In the semiconductor wafer 800, a dummy metal DM is disposed in a portion adjacent to the X gap region 107 in the X chip region 105 and the X margin region 106 as in the semiconductor wafer 100 (FIG. 13 and the like) according to the first embodiment. On the other hand, the dummy metal DM is not formed in the X gap region 107. As a result, on the upper surface of the semiconductor wafer 800, the X gap region 107 is depressed below the periphery thereof, and good smoothness cannot be obtained, and the epitaxial film 73F (FIG. 10 and the like) cannot be stably attached. There was sex.

  Therefore, in the semiconductor wafer 800, the LOCOS film 815 is provided instead of the dummy metal DM in the portion corresponding to the X gap region 107, so that the upper surface can be prevented from being depressed downward, and the smoothness of the upper surface is improved. Can do.

  In general, in a semiconductor wafer, a place where a wiring member (for example, aluminum) for connecting each transistor element or the like is arranged except for a place where a transistor element or the like constituting a flip-flop FF or a gate drive circuit GD (FIG. 4) is formed. Then, a LOCOS film is formed. Thereby, in the semiconductor wafer, a parasitic transistor is formed below the wiring member, that is, each circuit is prevented from operating as designed in the cut-out light emitting element chip. In other words, in a general semiconductor wafer, after the lower base layer is formed, a LOCOS film is partially formed on the upper side, and a conductive layer is further formed on the upper side. The

  For this reason, in the semiconductor wafer 800 according to the present embodiment, compared to the case of a general semiconductor wafer, at the time of manufacturing the LOCOS film, in addition to the portion corresponding to the wiring member, the portion corresponding to the X gap region 107 is also provided. What is necessary is just to change the shape of a mask pattern, etc. partially so that it may form. In other words, the semiconductor wafer 800 is equivalent to a general semiconductor wafer, the semiconductor wafer 100 according to the first embodiment, and the like, and it is not necessary to add a layer or a film by adding a manufacturing process. The LOCOS film 815 can be easily manufactured at the same cost by the manufacturing process.

By the way, as described above, the LOCOS film is made of a material centered on silicon, like the base layer 110 and the like and each insulating layer. For this reason, when the DRIE method (FIG. 14) described above is performed, the LOCOS film requires more time than the base layer 110 and each insulating layer when SF ₆ (sulfur fluoride gas) is used in the etching mode. However, the surface is shaved.

For this reason the semiconductor wafer 800, DRIE method (FIG. 14), without switching to another type of gas, by simply using the same SF ₆ the base layer 110 and the like and the insulating layer (sulfur hexafluoride gas), LOCOS The portion of the film 815 can also be etched, and a groove can be dug in the −Z direction.

  In other respects as well, the light emitting element chip 773 and the print head 733 according to the fourth embodiment, and the image forming apparatus 701 equipped with them can achieve the same operational effects as those of the first embodiment.

  According to the above configuration, in the fourth embodiment, when the light emitting element chip 773 is manufactured, in addition to the location where the wiring member is formed between the base layer 110 and the first conductive layer 111 in the semiconductor wafer 800. Then, a LOCOS film 815 is provided at a position corresponding to the X gap region 107. Therefore, in the semiconductor wafer 800, it is possible to form a groove having a sufficient depth with extremely high positional accuracy according to the process rule while improving the smoothness of the surface and suppressing the number of steps in the DRIE method and the type of gas used. Thus, the print head 733 on which the light emitting element chip 773 manufactured based on the semiconductor wafer 800 is mounted can form an extremely high quality image by the image forming apparatus 701.

[5. Fifth embodiment]
The image forming apparatus 901 (FIG. 1) according to the fifth embodiment is different from the image forming apparatus 1 according to the first embodiment in that it has a print head 933 instead of the print head 33 (FIG. 2). However, the other points are similarly configured. The print head 933 is different from the print head 33 according to the first embodiment in that it has a light emitting element chip 973 instead of the light emitting element chip 73 (FIG. 9), but the other points are similarly configured. Has been.

  The light emitting element chip 973 includes a plurality of flip-flops FF (FF1, FF2,...) And a plurality of gate drive circuits GD (GD1,. GD2,...) Are connected in the same manner as in the first embodiment. The light emitting element chip 973 is also provided with an anode common bus 988A, a cathode common bus 988K, and the like which are wirings for connecting to the anode terminal and the cathode terminal of each light emitting thyristor LT.

  The light emitting element chip 973 includes six terminal pads 984 (984A, 984K, 984SI, 984SCK, 984VDD, and 984VSS) and a number of micro vias 985 (985A1 to 985A192, 985K1 to 985K192, 985G1 to 985G192, and 985J1 to 985J4). )have. Incidentally, the light emitting element chip 973 is similar to the light emitting element chip 73 (FIG. 12) according to the first embodiment, and the terminal pads 984 and the respective portions corresponding to the terminal pads 84 and the microvia rows 85 on the upper surface thereof. Micro vias 985 are respectively disposed.

  Of these, the terminal pads 984A and 984K are connected to the common anode bus 988A and the common cathode bus 988K, respectively. Further, resistors 991, 992, and 993 are connected in series on the cathode pad 2008K closer to the terminal pad 984K than the portion where each gate drive circuit GD is connected.

  The terminal pad 984SI is connected to the input terminal D in the first-stage flip-flop FF1 via the buffer 989SI. The terminal pad 984SCK is connected to the clock terminal in each flip-flop FF1 via the buffer 989SCK. The terminal pad 984VDD is connected to a power supply terminal (not shown) of each element and is supplied with a power supply VDD voltage. The terminal pad 984VSS is connected to a ground terminal (not shown) of each element and is connected to the ground terminal of the printed wiring board 72 (FIG. 10).

  The micro vias 985A1 to 985A192 are connected to the anode terminals of the respective light emitting thyristors LT. The micro vias 985K1 to 985K192 are connected to the cathode terminals of the respective light emitting thyristors LT. The micro vias 985G1 to 985G192 are connected to the gate terminals of the respective light emitting thyristors LT.

  The micro vias 985J1, 985J2, 985J3, and 985J4 are connected to the terminal pad 984K side of the resistor 991, the resistors 991 and 992, the resistors 992 and 993, and the gate drive circuit GD side of the resistor 993, respectively. . The light emitting element chip 973 is appropriately selected from the micro vias 985J1 to 985J4 after the epitaxial film 73F (FIG. 10) is pasted as in the first embodiment, followed by a predetermined measurement operation in the thin film wiring process. These are connected by a predetermined jumper wiring. Thereby, in the light emitting element chip 973, the resistance value on the terminal pad 984K side in the cathode common bus 988K is adjusted.

  For this reason, in the print head 933 on which the light emitting element chip 973 is mounted, the characteristic impedance value of a connection cable (not shown) connecting to the control unit 3 (FIG. 3 etc.) and the equivalent of the light emitting element chip 973 etc. It is possible to achieve good signal transmission with less signal reflection by matching the impedance value.

  By the way, the light emitting element chip 973 is manufactured by a process or the like in a state aligned with the semiconductor wafer 100 (FIG. 13) as in the first embodiment, and an epitaxial film 73F (FIG. 10) is attached to each microchip. Vias 985 are appropriately connected by wiring or the like, and then separated by dicing. The separated light emitting element chips 973 are attached to the printed wiring board 72, and operations such as wire bonding are further performed. However, in the light emitting element chip 973, static electricity is unavoidable in the work such as wire bonding.

  Here, an object charged to a relatively large negative potential (for example, −100 [V]) comes into contact with the terminal pad 984A, and the relatively large negative charge is connected to the anode terminal of the light-emitting thyristor LT via the anode common bus 988A. It is assumed that the At this time, since the light emitting thyristor LT is not likely to be in the lighting condition, the supplied charge cannot be discharged, and the internal PN reverse connection, for example, the N-type layer 63 in FIG. The junction portion of the P-type layer 62 is broken down, resulting in an electrical failure.

  Therefore, in the light emitting element chip 973 according to the present embodiment, ESD (Electrostatic Discharge) protection units 995 (995A, 995K, 995SI and 995SCK). Incidentally, the ESD protection units 995K, 995SI, and 995SCK are all configured in the same manner as the ESD protection unit 995A. Therefore, hereinafter, the ESD protection unit 995A will be mainly described.

  The ESD protection unit 995A includes a PMOS transistor 996A and an NMOS transistor 997A, that is, a CMOS. The PMOS transistor 996A has a source terminal and a gate terminal connected to the power supply VDD, and a drain terminal connected to the anode common bus 988A. The NMOS transistor 997A has a source terminal and a gate terminal connected to the ground (that is, VSS), and a drain terminal connected to the anode common bus 988A.

  In the ESD protection unit 995A, when a signal having a potential of 0 to 5 [V] is supplied to the anode common bus 988A via the terminal pad 984A, both the PMOS transistor 996A and the NMOS transistor 997A are turned off. It does not affect the operation of the light emitting thyristor LT or the like.

  On the other hand, if a signal having a relatively large negative potential (eg, −100 [V]) is supplied to the anode common bus 988A via the terminal pad 984A, the ESD protection unit 995A turns on the NMOS transistor 997A. The current can flow from the drain terminal to the source terminal, that is, to the ground. At this time, in the light emitting element chip 973, since the threshold voltage in the NMOS transistor 997A is typically about 0.5 [V], the voltage applied to the anode terminal of each light emitting thyristor LT connected to the anode common bus 988A is set. It can be suppressed to about −0.5 [V].

  In addition, if a signal having a relatively large positive potential (for example, 100 [V]) is supplied to the anode common bus 988A via the terminal pad 984A, the ESD protection unit 995A causes the PMOS transistor 996A to transition to the on state. The current can flow from the drain terminal to the source terminal, that is, to the power supply VDD. At this time, in the light emitting element chip 973, the threshold voltage in the PMOS transistor 996A is typically about 0.5 [V], and therefore the voltage applied to the anode terminal of each light emitting thyristor LT connected to the anode common bus 988A is set. It can be suppressed to about 0.5 [V].

  Here, in the light emitting element chip 973, a parasitic circuit (not shown) having a predetermined impedance component is formed between the power supplies VDD and VSS by a circuit pattern formed inside. Therefore, in the light emitting element chip 973, a relatively large positive potential supplied to the power supply VDD and a relatively large negative potential supplied to the ground (VSS) can be discharged by this parasitic circuit.

  In the light emitting element chip 973, since each PMOS transistor 996 and each NMOS transistor 997 of each ESD protection unit 995 are CMOS, each flip-flop FF or each gate drive is used when a semiconductor wafer is manufactured by an exposure technique or an etching technique. These can be manufactured in parallel with the circuit GD. For this reason, in the light emitting element chip 973, a process for separately mounting each element of the ESD protection unit 995 is not necessary, and each element that can occur when the respective elements of the ESD protection unit 995 are mounted later is mounted. In principle, the problem that each light-emitting thyristor LT cannot be protected from static electricity or the like can be avoided in principle.

  In other respects as well, the light emitting element chip 973 and the print head 933 according to the fifth embodiment, and the image forming apparatus 901 mounted with these, can achieve the same operational effects as those of the first embodiment.

  According to the above configuration, in the fifth embodiment, the ESD protection unit 995A and the like are provided in the light emitting element chip 973. For this reason, in the print head 933, even if an object charged with a relatively large positive or negative potential contacts the terminal pad 984 A of the light emitting element chip 973 or the like in the manufacturing process or the like, this is treated as the power supply VDD or ground (VSS). The light emitting thyristor LT can be protected from destruction. Accordingly, the print head 933 on which the light emitting element chip 973 is mounted can form an extremely high quality image by the image forming apparatus 901.

[6. Other Embodiments]
In the first embodiment described above, the X direction in each conductive layer 120 is related to the boundary between the X chip region 105 and the X margin region 106 and the boundary between the X margin region 106 and the X gap region 107. The case where the positions of the side surfaces of the dummy metal DM are aligned with each other has been described (FIG. 13B). However, the present invention is not limited to this. For example, the positions of the side surfaces of the dummy metal DM in the X direction in each conductive layer 120 may be different from each other. In this case, it is sufficient that the dummy metal DM is not disposed at least in the X gap region 107. The same applies to the third to fifth embodiments.

  In the first embodiment described above, the case where the chip assembly gap 102, the Y gap area 104, and the X gap area 107 are simultaneously formed on the semiconductor wafer 100 by the DRIE method has been described. However, the present invention is not limited to this. For example, the grooves of the chip assembly gap 102 and the Y gap area 104 and the groove of the X gap area 107 may be formed by different processes. The same applies to the second to fifth embodiments.

  Further, in the above-described first embodiment, the case where the X margin region 106 is provided in the X direction in the semiconductor wafer 100 has been described (FIG. 13A). However, the present invention is not limited to this, and the X margin region 106 may be omitted as in the semiconductor wafer 1000 shown in FIG. 23 corresponding to FIG. Incidentally, FIG. 23B is a cross-sectional view taken along line G1-G2 in FIG. That is, the X gap region 107 may be disposed between the X chip regions 105 in the X direction. Thereby, the quantity of the light emitting element chips 73 that can be manufactured from one semiconductor wafer can be increased. The same applies to the second and third embodiments.

  Further, in the above-described first embodiment, the case where one long side of the light emitting element chip 73 is bent in a crank shape has been described (FIGS. 12, 13, etc.). However, the present invention is not limited to this. For example, both long sides of the light emitting element chip 73 may be linear, or any side of the light emitting element chip 73 may be bent in a crank shape. In any case, the dummy metal DM may not be disposed in the portion where the groove is to be formed by the DRIE method. The same applies to the second to fifth embodiments.

  Furthermore, in the above-described first embodiment, the case where the dummy metals DM arranged in the respective conductive layers 120 are almost the same size has been described. However, the present invention is not limited to this. For example, the size of the dummy metal DM may be different for each conductive layer 120, or a plurality of types of dummy metals DM having different sizes may be mixed in one conductive layer 120. Also good. The same applies to the second to fifth embodiments.

  Further, in the above-described first embodiment, the case where the dummy metal DM is arranged in all the conductive layers 120 has been described. However, the present invention is not limited to this, and the dummy metal DM may be disposed only in some of the conductive layers 120. The same applies to the second to fifth embodiments.

  Further, in the above-described first embodiment, the case where the conductive layer 120 has three layers has been described. However, the present invention is not limited to this. For example, the conductive layer 120 may have two or less layers or four or more layers. The same applies to the second to fifth embodiments.

  Further, in the fourth embodiment described above, the length of the relatively thick portion of the LOCOS film 815 in the X direction is equal to the length dx of the X gap region 107 and includes the bird's beak portion. The case where the length is made longer than the length dx has been described (FIG. 21). However, the present invention is not limited to this, and the length of the LOCOS film 615 in the X direction, for example, the length including the bird's beak part of the LOCOS film 815 is made equal to the length dx of the X gap region 107. Various values may be used. In this case, it is desirable to adjust the length of each part of the LOCOS film 815 in the X direction so that the smoothness of the upper surface of the semiconductor wafer 800 can be improved.

  Furthermore, in the above-described fifth embodiment, the case where the ESD protection unit 995A is configured by the PMOS transistor 996A and the NMOS transistor 997A has been described (FIG. 22). However, the present invention is not limited to this, and the ESD protection unit 1195A may be configured by various elements such as the diodes 1196A and 1197A, such as a light emitting element chip 1173 shown in FIG. 24 corresponding to FIG. In short, when a signal having a potential of 0 to 5 [V] supplied to the anode terminal 1184A or the like is passed as it is, when a relatively large positive or negative voltage is applied, the signal is supplied to the power supply VDD or ground (VSS). It is sufficient that each light-emitting thyristor LT can be protected by discharging to). The same applies to the ESD protection units 995K, 995SI, and 995SCK.

  Further, in the first embodiment described above, the light emitting thyristor LT of the light emitting element chip 73 is caused to emit light, thereby forming an electrostatic latent image on the peripheral side surface of the photosensitive drum 38 (FIG. 2). The case where the toner image is transferred to form an image is described in FIG. However, the present invention is not limited to this, and for example, an image is formed by various methods such as a printer having an organic EL head composed of an array of organic EL (Electro Luminescence) elements, a thermal printer having aligned heating resistors, and the like. The present invention may be applied to a case where various driven elements arranged in a linear or matrix form are driven by various driving circuits in head portions mounted on various printers. The same applies to the second to fifth embodiments.

  Further, in the above-described first embodiment, the case where the present invention is applied to the image forming apparatus 1 that is an MFP has been described. However, the present invention is not limited to this. For example, the present invention may be applied to various electronic devices having a function of forming a toner image by an electrophotographic method and fixing it on a sheet, such as a copying machine or a facsimile machine. The same applies to the second to fifth embodiments.

  Further, in the above-described first embodiment, the case where the present invention is applied to the case where the light emitting element chip 73 that emits light is manufactured based on the semiconductor wafer 100 has been described. However, the present invention is not limited to this, and an element having various functions such as an image sensor (for example, CIS (Contact Image Sensor)) that receives light and generates an electrical signal corresponding to the amount of light based on a semiconductor wafer. The present invention may be applied when manufacturing a chip. The same applies to the second to fifth embodiments.

  Furthermore, the present invention is not limited to the above-described embodiments and other embodiments. That is, the scope of the present invention extends to embodiments in which some or all of the above-described embodiments and other embodiments described above are arbitrarily combined, and embodiments in which some are extracted. It is.

  Further, in the first embodiment described above, the chip base 73B as the chip base, the light emitting element group 81 as the driven element group, the conductive layer 120 as the conductive layer, and the dummy metal DM as the dummy conductor. The case where the light emitting element chip 73 as the driven element chip is configured is described above. However, the present invention is not limited to this, and a driven element chip may be configured by a chip base having various configurations, a driven element group, a conductive layer, and a dummy conductor.

  The present invention can be used in, for example, an MFP that performs printing by forming a toner image by an electrophotographic method and fixing the toner image on a sheet.

  DESCRIPTION OF SYMBOLS 1,301,501,701,901 ... Image forming apparatus, 3 ... Control part, 16 ... Image forming unit, 33, 333, 533, 733, 933 ... Print head, 50 ... Drive control circuit, 72 ... Printed wiring board, 73, 373, 573, 773, 973 ... Light emitting element chip, 73B ... Chip base, 73BS ... Chip base surface, 73F ... Epitaxial film, 74 ... Paste, 81 ... Light emitting element Group, 82 ... drive circuit group, 100, 400, 600, 800 ... semiconductor wafer, 101 ... light emitting element chip set, 102 ... chip set gap, 103 ... Y chip area, 104 ... Y gap area, 105 ... X chip area, 106 ... X margin area, 107, 407 ... X gap area, 108 ... margin chip, 111, 411 ... first conductive layer, 12, 412 ... 2nd conductive layer, 113, 413 ... 3rd conductive layer, 120 ... conductive layer, 122 ... chip boundary, 123 ... deposited layer, 615, 815 ... LOCOS film, 616, 816 ... LOCOS film gap, 995... ESD protector, 996... PMOS transistor, 997... NMOS transistor, DM .. dummy metal, LT.

Claims (12)

A method for manufacturing a driven element chip by dividing a semiconductor wafer to manufacture a plurality of driven element chips,
The driven element chip is:
A chip substrate having an arrangement surface;
A driven element group provided on the arrangement surface and in which a plurality of driven elements are aligned along the alignment direction;
A conductive layer disposed inside the chip base and having a wiring portion electrically connected to the driven element or a component that drives the driven element;
A dummy conductor disposed in a portion of the conductive layer where the wiring portion is not disposed,
The semiconductor wafer has the arrangement surface when the dummy conductor is arranged in the conductive layer, avoiding a portion that becomes a gap between the driven element chips, and divided into a plurality of the driven element chips. A groove by etching is formed at least in a portion that becomes a side surface on the alignment direction side in the method of manufacturing a driven element chip. The dummy conductor is disposed on the conductive layer so that a side surface of the dummy conductor is aligned with a boundary between the driven element chip and the gap,
2. The method of manufacturing a driven element chip according to claim 1, wherein in the etching process, a side surface of the dummy conductor is exposed to an inner side surface of the groove in the etching process. The semiconductor wafer has a plurality of the conductive layers, and a side surface of the dummy conductor located at a boundary between the driven element chip and the gap is closer to the arrangement surface than the conductive layer closer to the arrangement surface. The method for manufacturing a driven element chip according to claim 2, wherein the distant conductive layer is disposed close to a center side of the driven element chip. The chip base is provided with a base layer on the opposite side of the conductive layer to the arrangement surface, and further, in a portion between the conductive layer and the base layer and serving as a gap between the driven element chips. The method of manufacturing a driven element chip according to claim 1, wherein a Local Oxidation of Silicon) film is formed. A chip substrate having an arrangement surface;
A driven element group provided on the arrangement surface and in which a plurality of driven elements are aligned along the alignment direction;
A conductive layer disposed inside the chip base and having a wiring portion electrically connected to the driven element or a component that drives the driven element;
A dummy conductor disposed in a portion of the conductive layer where the wiring portion is not disposed,
The driven element chip, wherein the chip base is formed by etching at least a side face of the chip base that is the side of the arrangement surface in the alignment direction. The driven element chip according to claim 5, wherein the side surface of the dummy conductor is exposed by an etching process in a portion corresponding to the conductive layer on the side surface of the chip base. The chip base has a plurality of the conductive layers,
The side surface of the dummy conductor exposed on the side surface of the chip base is arranged close to the center side of the driven element chip in the conductive layer farther from the arrangement surface than the conductive layer near the arrangement surface. The driven element chip according to claim 6. The chip base is provided with a base layer on a side opposite to the arrangement surface of the conductive layer, and further, a LOCOS film is formed between the conductive layer and the base layer and serving as a gap between the driven element chips. The driven element chip according to claim 5, wherein the driven element chip is formed. The driven element chip according to claim 5, wherein the driven element is provided on an element film attached to the arrangement surface of the chip base. The driven member according to claim 5, wherein the conductive layer of the chip base is provided with a protection portion that protects the driven element in a wiring electrically connected to the driven element. Drive element chip. A plurality of the driven element chips according to any one of claims 5 to 10,
A plurality of the driven element chips, and a substrate attached in a state of being arranged along the main scanning direction,
The exposure apparatus, wherein the plurality of driven elements respectively provided in the plurality of driven elements are light emitting elements. The exposure apparatus according to claim 11;
An image forming apparatus comprising: a control unit that supplies a signal corresponding to an image to be formed to the exposure apparatus.

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