JP5510469B2 - Logic operation circuit, light emitting element chip, exposure apparatus, and image forming apparatus - Google Patents

Description

The present invention relates to a logical operation circuit, a light emitting element chip, an exposure apparatus, and an image forming apparatus.

  In image forming apparatuses such as printers, copiers, and facsimiles that employ an electrophotographic method, after obtaining an electrostatic latent image by irradiating image information onto a uniformly charged photoreceptor by an optical recording means, The electrostatic latent image is visualized by adding toner, and the image is formed by transferring and fixing on the recording paper. As such an optical recording means, in addition to an optical scanning method in which a laser beam is used for scanning in the main scanning direction for exposure, in recent years, light emission in which light emitting elements such as LEDs (Light Emitting Diodes) are arranged one-dimensionally is used. Optical recording means using an exposure apparatus in which a large number of light emitting element chips including an element array are arranged in the main scanning direction is employed.

  In Patent Document 1, a light emitting element chip using LEDs as light emitting elements is thinned and bonded onto a substrate on which an integrated circuit for controlling the light emitting element array is formed, and then wiring between the light emitting element array and the integrated circuit is performed. A technique for miniaturizing a light emitting element head has been proposed.

JP 2004-207444 A

The present invention provides a logical operation circuit using a pnpn structure .

According to a first aspect of the present invention, there is provided a substrate, a first semiconductor layer stacked on the substrate and having a first conductivity type set to a first potential, stacked on the first semiconductor layer, and the first semiconductor layer A second semiconductor layer having a second conductivity type different from the one conductivity type, and a second semiconductor layer set at a second potential so that a junction with the first semiconductor layer becomes a forward bias; A third semiconductor layer that is stacked on the second semiconductor layer, has the first conductivity type, and has an input electrode for inputting a signal from the outside; and is stacked on the third semiconductor layer and has the second conductivity type. And a fourth semiconductor layer having an output electrode that outputs an inverted signal of the signal, and the output electrode is connected to the first potential via a load resistor, so that the input electrode is This is a logical operation circuit in which a NOT circuit that has an input and outputs the output electrode is configured .
According to a second aspect of the present invention, when the first conductivity type is a p-type using holes as charge carriers and the second conductivity type is an n-type using electrons as charge carriers, the logic operation circuit is A NOR circuit that has a plurality of the NOT circuits, shares the first potential and the second potential of each NOT circuit, and outputs the NOR of a signal input from the outside to each NOT circuit. The logic operation circuit according to claim 1, further comprising:
According to a third aspect of the present invention, when the first conductivity type is n-type using electrons as charge carriers and the second conductivity type is p-type using holes as charge carriers, the logic operation circuit is A NAND circuit that has a plurality of the NOT circuits, shares the first potential and the second potential of each NOT circuit, and outputs NAND of a signal input from the outside to each NOT circuit. The logic operation circuit according to claim 1, further comprising:
According to a fourth aspect of the present invention, there is provided a substrate, a first semiconductor layer having a first conductivity type stacked on the substrate, and a first semiconductor layer stacked on the first semiconductor layer. A second semiconductor layer having a second conductivity type having a different conductivity type, stacked on the second semiconductor layer, a third semiconductor layer having the first conductivity type, and stacked on the third semiconductor layer; a light emitting unit including a plurality of light emitting device including a fourth semiconductor layer having a second conductivity type, and is stacked on the substrate, said first semiconductor layer is set to a first potential, the first semiconductor The second semiconductor layer is stacked on the second semiconductor layer, and is stacked on the second semiconductor layer so as to have a forward bias at the junction between the first semiconductor layer and the first semiconductor layer. said third semiconductor layer having an input electrode more signal is input, the third semiconductor layer It is stacked, and a fourth semiconductor layer having an output electrode for outputting the inverted signal of the signal, that the output electrode is connected to the first potential via a load resistor, the input electrode A light-emitting element chip including a logic operation circuit configured with a NOT circuit having an output as an input and an output of the output electrode, and a control unit that controls light emission of the light-emitting unit.
The invention according to claim 5 is respectively laminated on the substrate, and includes the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, The apparatus further comprises a setting unit provided corresponding to each of the plurality of light emitting elements, and provided with a plurality of setting elements for setting the corresponding light emitting element to a state capable of emitting light by being set to an on state. Item 5. A light emitting device chip according to Item 4.
According to a sixth aspect of the present invention, the first conductivity type is a p-type using holes as charge carriers, and the second conductivity type is an n-type using electrons as charge carriers, The logic operation circuit of the control unit has a plurality of the NOT circuits, and the first potential and the second potential of each NOT circuit are made common, and signals inputted from the outside to the respective NOT circuits are shared. A NOR circuit that outputs NOR, and a combination of the NOT circuit and the NOR circuit that do not constitute the NOR circuit, and identification information unique to the light emitting element chip attached to the light emitting element chip and the light emitting element chip The control signal for causing the plurality of light emitting elements constituting the light emitting unit to emit light is compared with the identification information input from the outside of the light emitting unit or the setting unit. A light-emitting element chip according to claim 5, characterized in that it is supplied.
According to a seventh aspect of the present invention, there is provided a substrate, a first semiconductor layer having a first conductivity type stacked on the substrate, and a first semiconductor layer stacked on the first semiconductor layer. A second semiconductor layer having a second conductivity type having a different conductivity type, stacked on the second semiconductor layer, a third semiconductor layer having the first conductivity type, and stacked on the third semiconductor layer; a fourth semiconductor layer having a second conductivity type, a light emitting unit including a plurality of light emitting device including, stacked on the substrate, and the first semiconductor layer is set to a first potential, the first semiconductor The second semiconductor layer is stacked on the second semiconductor layer, and is stacked on the second semiconductor layer so as to have a forward bias at the junction between the first semiconductor layer and the first semiconductor layer. and said third semiconductor layer having an input electrode more signal is input, the third semiconductor layer It is stacked, and a said fourth semiconductor layer having an output electrode for outputting the inverted signal of the signal, that the output electrode is connected to the first potential via a load resistor, inputs the input electrode A plurality of light emitting element chips each including a logic operation circuit including a NOT circuit configured to output the output electrode, and a control unit that controls the operation of the light emitting unit. An exposure apparatus that performs exposure.
According to an eighth aspect of the present invention, there is provided an image carrier, a charging unit that charges the image carrier, a substrate, a first semiconductor layer having a first conductivity type, each of which is laminated on the substrate, A second semiconductor layer that is stacked on the first semiconductor layer and has a second conductivity type that is different from the first conductivity type, and a second semiconductor layer that is stacked on the second semiconductor layer and has the first conductivity type. A light-emitting unit including a plurality of light-emitting elements each including a third semiconductor layer and a fourth semiconductor layer stacked on the third semiconductor layer and having the second conductivity type; The first semiconductor layer set at the potential and the first semiconductor layer stacked on the first semiconductor layer, and the second potential set at the second potential so that the junction between the first semiconductor layer and the first semiconductor layer is forward biased. and the second semiconductor layer is stacked on the second semiconductor layer, an input electrode signal from the outside is input And said third semiconductor layer having been laminated on the third semiconductor layer, and a said fourth semiconductor layer having an output electrode for outputting the inverted signal of the signal, the said output electrode via a load resistor A control unit that includes a logical operation circuit including a NOT circuit configured to have the input electrode as an input and the output electrode as an output by being connected to the first potential, and to control the operation of the light emitting unit; a plurality of light emitting device chips Ru comprising an exposure means for forming an electrostatic latent image by exposing the charged the image carrier, a developing unit for developing the electrostatic latent image formed on the image carrier And an image forming apparatus including transfer means for transferring the image developed on the image holding member to the transfer target.

According to the first aspect of the present invention, a NOT circuit can be configured using the pnpn structure .
According to invention of Claim 2, a NOR circuit can be comprised using a pnpn structure .
According to invention of Claim 3, a NAND circuit can be comprised using a pnpn structure .
According to the fourth aspect of the present invention , the light emitting unit and the logical operation unit can be formed simultaneously as compared with the case where this configuration is not adopted .
According to the fifth aspect of the present invention, it is possible to provide a light emitting element chip that can reduce the complexity of routing signal lines compared to the case where this configuration is not adopted.
According to the sixth aspect of the present invention, the number of signal lines can be further reduced as compared with the case where this configuration is not adopted.
According to the seventh aspect of the present invention, it is possible to provide an exposure apparatus that reduces the complexity of routing signal lines compared to the case where this configuration is not adopted.
According to the invention of claim 8, it is possible to provide a small and low-cost image forming apparatus as compared with the case where this configuration is not adopted.

1 is a diagram illustrating an overall configuration of an image forming apparatus to which the exemplary embodiment is applied. It is the figure which showed the structure of the exposure apparatus with which this Embodiment is applied. It is the figure which showed the structure of the light emitting element head. It is a figure explaining an example of the signal which a signal generation circuit supplies to a light emitting element chip | tip in a light emitting element head. It is the figure which showed the structure of the light emitting element chip | tip. It is the figure which showed the equivalent circuit of the light emitting element chip | tip using the self-scanning light emitting element array which is 1st Embodiment. It is the figure which showed the cross-section of the principal part of the light emitting element chip | tip by this Embodiment. It is the figure which showed the chip selector which is an example of a control part. It is the figure which showed the 1st NOT circuit by a pnpn structure. It is the figure which showed the NOR circuit by a pnpn structure. It is the figure which showed the chip selector which is another example of a control part. It is the figure which showed the chip selector which is another example of a control part. It is the figure which showed the equivalent circuit of the light emitting element chip | tip using the self-scanning light emitting element array which is 2nd Embodiment. It is the figure which showed the cross-section of the light emitting element chip | tip by this Embodiment. It is the figure which showed the chip selector which is an example of a control part. It is the figure which showed the 2nd NOT circuit by an npnp structure. It is the figure which showed the NAND circuit by npnp structure.

  Embodiments of the present invention will be described below. However, the present invention is not limited to the following embodiments, and can be implemented with various modifications within the scope of the gist. Also, the drawings used are used to describe the present embodiment and do not represent the actual size.

FIG. 1 is a diagram illustrating an overall configuration of an image forming apparatus 1 to which the exemplary embodiment is applied.
An image forming apparatus 1 shown in FIG. 1 includes an image process system 10 that forms an image corresponding to gradation data of each color, an image output control unit 30 that controls the image process system 10, such as a personal computer (PC) 2 or the like. An image processing unit 40 that is connected to the image reading device 3 and performs predetermined image processing on image data received from the image reading device 3 is provided.

  The image processing system 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at intervals defined in the horizontal direction. The image forming unit 11 is composed of four image forming units 11Y, 11M, 11C, and 11K of yellow (Y), magenta (M), cyan (C), and black (K). The photosensitive drum 12 as an example of an image holding member (photosensitive member) that forms a toner image, the charger 13 as an example of a charging unit that charges the surface of the photosensitive drum 12, and the charger 13 are charged. An exposure device 14 as an example of an exposure unit that exposes the photosensitive drum 12 and a developing unit 15 as an example of a development unit that develops a latent image obtained by the exposure device 14 are provided. Further, the image process system 10 conveys the recording paper in order to multiplex-transfer the toner images of the respective colors formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto the recording paper. A sheet conveying belt 21, a driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer roll 23 as an example of a transfer unit that transfers a toner image on the photosensitive drum 12 to a recording sheet that is a transfer target are provided.

  Image data input from the PC 2 or the image reading device 3 is subjected to image processing by the image processing unit 40, and is supplied to each of the image forming units 11Y, 11M, 11C, and 11K as an image signal through the interface. The image process system 10 operates based on a synchronization signal or the like supplied from the image output control unit 30. For example, in the yellow image forming unit 11Y, an electrostatic latent image is formed on the surface of the photosensitive drum 12 charged by the charger 13 by the exposure device 14 based on the image signal obtained from the image processing unit 40. . A yellow toner image is formed by the developing device 15 on the formed electrostatic latent image. The formed yellow toner image is transferred using a transfer roll 23 onto a recording sheet on a sheet conveying belt 21 that rotates in the direction of the arrow in the figure. Subsequently, magenta, cyan, and black toner images are formed on the respective photosensitive drums 12 and are multiple-transferred onto a recording sheet on the sheet conveying belt 21 using a transfer roll 23. The multiple transferred toner images on the recording paper are conveyed to the fixing device 24 and fixed on the recording paper by heat and pressure.

  FIG. 2 is a diagram showing the configuration of the exposure apparatus 14 to which the present embodiment is applied. The exposure apparatus 14 includes a light-emitting element chip 51 in which a large number of light-emitting elements are arranged one-dimensionally, a printed circuit board 52 on which a circuit for supporting the light-emitting element chip 51 and controlling driving of the light-emitting element chip 51 is mounted. And a rod lens array 53 which is an optical element for forming an image of the light output emitted from each light emitting element on the photosensitive drum 12. The printed circuit board 52 and the rod lens array 53 are held by the housing 54. A plurality of light emitting element chips 51 are supported on the printed circuit board 52, and the light emitting elements are arranged in the main scanning direction by the number of pixels. For example, when an A3 size short (297 mm) is used as the main scanning direction, 7040 light emitting elements are arranged every 42.3 μm at a resolution of 600 dpi. In the present embodiment, 7680 light-emitting elements are actually arranged in consideration of misalignment of side registration and the like. Here, the light emitting element chip 51 and the printed circuit board 52 are collectively referred to as a light emitting element head 100.

FIG. 3 is a diagram illustrating a configuration of the light emitting element head 100.
The light emitting element head 100 supplies a printed circuit board 52, a plurality of light emitting element chips 51 arranged in a staggered manner in the main scanning direction, and a control signal for causing the light emitting elements 102 of the plurality of light emitting element chips 51 to emit light. And a signal generation circuit 110. The signal generation circuit 110 may be an LSI such as an ASIC (Application Specific Integrated Circuit).

The light emitting element chip 51 includes a substrate 105, light emitting elements 102 linearly arranged along the long side of the substrate 105 at a regular interval, bonding pads 101, and a controller 140.
The light emitting element chips 51 are arranged on the printed circuit board 52 so that the odd-numbered light emitting element chips 51 and the even-numbered light emitting element chips 51 face each other, and the bonding pads 101 and the control unit 140 are overlapped. Thereby, the light emitting elements 102 on the plurality of light emitting element chips 51 are arranged at equal intervals.

  The signal generation circuit 110 is a light emitting element 102 of the light emitting element chip 51 based on an image signal from the image processing unit 40 provided in the image forming apparatus 1 (see FIG. 1), a synchronization signal from the image output control unit 30, and the like. A control signal for causing the light emission operation to be generated.

In an exposure apparatus using a self-scanning light emitting element array using a light emitting thyristor having a GaAs pnpn structure or npnp structure, a large number of light emitting element chips formed in a one-dimensional array are arranged in a staggered pattern. To do. As a control signal for driving the light emitting element array, a clock signal for sequentially emitting light from the light emitting elements by self-scanning and a lighting signal for designating lighting / non-lighting of each light emitting element are used.
Although the clock signal can be used in common by a plurality of light emitting element chips on the light emitting element head, the lighting signal is provided as a different lighting signal for each light emitting element chip. A corresponding lighting signal line is used.
For this reason, the number of signal lines increases as the number of light emitting element chips increases, and the routing of signal lines between the light emitting element chips arranged in a staggered pattern becomes complicated.
If the light emitting element chips select and incorporate the lighting signals, the lighting signals are multiplexed by a plurality of light emitting element chips, the number of signal lines is reduced, and the signal line routing between the light emitting element chips is simplified.
For this purpose, it is necessary to provide a logical operation circuit for selecting a lighting signal for each light emitting element chip. That is, as an example, a chip selector is provided for each light emitting element chip, identification information for identifying the light emitting element chip is given to each light emitting element chip, and the identification information of the chip select signal cs received by the chip selector and the identification of the light emitting element chip A lighting signal may be taken in when the information matches.

FIG. 4 is a diagram illustrating an example of a signal that the signal generation circuit 110 supplies to the light emitting element chip 51 in the light emitting element head 100. The signal generation circuit 110 includes a transfer signal generation unit 111, a lighting signal generation unit 112, and a selection signal generation unit 113. Transfer signal generator 111 generates start signal φs and clock signals φ1 and φ2. Lighting signal generation unit 112 generates a lighting signal phi _I for controlling lighting / non-lighting of the light emitting element 102. The selection signal generator 113 generates a chip select signal cs for selecting the light emitting element chip 51 to be lit from the plurality of light emitting element chips 51. Further, a power source _VGA and a reference potential (SUB) are supplied to the light emitting element chip 51.

The start signal φs and the clock signals φ 1 and φ 2 are shared by the plurality of light emitting element chips 51 on the light emitting element head 100. Furthermore, in the present embodiment, the lighting signal phi _I and the chip select signal cs is also shared by a plurality of light-emitting element chips 51 on the light-emitting element head 100. That is, even for the light-emitting element chips 51 is not selected as the light-emitting element chip 51 to be turned, the start signal .phi.s, the clock signal .phi.1, .phi.2, lighting signal phi _I like are supplied.

FIG. 5 is a diagram showing a configuration of the light emitting element chip 51 according to the present embodiment.
The light emitting element chip 51 includes a light emitting unit 120 in which the light emitting elements 102 are arranged at equal intervals, a setting unit 130 for sequentially causing the light emitting elements 102 to emit light, a control unit 140, and a bonding pad 101 on a substrate 105. .

Below, 1st Embodiment of the light emitting element chip | tip 51 is described.
FIG. 6 is a diagram showing an equivalent circuit of a light emitting element chip 51a using a self-scanning light emitting element array of a type in which the light emitting section 120 and the setting section 130 according to the first embodiment are separated. This self-scanning light emitting element array includes a light emitting unit 120 including light emitting thyristors L ₁ , L ₂ , L ₃ ,... Which are light emitting elements 102, and transfer thyristors T ₁ , T ₂ , T ₃ ,. , Connecting diodes D ₁ , D ₂ , D ₃ ,..., And a chip selector 141 that is an example of a control unit. The light emitting thyristors L ₁ , L ₂ , L ₃ ,... And the transfer thyristors T ₁ , T ₂ , T ₃ ,.

A power supply V _GA (here, assumed to be −3.3 V) is connected to the transfer thyristors T ₁ , T ₂ , T ₃ ,... From the power line 72 through the load resistors R ₁ , R ₂ , R ₃ ,. Connected to the gate electrodes G ₁ , G ₂ , G ₃ ,... The transfer thyristor _{T 1, T 2, T 3} , ... gate electrode _G 1 _of G 2, _{G 3,} ... light-emitting thyristor _{L 1, L 2, L 3} , ... gate electrode _{G 1, G} 2, and Are connected to G ₃ ,. Here, the transfer thyristor _{T 1, T 2, T 3} , emitting a ... gate electrode of the thyristor _{L 1, L 2, L 3} , no distinction ... a gate electrode of the gate electrode _{G 1,} G 2, _{G 3} , ...
A start signal (φs) line 73 is connected to the gate electrode G ₁ of the transfer thyristor T ₁ and a start signal φs is supplied.
The anode electrodes of the light emitting thyristors L ₁ , L ₂ , L ₃ ,... And the transfer thyristors T ₁ , T ₂ , T ₃ , etc. are connected to a reference potential (SUB) (here, assumed to be 0V). The cathode electrodes of the transfer thyristors T ₁ , T ₂ , T ₃ ,... Are alternately connected to clock signal (φ1, φ2) lines 74, 76, and the clock signals φ1, φ2 are supplied.

The chip selector 141 is connected to a chip select signal line 77, an input side lighting signal line 78, and a reference potential SUB. Further, the chip selector 141 is connected to the cathode electrodes of the light emitting thyristors L ₁ , L ₂ , L ₃ ,.

When the chip selector 141 receives the chip select signal cs, if the identification information (ID) unique to the light emitting element chip 51a matches the identification information input as the chip select signal cs, the chip selector 141 is mounted. were it is determined that the light-emitting element chip 51a is selected, and supplies to the light emitting unit 120 the lighting signal phi _{I 'corresponding} to the lighting signal phi _I input. On the other hand, when the identification information (ID) unique to the light emitting element chip 51a and the identification information input as the chip select signal cs do not match, the chip selector 141 has the light emitting element chip 51a on which the chip selector 141 is mounted. It is determined that it is not selected, and the lighting signal φ _I ′ is not output to the light emitting unit 120.
This feature also simultaneously supplying the lighting signals phi _I like to all the light-emitting element chip 51a on the light-emitting element head 100, only the light-emitting element chip 51a it is determined that the chip selector 141 is selected capture a lighting signal phi _I .
The detailed operation of the chip selector 141 will be described later.

Here, operations of the light emitting unit 120 and the setting unit 130 will be briefly described. First, the operation of the setting unit 130 will be described. Here, the L level and -3.3V power supply _{V GA,} and 0V reference potential (SUB) to H level.

The start signal φs is a signal for starting the operation of the setting unit 130. The on-voltage of the transfer thyristor is approximated by the potential of the gate electrode + the diffusion potential of the pn junction (here, assumed to be 1 V). When the start signal φs to H level (0V), the potential of the gate electrode _{G 1} is made to 0V, and the ON voltage of the transfer thyristor _{T 1} becomes -1 V. At this time, when the clock signal φ2 to L level, the transfer thyristor T ₁ is turned on. Immediately thereafter, the start signal φs is returned to the L level.

When the transfer thyristor _{T 1} is turned on, the potential of the gate electrode _{G 1} is raised to the 0V approximately SUB from -3.3V to _{V GA.} The effect of this potential rise is transmitted to the gate electrode G ₂ through the connecting diode D _1, the value of the potential of the gate electrode G ₂ minus -1 V (equal to the forward threshold voltage (diffusion potential of the connection diode D ₁ from SUB) ). Thus, the ON voltage of the transfer thyristor _{T 2} are, the -2 V. Therefore, when the clock signal φ1 is lower than -2V potential, the transfer thyristor T ₂ is turned on. Following this, when returning the clock signal φ2 to 0V at the H level, the transfer thyristor _{T 1} is turned off, the potential of the gate electrode _{G 1} becomes -3.3V of L level.

When the transfer thyristor _{T 2} is turned on, the potential of the gate electrode _{G 2} is increased up to 0V approximately SUB from -1 V. The effect of this potential rise is transmitted to the gate electrode _{G 3} through the connecting diode _{D 2,} the potential of the gate electrode _{G 3} is turned -1 V, the ON voltage of the transfer thyristor _{T 3} becomes -2 V.
Meanwhile, since the connecting diode D ₁ is reverse biased, not transmitted the aforementioned effects of the potential rise to the gate electrode G _1. Therefore, the potential of the gate electrode _{G 1} will remain -3.3 V, the ON voltage of the transfer thyristor _{T 1} becomes -4.3V.
When the clock signal φ2 to a potential between -2V and -4.3V, the transfer thyristor T ₃ is turned on, the transfer thyristors excluding the transfer thyristors T ₂ and the transfer thyristor T ₃ is kept in the off state.
Thus, by repeating the operations of the clock signal φ1 and the clock signal φ2, the transfer thyristors are sequentially turned on.

Next, the operation of the light emitting unit 120 will be described. Now, the transfer thyristor _{T 1} is When in the ON state, the potential of the gate electrode _{G 1 is} raised to the 0V approximately SUB from -3.3V to _{V GA.} ON voltage of the light-emitting thyristor, the diffusion potential of + pn junction of the gate electrode (assumed here to be 1V.) Because it is approximated by the on voltage of the light-emitting thyristor L ₁ becomes -1 V.
On the other hand, on-voltage of the light-emitting thyristor _{L 2} is -2 V. The on voltage of the light emitting thyristors L ₃ , L ₄ , L ₅ ,... Is −3 V or less because a connection diode is further added. Accordingly, the lighting signal phi _I, if the potential between -1V to-2V, only the light-emitting thyristor _{L 1} is turned on, the light-emitting thyristor _{L 2, L 3, L 4} , ... are kept OFF state The
Incidentally, the on-state light-emitting thyristor L _1, by a lighting signal phi _I to 0V at the H level, to turn off.

The light-emitting thyristor _{L 1, L 2, L 3} , ... emission intensity of is determined by the width of current amount and / or lighting signal phi _I flowing to the lighting signal phi _I. Furthermore, even certain transfer thyristor is turned on, if the lighting signal phi _I remains at H level 0V, the light-emitting thyristor corresponding to the transfer thyristor remains unlit.

FIG. 7 is a view showing a cross-sectional structure of a main part of the light emitting element chip 51a according to the present embodiment. Light-emitting element chip 51a is formed on a substrate 200, made of pnpn structure light-emitting thyristor _{L 1,} L 2, _{L 3} of the light emitting portion 120, and the light emitting thyristor 401 is ..., the transfer thyristors _{T 1} of the setting unit 130 , T ₂ , T ₃ ,..., And a logical operation element 403 of the control unit 140.
The light emitting element chip 51a is a case where the first conductivity type is a p-type using holes as charge carriers, and the second conductivity type is an n-type using electrons as charge carriers, and is configured by a GaAs-based semiconductor. On the substrate 200, a p-type first semiconductor layer (abbreviated as p in the drawing) 201, an n-type second semiconductor layer (abbreviated as n in the drawing) 202, and a p-type third semiconductor layer (in the drawing). p.) 203 and an n-type fourth semiconductor layer (abbreviated n in the drawing) 204 are stacked, and then a predetermined portion is etched. In the present embodiment, the light-emitting thyristor 401 of the light-emitting unit 120, the transfer thyristor 402 of the setting unit 130, and the logic operation element 403 of the control unit 140 are the p-type first semiconductor layer 201 and the n-type second semiconductor layer 202. , P-type third semiconductor layer 203 and n-type fourth semiconductor layer 204 are stacked vertically.

The connection diodes D ₁ , D ₂ , D ₃ ,... Used for the setting unit 130 are formed using a junction between the p-type third semiconductor layer 203 and the n-type fourth semiconductor layer 204.
Further, in the control unit 140, the logical operation element 403 has a pnpn structure, but not all logical operation elements have a pnpn structure. A pnp transistor including a p-type first semiconductor layer 201, an n-type second semiconductor layer 202, and a p-type third semiconductor layer 203, an n-type second semiconductor layer 202, and a p-type third semiconductor layer 203 And an npn transistor composed of the n-type fourth semiconductor layer 204, a diode using the junction of the p-type first semiconductor layer 201 and the n-type second semiconductor layer 202, and the n-type second semiconductor layer 202 Any continuous layer such as a diode using a junction between the p-type third semiconductor layer 203 and a diode using a junction between the p-type third semiconductor layer 203 and the n-type fourth semiconductor layer 204 is combined. Can be used.
As will be described later, the control unit 140 uses the pnpn structure after performing a predetermined process, such as removing an upper semiconductor layer in a partial region.

  The light emitting thyristor 401 of the light emitting unit 120 and the transfer thyristor 402 of the setting unit 130 use the p-type first semiconductor layer 201 serving as the anode electrode (A) as a reference potential (SUB) electrode and the n-type fourth semiconductor layer 204. Are connected to the cathode electrode (K), and the p-type third semiconductor layer 203 is connected to the gate electrode (G). On the other hand, the logic operation element 403 having the pnpn structure of the control unit 140 includes the p-type first semiconductor layer 201 as a reference potential (SUB) electrode and the n-type second semiconductor layer 202 as a DC voltage electrode (E). In addition, the p-type third semiconductor layer 203 is connected to the input electrode (Input), and the n-type fourth semiconductor layer 204 is connected to the output electrode (Output).

  The logical operation element 403 of the control unit 140 has a structure in which a DC voltage electrode (E) is provided on the n-type second semiconductor layer 202 of the light emitting thyristor 401 of the light emitting unit 120 or the transfer thyristor 402 of the setting unit 130. Therefore, by controlling the potential of the DC voltage electrode (E) of the logical operation element 403, the logical operation element 403 becomes the light emitting thyristor 401 of the light emitting unit 120 or the transfer thyristor 402 of the setting unit 130.

In FIG. 7, the light-emitting thyristor 401, the transfer thyristor 402, and the logical operation element 403 are each formed in an independent island shape, but it is not necessary that all the layers are separated. A structure in which layers are connected can also be used.
The substrate 200 may be a p-type semiconductor, and may be abbreviated as the substrate 200 also serves as the p-type first semiconductor layer 201. In these cases, a reference potential (SUB) electrode may be provided on the back surface of the substrate 200.

FIG. 8 is a diagram illustrating a chip selector 141 which is an example of a control unit. FIG. 8A shows an equivalent circuit of the chip selector 141, and FIG. 8B shows a cross-sectional structure of the chip selector 141.
The chip selector 141 includes four chip select signal (cs) lines 771 to 774, an input side lighting signal (φ _I ) line 78, an output side lighting signal (φ _I ′) line 79, and a reference potential ( SUB) electrode. The chip selector 141 includes a fuse 171 that creates a current path disconnection or contact state, a first NOT circuit 300 that performs a negative (NOT) logical operation, and an AND circuit 146 that performs a logical OR (AND) logical operation. A decode circuit 145 and a transistor switch 147 are provided. The chip select signal (cs) lines 771 to 774 are connected to the decode circuit 145, and the output of the AND circuit 146 in the decode circuit 145 is connected to the base electrode (B) of the transistor switch 147. The emitter electrode of the transistor switch 147 (e) is connected to the reference potential (SUB) electrode, the collector electrode of the transistor switch 147 (c) the input side of the lighting signal (phi _I) line 78 and the output side of the lighting signal (phi _I ') Connected to line 79.

  The decode circuit 145 compares the identification information unique to the light emitting element chip 51a with the identification information input as the chip select signal cs by a logical operation. The transistor switch 147 supplies a control signal for causing the light emitting thyristor 401 to perform a light emitting operation based on the comparison result of the logical operation of the decoding circuit 145.

First, the operation of the decoding circuit 145 will be described. The chip select signal (cs) line 771 branches in the decode circuit 145 into a path 771a having only the fuse 171 and a path 771b in which the fuse 171 and the first NOT circuit 300 are connected in series. For example, in a setting in which the fuse 171 of the path 771a of only the fuse 171 is connected and the fuse 171 of the path 771b in which the fuse 171 and the first NOT circuit 300 are connected in series is disconnected, the chip select signal (cs) line 771 When the chip select signal cs is “1”, “1” is input to the AND circuit 146. On the other hand, when the chip select signal cs on the chip select signal (cs) line 771 is “0”, “0” is input to the AND circuit 146.
On the other hand, in the setting in which the fuse 171 in the path 771a only for the fuse 171 is cut off and the fuse 171 in the path 771b in which the fuse 171 and the first NOT circuit 300 are connected in series is connected, the chip select signal (cs) line When the chip select signal cs 771 is “1”, the first NOT circuit 300 inverts (inverts) the output, so that “0” is input to the AND circuit 146. On the other hand, when the chip select signal cs on the chip select signal (cs) line 771 is “0”, “1” is input to the AND circuit 146.
The same applies to the other chip select signal (cs) lines 772-774.

In FIG. 8A, all of the chip select signal (cs) lines 771 to 774 are connected to the fuse 171 of the path 771a of the fuse 171 only, and the path in which the fuse 171 and the first NOT circuit 300 are connected in series. The fuse 171 is set to be disconnected. Therefore, all inputs of the AND circuit 146 are “1” only when all the chip select signals cs of the chip select signal (cs) lines 771 to 774 are “1”, that is, when the chip select signal cs is “1111”. Thus, the output of the AND circuit 146 becomes 1. On the other hand, when the chip select signal cs is not “1111”, for example, “0010”, the output of the AND circuit 146 becomes “0”.
Here, the identification information unique to the light emitting element chip 51 is configured by connecting and disconnecting the fuse 171 and is compared with the identification information input from the outside as the chip select signal cs.

Next, the transistor switch 147 will be described. The transistor switch 147, which is a pnp transistor, has an emitter electrode (e) connected to 0 V at the H level. When the output of the AND circuit 146 is “1” (H level), the transistor switch 147 is in an output cut-off state, and the lighting signal line (φ _I ′) on the output side from the lighting signal (φ _I ) line 78 on the input side. ) 79 via the input side of the lighting signal phi lighting signal corresponding to the _I phi _{I 'is} supplied to the cathode electrode of the light emitting thyristors 401 of the light emitting portion 120 (K). Thereby, lighting of the light emitting thyristor 401 of the light emitting element chip 51a on which the chip selector 141 is mounted is controlled.
On the other hand, when the output of the AND circuit 146 is “0” (L level), the transistor switch 147 is turned on, and the lighting signal (φ _I ′) line 79 is fixed to 0 V of SUB. Therefore, the light-emitting thyristor 401 of the light-emitting element chip 51a on which the chip selector 141 is mounted is turned on because the reference potential (SUB) electrode, which is the anode electrode (A), and the cathode electrode (K) have the same potential of 0V. do not do.
In this way, the chip selector 141 controls the light emitting operation of the light emitting element chip 51a on which the chip selector 141 is mounted.

  Here, four signal lines are used as the chip select signal cs, but the number may be increased or decreased according to the number of light emitting element chips 51a on the light emitting element head 100. Here, the method of giving identification information to the light emitting element chip 51a using the fuse 171 is used, but the identification information is given by forming a predetermined wiring at the time of manufacturing the light emitting element chip 51. Methods etc. can also be used.

FIG. 8B is a diagram illustrating a cross-sectional structure of the transistor switch 147 and the light-emitting thyristor 401. The light-emitting thyristor 401 has been described with reference to FIG. The transistor switch 147 uses the p-type first semiconductor layer 201, the n-type second semiconductor layer 202, and the p-type third semiconductor layer 203 for the emitter region, the base region, and the collector region, respectively. . The light-emitting thyristor 401 and the transistor switch 147 are formed on the substrate 200 with a p-type first semiconductor layer 201, an n-type second semiconductor layer 202, a p-type third semiconductor layer 203, and an n-type fourth semiconductor layer. After the semiconductor layer 204 is sequentially stacked, a predetermined layer is removed by etching. Here, the p-type first semiconductor layer 201 is shared.
The gate electrode (G) of the light emitting thyristor 401 is connected to the gate electrode (G) of the transfer thyristor 402 (not shown), and the base electrode (B) of the transistor switch 147 is connected to the output of the AND circuit 146 (not shown). ing.

First, the first NOT circuit 300 that is one of the logical operation elements 403 will be described.
FIG. 9 is a diagram showing a first NOT circuit 300 having a pnpn structure. FIG. 9A shows a cross-sectional structure of the first NOT circuit 300, and FIG. 9B shows an equivalent circuit of the first NOT circuit 300.
As shown in FIG. 9A, the first NOT circuit 300 has the same structure as the logical operation element 403 in FIG.

  As shown in FIG. 9B, the first NOT circuit 300 includes the p-type first semiconductor layer 201, the n-type second semiconductor layer 202, and the p-type shown in FIG. The third semiconductor layer 203 includes a pnp transistor (Q1) that functions as an emitter region, a base region, and a collector region, the n-type second semiconductor layer 202 shown in FIG. Each of the three semiconductor layers 203 and the n-type fourth semiconductor layer 204 is a circuit in which an emitter region, a base region, and an npn transistor (Q2) serving as a collector region are combined. The pnp transistor (Q1) and the npn transistor (Q2) are stacked vertically.

The operation of the first NOT circuit 300 will be described with reference to the equivalent circuit of FIG. The reference potential (SUB) electrode is set to H level 0 V, the DC voltage electrode (E) is set to −1 V to −1.5 V at L level, and the p-type first semiconductor layer 201 and the n-type second semiconductor layer The pn junction formed by 202 is made forward biased. Then, the pnp transistor (Q1) is turned on and functions as a constant current source. Further, the output electrode (Output) is pulled up to an H level via a load resistor (not shown). When the input electrode (Input) is at the L level, a current flows from the reference potential (SUB) electrode to the input electrode (Input) through the pnp transistor (Q1). Since the DC voltage electrode (E) is at the L level and the input electrode (Input) is at the L level, the npn transistor (Q2) is in the output cutoff state, and the output electrode (Output) is maintained at the H level.
On the other hand, when the input electrode (Input) is at the H level, a current flows from the reference potential (SUB) electrode through the pnp transistor (Q1) to the base of the npn transistor (Q2). As a result, the npn transistor (Q2) is turned on, and the output electrode (Output) is fixed to the potential of the DC voltage electrode (E) and becomes L level. That is, in the first NOT circuit 300, when the input electrode (Input) is at L level, the output electrode (Output) is at H level, and when the input electrode (Input) is at H level, the output electrode (Output) is at L level. And functions as NOT.
This operation is the same as the operation of IIL (Integrated Injection Logic, I ² L) known as a logic processing element of a bipolar transistor, and is based on the operation of the bipolar transistor.

Next, the AND circuit 146 will be described.
The AND circuit 146 includes a NOT circuit 300 and a NOR circuit 310 that performs a logical operation of a negative logical sum (NOR) based on A AND B = NOT (A) NOR NOT (B) based on the theory of logical operation. .
Therefore, the NOR circuit 310 that is one of the logical operation elements 403 will be described.
10A and 10B are diagrams showing a NOR circuit 310 having a pnpn structure, where FIG. 10A shows a cross-sectional structure of the NOR circuit 310 and FIG. 10B shows an equivalent circuit of the NOR circuit 310. . Further, FIG. 10C is a truth table of the NOR circuit 310.
As shown in FIG. 10A, the NOR circuit 310 has a structure in which two first NOT circuits 300 shown in FIG. 9A are arranged. The p-type first semiconductor layer 201 and the n-type second semiconductor layer 202 are common.
Two input electrodes (Input) of the first NOT circuit 300 arranged side by side are connected to the first input electrode (Input1) and the second input electrode (Input2), respectively. Further, each output electrode (Output), DC voltage electrode (E), and reference potential (SUB) electrode are made common.

  The operation of the NOR circuit 310 will be described with reference to the equivalent circuit shown in FIG. One of the two first NOT circuits 300 arranged side by side constitutes a pnp transistor (Q1) and an npn transistor (Q2), and the other one of the first NOT circuits 300 is a pnp transistor (Q3) and an npn transistor. (Q4). The relationship between the pnp transistors (Q1) to npn transistor (Q4) and the semiconductor layers 201 to 204 has been described with reference to FIG. The reference potential (SUB) electrode is set to H level 0 V, and the DC voltage electrode (E) is set to L level −1 to −1.5 V. Further, the output electrode (Output) is pulled up to an H level via a load resistor (not shown). When the first input electrode (Input1) is at the L level, a current flows from the reference potential (SUB) electrode to the first input electrode (Input1) through the pnp transistor (Q1). The npn transistor (Q2) is in the output cut-off state because the first input electrode (Input1) is at the L level. If the second input electrode (Input2) is also at the L level, the npn transistor (Q4) is in an output cutoff state. Therefore, the output electrode (Output) is maintained at the H level.

  On the other hand, when the first input electrode (Input1) is at the H level, current flows from the reference potential (SUB) electrode through the pnp transistor (Q1) to the base region of the npn transistor (Q2), and the npn transistor (Q2) Since the output is turned on, the output electrode (Output) is fixed to the potential of the DC voltage electrode (E) and becomes L level. Even if the second input electrode (Input 2) is at the L level, the npn transistor (Q4) is turned on, so that the output electrode (Output) is at the L level. That is, if either the first input electrode (Input1) or the second input electrode (Input2) is at the H level, the npn transistor (Q2) or (Q4) is turned on, so that the output electrode (Output) Is fixed at the L level. That is, the NOR circuit 310 functions as the NOR shown in the truth table of FIG.

Although FIG. 10 shows the two-input NOR circuit 310 in which two first NOT circuits 300 are arranged, a multi-input NOR circuit is formed by arranging a plurality of first NOT circuits 300.
As described above, the above-described AND circuit 146 can be composed of the first NOT circuit 300 and the NOR circuit 310 according to the present embodiment. Further, by combining the NOR circuit 310, various logical operations can be expressed.

In this embodiment, the light emitting thyristors 401 and the transfer thyristors 402 of the light emitting portion 120 and the setting unit 130 is to use a -3.3V as a power supply _{V GA,} logical operation element 403 of the control unit 140 DC voltage electrode As a voltage to be set in (E), −1 to −1.5 V is used. The voltage difference between the light emitting unit 120 and the setting unit 130 and the control unit 140 can be converted through a transistor switch or the like.

FIG. 11 is a diagram illustrating a chip selector 142 which is another example of the control unit. FIG. 11A shows an equivalent circuit, and FIG. 11B shows a cross-sectional structure.
The chip selector 142 shown in FIG. 11 is different from the chip selector 141 shown in FIG. 8 in that the transistor switch 148 has a multi-collector electrode structure. The multi-collector electrode structure means that the bipolar transistor has a plurality of collector electrodes. Here, the first collector electrode 161 is connected to a lighting signal (φ _I ) line 78 and a lighting signal (φ _I ′) line 79. The second collector electrode 162 is connected to the _second gate electrode (G ₂ ) provided in the n-type second semiconductor layer 202 of all the light emitting thyristors 401 a of the light emitting unit 120.

The operation of the chip selector 142 will be described with reference to the equivalent circuit of FIG. When the chip select signal cs is “1111”, the output of the AND circuit 146 becomes “1” (H level). Thus, the transistor switch 148 is output cutoff state, via the output side of the lighting signal (φ _I ') line 79 from a lighting signal (phi _I) line 78 on the input side, the lighting signal of the input side phi _I lighting signal phi _{I 'corresponding} to, is supplied to the light emitting portion 120 of the light-emitting element chips 51a. At this time, since the transistor switch 148 is in the output cut-off state, the second collector electrode 162 is also in a high impedance state and does not hinder the light emission of the light emitting thyristor 401a.

On the other hand, when the chip select signal cs is not “1111”, the output of the AND circuit 146 is “0” (L level), so that the transistor switch 148 is turned on, and the first collector electrode 161 and the second collector electrode 161 are turned on. The collector electrode 162 becomes 0V of SUB. As a result, the output side of the lighting signal (φ _I ') line 79 is fixed to 0V of SUB, the chip selector 142 lighting signal phi _I to the light-emitting thyristor 401a' does not supply. Since the second collector electrode 162 is connected to the _second gate electrode (G ₂ ) of the light-emitting thyristor 401a, the reference potential (SUB) electrode and the second gate electrode functioning as the anode electrode (A) of the light-emitting thyristor 401a. Both (G ₂ ) and the cathode electrode (K) become 0 V, thereby preventing the operation of the light emitting thyristor 401a.

As described above, when the chip selector 142 determines that the light emitting element chip 51a on which the chip selector 142 is mounted is not selected, the chip selector 142 does not supply the lighting signal φ _I ′ to the light emitting thyristor 401a and emits light. The thyristor 401a has a function of preventing an operation of emitting light due to a malfunction.

FIG. 12 is a diagram showing a chip selector 143 as another example of the control unit. Chip selector 141 and the chip selector 142 shown in FIGS. 8 and 11 controls the lighting signal phi _I. On the other hand, the chip selector 143 controls the clock signals φ1, φ2 and the start signal φs. When the chip selector 143 determines that the light emitting element chip 51b on which the chip selector 143 is mounted is selected based on the chip select signal cs, the input side clock signals φ1 and φ2 and the start signal φs are The output side clock signals φ1 ′ and φ2 ′ and the start signal φs ′ are supplied to the setting unit 130, respectively. On the other hand, when the chip selector 143 determines that the light emitting element chip 51b on which the chip selector 143 is mounted is not selected, the clock signals φ1 ′ and φ2 ′ and the start signal φs ′ are set in advance to 0V or the like. The operation of the setting unit 130 is prevented by fixing to the set potential.

Next, a second embodiment of the light emitting element chip 51 will be described. In the first embodiment shown in FIG. 6, the case where the light emitting thyristor and the transfer thyristor using the anode electrode as the reference potential (SUB) electrode has been described. Even when a light emitting thyristor and a transfer thyristor having a cathode electrode as a reference potential (SUB) electrode are used, the operation is performed by changing the polarity of the circuit.
FIG. 13 is a diagram showing an equivalent circuit of a light emitting element chip 51c using a self-scanning light emitting element array of a type in which the light emitting section and the setting section according to the second embodiment are separated. Although detailed description is omitted, the power supply _VGA is used as the power supply _VGK , and the circuit operates by changing the polarity of the circuit.

FIG. 14 is a diagram showing a cross-sectional structure of a main part of the light emitting element chip 51c according to the present embodiment. The light emitting element chip 51c includes a light emitting thyristor 411 which is a light emitting thyristor L ₁ , L ₂ , L ₃ ,... Of the light emitting unit 120 and a transfer thyristor T ₁ , A transfer thyristor 412 that is T ₂ , T ₃ ,... And a logical operation element 413 of the control unit 140 are provided.
The light emitting element chip 51c is a case where the first conductivity type is n-type using electrons as charge carriers and the second conductivity type is p-type using holes as charge carriers, and is made of a GaAs-based semiconductor. The n-type first semiconductor layer 211, the p-type second semiconductor layer 212, the n-type third semiconductor layer 213, and the p-type fourth semiconductor layer 214 are sequentially stacked on the substrate 210. Thereafter, a predetermined portion is formed by etching. In the present embodiment, the light-emitting thyristor 411 of the light-emitting unit 120, the transfer thyristor 412 of the setting unit 130, and the logical operation element 413 of the control unit 140 are the n-type first semiconductor layer 211 and the p-type second semiconductor layer 212. , N-type third semiconductor layer 213, and p-type fourth semiconductor layer 214 are stacked vertically.

The connection diode used for the setting unit 130 is formed using a junction between the n-type third semiconductor layer 213 and the p-type fourth semiconductor layer 214.
Further, in the control unit 140, the logical operation element 413 has an npnp structure, but not all logical operation elements have an npnp structure. An npn transistor including an n-type first semiconductor layer 211, a p-type second semiconductor layer 212, and an n-type third semiconductor layer 213, a p-type second semiconductor layer 212, and an n-type third semiconductor layer 213 A pnp transistor including a p-type fourth semiconductor layer 214, a diode using a junction between the n-type first semiconductor layer 211 and the p-type second semiconductor layer 212, and a p-type second semiconductor layer 212. Any continuous layer such as a diode using a junction between the n-type third semiconductor layer 213 and a diode using a junction between the n-type third semiconductor layer 213 and the p-type fourth semiconductor layer 214 is combined. Can be used.
As will be described later, the control unit 140 uses the npnp structure after performing a predetermined process such as removing an upper semiconductor layer in a partial region.

The light emitting thyristor 411 of the light emitting unit 120 and the transfer thyristor 412 of the setting unit 130 use the n-type first semiconductor layer 211 serving as an anode electrode (K) (not shown) as a reference potential (SUB) electrode and a p-type. The fourth semiconductor layer 214 is connected to the anode electrode (A), and the n-type third semiconductor layer 213 is connected to the gate electrode (G). On the other hand, the logic operation element 413 of the control unit 140 includes an n-type first semiconductor layer 211 as a reference potential (SUB) electrode, a p-type second semiconductor layer 212 as a DC voltage electrode (E), and an n-type first semiconductor layer 211. The third semiconductor layer 213 is connected to the input electrode (Input), and the p-type fourth semiconductor layer 214 is connected to the output electrode (Output).
Note that the logical operation element 413 has a structure in which a DC voltage electrode (E) is provided on the p-type second semiconductor layer 212 of the light-emitting thyristor 411 or the transfer thyristor 412. Therefore, by controlling the potential of the DC voltage electrode (E) of the logic operation element 413, the logic operation element 413 becomes the light emitting thyristor 411 of the light emitting unit 120 or the transfer thyristor 412 of the setting unit 130.

In FIG. 14, the light-emitting thyristor 411, the transfer thyristor 412 and the logical operation element 413 are formed in independent island shapes, but it is not necessary that all layers are separated. A structure in which layers are connected can also be used.
The substrate 210 may be an n-type semiconductor substrate, and may be abbreviated because the substrate 210 also serves as the n-type first semiconductor layer 211. In these cases, a reference potential (SUB) electrode may be provided on the back surface of the substrate 210.

FIG. 15 is a diagram illustrating a chip selector 144 as an example of a control unit according to the second embodiment. The transistor switch 151 of the chip selector 144 has a multi-collector electrode structure, and the transistor switch 151 includes a first collector electrode 163 and a second collector electrode 164. The second collector electrode 164 is connected to the second gate electrode (G2) of all the light emitting thyristors 411a of the light emitting unit 120.
Although detailed description is omitted, the chip selector 144 replaces the AND circuit 146 of the chip selector 142 with the OR circuit 159, the first NOT circuit 300 with the second NOT circuit 301, and further replaces the polarity of the transistor switch 151. At the same time, it operates by changing the polarity of the circuit.

The second NOT circuit 301 that is one of the logical operation elements will be described.
FIG. 16 is a diagram showing a second NOT circuit 301 having an npnp structure. FIG. 16A shows a cross-sectional structure of the second NOT circuit 301, and FIG. 16B shows an equivalent circuit of the second NOT circuit 301.

As shown in FIG. 16A, the second NOT circuit 301 has the structure of the logical operation element 413 shown in FIG.
As shown in FIG. 16B, the second NOT circuit 301 includes the n-type first semiconductor layer 211, the p-type second semiconductor layer 212, and the n-type semiconductor shown in FIG. The third semiconductor layer 213 includes an npn transistor (Q5) that functions as an emitter region, a base region, and a collector region, the p-type second semiconductor layer 212 shown in FIG. The third semiconductor layer 213 and the p-type fourth semiconductor layer 214 are a circuit in which an emitter region, a base region, and a pnp transistor (Q6) serving as a collector region are combined. The npn transistor (Q5) and the pnp transistor (Q6) are stacked vertically.

  The operation of the second NOT circuit 301 will be described with reference to the equivalent circuit of FIG. The reference potential (SUB) electrode is set to 0V of the SUB of the L level, the DC voltage electrode (E) is set to 1V to 1.5V of the H level, and the n-type first semiconductor layer 211 and the p-type second semiconductor layer The junction formed by the reference numeral 212 is forward biased. Then, the npn transistor (Q5) is turned on and functions as a constant current source. Further, the output electrode (Output) is pulled down to L level via a load resistor (not shown). When the input electrode (Input) is at the H level, a current flows from the input electrode (Input) to the reference potential (SUB) electrode through the npn transistor (Q5). Since the DC voltage electrode (E) is at the H level and the input electrode (Input) is at the H level, the pnp transistor (Q6) is in the output cutoff state, and the output electrode (Output) is maintained at the L level. On the other hand, when the input electrode (Input) is at the L level, a current flows from the base of the pnp transistor (Q6) to the reference potential (SUB) electrode through the npn transistor (Q5). As a result, the pnp transistor (Q6) is turned on, and the output electrode (Output) is fixed to the potential of the DC voltage electrode (E) and becomes H level. That is, in the second NOT circuit 301, when the input electrode (Input) is at L level, the output electrode (Output) is at H level, and when the input electrode (Input) is at H level, the output electrode (Output) is at L level. Therefore, it functions as NOT.

Next, the OR circuit 159 will be described.
The OR circuit 159 includes a second NOT circuit 301 and a NAND circuit 311 that performs a negative logical product (NAND) operation based on A OR B = NOT (A) NAND NOT (B).
Therefore, a NAND circuit 311 that is one of the logical operation elements 413 will be described.
17A and 17B are diagrams showing a NAND circuit 311 having an npnp structure, where FIG. 17A shows a cross-sectional structure of the NAND circuit 311, and FIG. 17B shows an equivalent circuit of the NAND circuit 311. FIG. 17C is a truth table of the NAND circuit 311.
As shown in FIG. 17A, the NAND circuit 311 has a structure in which two second NOT circuits 301 shown in FIG. The n-type first semiconductor layer 211 and the p-type second semiconductor layer 212 are common to each other.
Two input electrodes (Input) of the second NOT circuit 301 arranged side by side are connected to a third input electrode (Input 3) and a fourth input electrode (Input 4), respectively. Further, each output electrode (Output), DC voltage electrode (E), and reference potential (SUB) electrode are made common.

The operation of the NAND circuit 311 will be described with reference to the equivalent circuit of FIG. One of the two second NOT circuits 301 arranged side by side constitutes an npn transistor (Q5) and a pnp transistor (Q6), and the other one of the second NOT circuit 301 is an npn transistor (Q7) and a pnp transistor ( Q8) is configured.
The relationship between the npn transistors (Q5) to pnp transistor (Q8) and the semiconductor layers 211 to 214 is the same as that described with reference to FIG. The reference potential (SUB) electrode is set to 0 V at the L level, and the DC voltage electrode (E) is set to 1 V to 1.5 V at the H level. Further, the output electrode (Output) is pulled down to L level via a load resistor (not shown). When the third input electrode (Input 3) is at the H level, a current flows from the third input electrode (Input 3) to the reference potential (SUB) electrode through the npn transistor (Q5). The pnp transistor (Q6) is in the output cut-off state because the third input electrode (Input3) is at the H level. If the fourth input electrode (Input 4) is also at the H level, the pnp transistor (Q8) is in an output cutoff state. Therefore, the output electrode (Output) maintains the L level.

On the other hand, when the third input electrode (Input 3) is at the L level, current flows from the base of the pnp transistor (Q6) to the reference potential (SUB) electrode through the npn transistor (Q5), and the pnp transistor (Q6) is turned on. Therefore, the output electrode (Output) is fixed to the potential of the DC voltage electrode (E) and becomes H level. Even if the fourth input electrode (Input 4) is at H level, the output electrode (Output) is at H level. That is, if either the third input electrode (Input 3) or the fourth input electrode (Input 4) is at the L level, the pnp transistor (Q6) or the pnp transistor (Q8) is turned on, so that the output electrode ( Output) becomes H level. That is, the NAND circuit 311 functions as the NAND shown in the truth table of FIG.
Although FIG. 17 shows the two-input NAND circuit 311 in which two second NOT circuits 301 are arranged, a multi-input NAND circuit is formed by arranging a plurality of second NOT circuits 301.
As described above, the OR circuit 159 described above can be composed of the second NOT circuit 301 and the NAND circuit 311 according to this embodiment. Furthermore, various logical operations can be expressed by combining the NAND circuit 311.

In the present embodiment, the light emitting thyristor 411 and the transfer thyristor 412 of the light emitting unit 120 and the setting unit 130 use 3.3 V as the power source V _GK , whereas the logic operation element 413 of the control unit 140 has a DC voltage electrode ( 1 to 1.5 V is used as the voltage to be set in E). The voltage difference between the light emitting unit 120 and the setting unit 130 and the control unit 140 can be converted through a transistor switch or the like.

Furthermore, an RS flip-flop, a D latch, a D flip-flop, a shift register, or the like can be configured by a NOR circuit or a NAND circuit according to the theory of logical operation.
Therefore, in this embodiment, the case of the chip selector as the control unit has been described. However, the present invention is not limited to this, and a shift circuit that shifts the position of the light emitting element that starts the lighting of the light emitting unit can be configured.
The semiconductor device is composed of a GaAs-based semiconductor. However, the present invention is not limited to this. For example, GaP or a compound semiconductor that is difficult to manufacture a p-type semiconductor or an n-type semiconductor by ion implantation may be used.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 11Y, 11M, 11C, 11K ... Image forming unit, 14 ... Exposure apparatus, 23 ... Transfer roll, 24 ... Fixing device, 51, 51a, 51b, 51c ... Light emitting element chip, 53 ... Rod lens array DESCRIPTION OF SYMBOLS 100 ... Light emitting element head 101 ... Bonding pad 102 ... Light emitting element 105 ... Substrate 110 ... Signal generating circuit 120 ... Light emitting part 130 ... Setting part 140 ... Control part 141, 142, 143, 144 ... Chip selector, 300 ... first NOT circuit, 301 ... second NOT circuit, 310 ... NOR circuit, 311 ... NAND circuit, 401, 401a, 411, 411a ... light emitting thyristor, 402,412 ... transfer thyristor, 403,413 ... Logic operation elements

Claims (8)

A substrate,
A first semiconductor layer stacked on the substrate and having a first conductivity type set to a first potential;
The second conductivity type is stacked on the first semiconductor layer and has a second conductivity type different from the first conductivity type, and the second bias is applied so that the junction with the first semiconductor layer is forward biased. A second semiconductor layer set at a potential;
A third semiconductor layer stacked on the second semiconductor layer, having the first conductivity type, and having an input electrode to which a signal is input from the outside;
A fourth semiconductor layer stacked on the third semiconductor layer, having the second conductivity type, and having an output electrode for outputting an inverted signal of the signal ,
A logic operation circuit in which a NOT circuit having the input electrode as an input and the output electrode as an output is configured by connecting the output electrode to the first potential via a load resistor . When the first conductivity type is p-type using holes as charge carriers and the second conductivity type is n-type using electrons as charge carriers,
The logical operation circuit includes a plurality of NOT circuits, and the first potential and the second potential of each NOT circuit are made common, and NOR of a signal input from the outside to each NOT circuit is set. The logical operation circuit according to claim 1, further comprising a NOR circuit for outputting. When the first conductivity type is n-type using electrons as charge carriers and the second conductivity type is p-type using holes as charge carriers,
The logical operation circuit includes a plurality of NOT circuits, and the first potential and the second potential of each NOT circuit are made common, and a NAND of a signal input from the outside to each NOT circuit is obtained. The logic operation circuit according to claim 1, further comprising a NAND circuit for outputting. A substrate,
A first semiconductor layer having a first conductivity type stacked on the substrate and a second semiconductor type stacked on the first semiconductor layer and having a second conductivity type different from the first conductivity type. Two semiconductor layers, a third semiconductor layer stacked on the second semiconductor layer and having the first conductivity type, a fourth semiconductor layer stacked on the third semiconductor layer and having the second conductivity type, and a light emitting unit including a plurality of light emitting device including a
The first semiconductor layer stacked on the substrate and set at a first potential and the first semiconductor layer stacked on the first semiconductor layer, and a junction between the first semiconductor layer is forward biased, A second semiconductor layer set at a second potential; a third semiconductor layer stacked on the second semiconductor layer and having an input electrode to which a signal is input from the outside; and the third semiconductor layer And a fourth semiconductor layer having an output electrode that outputs an inverted signal of the signal, and the output electrode is connected to the first potential via a load resistor, whereby the input electrode is A light-emitting element chip including a logic operation circuit configured with a NOT circuit having an output as an input and an output of the output electrode, and a control unit that controls light emission of the light-emitting unit.   Each of them is stacked on the substrate and has the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and corresponds to each of the plurality of light emitting elements. The light emitting device chip according to claim 4, further comprising: a setting unit provided with a plurality of setting elements that are set in an on state and set the corresponding light emitting elements in a state capable of emitting light. .   The first conductivity type is a p-type using holes as charge carriers, the second conductivity type is an n-type using electrons as charge carriers, and a logic operation circuit of the control unit of the light emitting element chip is A NOR circuit having a plurality of the NOT circuits, wherein the first potential and the second potential of each NOT circuit are made common, and a NOR of a signal input from the outside is output to each NOT circuit; The identification information unique to the light emitting element chip attached to the light emitting element chip and the identification information input from the outside of the light emitting element chip by combining the NOT circuit and the NOR circuit that do not constitute the NOR circuit And a control signal for causing the light emitting elements constituting the light emitting section to emit light is supplied to the light emitting section or the setting section. Light emitting device chip of claim 5. A substrate, a first semiconductor layer having a first conductivity type stacked on the substrate, and a second conductivity type stacked on the first semiconductor layer and having a conductivity type different from the first conductivity type A second semiconductor layer having a first conductivity type, a third semiconductor layer having a first conductivity type, and a fourth semiconductor layer having a second conductivity type, stacked on the third semiconductor layer. a semiconductor layer, a light emitting unit including a plurality of light emitting device including, stacked on the substrate, and the first semiconductor layer is set to a first potential, is stacked on the first semiconductor layer, said first A second semiconductor layer set at a second potential so that a junction between the first semiconductor layer and the first semiconductor layer becomes a forward bias; and an input electrode that is stacked on the second semiconductor layer and receives a signal from the outside. and said third semiconductor layer having been laminated on the third semiconductor layer, of the signal And a said fourth semiconductor layer having an output electrode for outputting a rotation signal, the output electrode via a load resistor that is connected to the first potential, and inputs the input electrode, the output electrode An exposure apparatus that includes a plurality of light emitting element chips including a logical operation circuit configured with an output NOT circuit and includes a control unit that controls the operation of the light emitting unit, and that exposes a charged image carrier. An image carrier,
Charging means for charging the image carrier;
A substrate, a first semiconductor layer having a first conductivity type stacked on the substrate, and a second conductivity type stacked on the first semiconductor layer and having a conductivity type different from the first conductivity type A second semiconductor layer having a first conductivity type, a third semiconductor layer having a first conductivity type, and a fourth semiconductor layer having a second conductivity type, stacked on the third semiconductor layer. a semiconductor layer, a light emitting unit including a plurality of light emitting device including a stacked on the substrate, and the first semiconductor layer is set to a first potential, is stacked on the first semiconductor layer, said first A second semiconductor layer set at a second potential so that a junction between the first semiconductor layer and the first semiconductor layer becomes a forward bias; and an input electrode that is stacked on the second semiconductor layer and receives a signal from the outside. and said third semiconductor layer having been laminated on the third semiconductor layer, of the signal Comprising a said fourth semiconductor layer having an output electrode for outputting a rotation signal, and the output electrode via a load resistor that is connected to the first potential, and inputs the input electrode, the output electrode NOT circuit to output includes a logic operation circuit which is configured, a plurality of light emitting device chips which Ru and a control unit for controlling the operation of the light emitting portion, the static by exposing the charged the image carrier Exposure means for forming an electrostatic latent image;
Developing means for developing the electrostatic latent image formed on the image carrier;
An image forming apparatus comprising: a transfer unit that transfers an image developed on the image carrier to a transfer target.

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