JP4885760B2 - Light emitting element array, light emitting device, and image forming apparatus - Google Patents

Description

  The present invention relates to a light-emitting element array including a plurality of light-emitting elements, a light-emitting device including the light-emitting element array, and an image forming apparatus including the light-emitting device.

  As a light emitting device used as an optical printer head such as an electrophotographic printer, there is an LED array formed by arranging a large number of light emitting diodes (abbreviated as LEDs). This LED array has a large number of bonding pads in order to individually connect the light emitting diode and the driving circuit. For example, when an electrophotographic printer is configured with an A3 size, 600 dpi (dot par inch) specification, the connection point between the bonding pad and the circuit wiring is when the anode or cathode of the LED is a common electrode by a conductive substrate. However, the same number as the light emitting elements is required, and the number is about 7300. For this reason, it takes a very long time to connect the two by a known wire bonding method, and it is difficult to improve productivity. Further, in order to form the bonding pad, a larger area than that for forming the light emitting element is required, and as the image to be formed by the electrophotographic printer becomes higher in definition, the light emitting element per unit length in the scanning direction is increased. As the number increases, the number of bonding pads also increases.

As a first conventional technique for reducing the number of bonding pads, there is a dynamic (time division) driving type light emitting element array. This is because the LED array is composed of n ₁ (m ₁ is a positive integer) group of m ₁ (m ₁ is a positive integer) LEDs, and the anode or cathode of the LED is common to each group. In this case, m ₁ × n ₁ matrix wiring is applied. In the dynamic (time division) driving, each LED is caused to emit light by switching the driving signal applied to the matrix wiring in a time division manner. When a dynamic drive type LED array is used, it is possible to reduce the number of bonding pads to about 1/4 compared to the LED array described above in which each LED and a drive circuit are individually connected (for example, patents). Reference 1).

As a second conventional technique, there is a dynamic drive type light emitting device that drives a light emitting element array formed by connecting field effect transistors to each LED in a time-sharing manner (see, for example, Patent Document 2). In this light emitting device, a driving IC (Integrated Circuit) having a built-in switching element composed of a NAND gate or the like is connected to the light emitting element array, and the switching element built in the driving IC is connected to a strobe signal (STB). ) And the gate signal, and the gate signal is output only while the strobe signal takes a true value, whereby the light emitting element array can be dynamically driven.

  As a third conventional technique, a light emitting thyristor having a PNPN structure is used as the light emitting element in order to reduce the area occupied by the wiring connected to the light emitting element, and either the anode or the cathode is shared by the conductive substrate. There is a light-emitting element array formed by connecting the other of the anode and the cathode and the gate electrode in a matrix (see, for example, Patent Documents 3 and 4). By connecting the gate electrode through which almost no current flows through the entire light emitting element array using the electrode wiring, the line width of the electrode wiring can be reduced and the area for forming the electrode wiring can be reduced.

JP 11-268333 A JP-A-6-177431 Japanese Patent No. 2807910 JP 2001-217457 A

However, in the first conventional technique, in order to connect m ₁ + n ₁ electrode wirings to the anode or cathode of the LED, any electrode wiring is proportional to the light emission intensity of the LED for causing the LED to emit light. Main current flows. In this case, if the wiring resistance is large, the power consumption of the driving IC increases due to the loss of the wiring resistance, or the driving performance deteriorates. Therefore, it is necessary to increase the electrode wiring width to some extent to reduce the wiring resistance. For this reason, there is a problem that the area for forming the electrode wiring increases, and the surface area of the chip on which the LED array is formed increases.

In the first to third conventional techniques, for example, when dynamic (time division) driving is performed using an m ₂ × n ₂ matrix wiring (where m ₂ and n ₂ are positive integers), One light emitting element array requires m ₂ + n ₂ electrode wiring. However, when a light-emitting device is configured using a plurality of light-emitting element arrays (p ₂ , p ₂ is an integer of 2 or more), p ₂ × (m ₂ + n ₂ ) in proportion to the number of light-emitting element arrays Electrode wiring is required. Further, the number of output terminals of the driving IC for driving the light emitting element array needs to be increased according to the number of necessary electrode wirings, and the number of terminals of the driving IC is equal to the number of terminals of one light emitting element array. In this case, as many driving ICs as the number of light emitting element arrays are required. Thus, when a light-emitting device is configured using a plurality of light-emitting element arrays, the conventional technique requires a large number of driving ICs, and the number of wirings connecting the light-emitting element arrays and the driving ICs increases. There is a problem that the entire apparatus becomes complicated or the apparatus becomes large.

  In addition, when light emitting elements are arranged at high density to obtain a high-definition image, the number of bonding pads increases with the conventional technology, but the wire pitch becomes difficult because the pad pitch becomes too narrow. Become. As a result, there is a problem that the density of the light emitting element is limited.

  In the second conventional technique, it is necessary to connect a driving IC incorporating a switching element such as a NAND gate to the light emitting element array. When a light-emitting device is configured using a plurality of light-emitting element arrays, the number of driving ICs connected to each light-emitting element array increases as the number of light-emitting element arrays increases. There is a problem of becoming.

  An object of the present invention is to provide a light emitting element array that can be driven in a time-sharing manner with a small number of driving ICs, and a light emitting element array suitable for increasing the density of light emitting elements by reducing the number of bonding pads. Is to provide. A further object of the present invention is to provide a small and high-definition light-emitting device using such a light-emitting element and an image forming apparatus including the light-emitting device.

The light emitting element array of the present invention includes: (a) a first switch unit that outputs a first selection signal and an output trigger signal when both a clock signal and an input trigger signal are provided as input signals;
(B) a first selection signal transmission path that is connected to the first switch section and transmits the first selection signal;
(C) Connected to the first selection signal transmission line and outputs a control signal when both the second selection signal and the first selection signal from the first selection signal transmission line are given as input signals n (N is an integer of 2 or more) second switch units;
(D) n control signal transmission lines that are individually connected to the n second switch units and transmit the control signal;
(E) A plurality of light emitting elements that are connected to any one of the n control signal transmission paths and emit light when both the light emission signal and the control signal from the connected control signal transmission path are provided as input signals. Including elements,
At least one of the light emitting elements is connected to each control signal transmission path.

Further, in the light emitting element array of the present invention, the plurality of light emitting elements constitute a plurality of light emitting element blocks including n or less light emitting elements,
A light emitting element block composed of a plurality of light emitting elements is characterized in that the plurality of light emitting elements are individually connected to different control signal transmission paths, and a common light emission signal is input to the plurality of light emitting elements. To do.

In the light emitting element array of the present invention, the plurality of light emitting elements are arranged in a line,
The light emitting element block is composed of n-1 (n is an integer of 4 or more) light emitting elements,
In the odd-numbered light emitting element block from one side to the other in the arrangement direction of the light emitting elements, the i ₁ (i ₁ is 1 or more and n in the light emitting element block from the one to the other in the arrangement direction). -1 or less integer) light-emitting element and j ₁ (j ₁ is an integer greater than or equal to 1 and less than or equal to n−1) control signal transmission line are connected so as to satisfy i ₁ = j ₁ And
In the even-numbered light emitting element block from the one side of the arrangement direction toward the other side, the i ₂ (i ₂ is 1 ₂₎ in the light emitting element block from the one side of the arrangement direction toward the other side. The above-mentioned and n−1 or less integer) light-emitting element and the j ₂ (j ₂ is an integer of 2 or more and n or less) -th control signal transmission line satisfy i ₂ + j ₂ = n + 1. It is connected to.

The light-emitting element array of the present invention includes a substrate and a bonding pad provided on one surface of the substrate,
The light emitting elements are provided on the one surface of the substrate and arranged in a substantially straight line,
The n control signal transmission lines and the first selection signal transmission line are provided on the one surface of the substrate along the arrangement direction of the light emitting elements,
The bonding pads are arranged to be spaced apart from each other along the arrangement direction of the light emitting elements,
An input trigger signal bonding pad connected to the first switch unit for inputting the input trigger signal;
A clock signal bonding pad connected to the first switch unit for inputting the clock signal;
The output trigger signal bonding pad connected to the first switch unit for outputting the output trigger signal;
A second selection signal bonding pad that is individually connected to each of the second switch units and for inputting the second selection signal;
A plurality of light emitting signal bonding pads connected to the light emitting elements included in each of the light emitting element blocks, individually provided to give the light emitting signal to each of the light emitting element blocks, and having a number smaller than the number of light emitting elements; Have
The first switch unit and the second switch unit may be disposed between adjacent bonding pads.

In the light emitting element array of the present invention, the input trigger signal bonding pad is provided at one end of the substrate along the arrangement direction of the light emitting elements.
The output trigger signal bonding pad may be provided at the other end of the substrate along the arrangement direction of the light emitting elements.

In the light-emitting element array according to the present invention, the first switch section includes a clock thyristor including a light-emitting thyristor and a trigger thyristor including a light-emitting thyristor, and each gate electrode of these thyristors has the first selection signal transmission path. Connected to
Each of the second switch units includes a switch thyristor including a diode and a light emitting thyristor, and a gate electrode of each switch thyristor is individually connected to the control signal transmission line, and the first switch via the diode. Connected to the selection signal transmission line,
Each light emitting element is composed of a light emitting thyristor composed of a light emitting thyristor, and a gate electrode of each light emitting thyristor is connected to any one of the control signal transmission lines,
The clock thyristor, the trigger thyristor, the switch thyristor, and the light emitting thyristor have either one of an anode and a cathode grounded in common, and the clock thyristor, the switch thyristor, and the light emitting thyristor have an anode and a cathode The other electrode is supplied with the clock signal, the second selection signal, and the light emission signal, respectively.
The clock thyristor is configured to change the voltage between the gate electrode and the ground when the input trigger signal is input to the gate electrode and the threshold voltage is lowered and the clock signal is input and transitions to the on state. Output to the first selection signal transmission line as one selection signal;
The trigger thyristor outputs a voltage between an anode and a cathode as the output trigger signal when the clock thyristor is on.
The switch thyristor is turned on when the first selection signal is input to the gate electrode and the threshold voltage is lowered through the diode biased in the forward direction, and the second selection signal is input. When the transition is made, the voltage between the gate electrode and the ground is output as a control signal to the control signal transmission line.

In the light emitting element array of the present invention, the first switch unit further includes a first resistor, and one end of the first resistor is connected to the first selection signal transmission path. A positive constant voltage is applied to the other end when the cathodes of the respective light emitting thyristors are commonly grounded, and a negative constant voltage is applied when the anodes of the respective light emitting thyristors are commonly grounded,
The second switch unit further includes a second resistor, and one end of the second resistor is connected to the gate electrode of the switch thyristor, and the diode is sequentially connected to the other end of the second resistor. A constant voltage is applied so as to be biased in the direction.

In the light-emitting element array according to the present invention, the first switch section includes a clock thyristor including a light-emitting thyristor and a trigger thyristor including a light-emitting thyristor, and a gate electrode of these thyristors is connected to the first selection signal transmission path. Connected,
Each of the second switch sections includes a selection thyristor composed of a light emitting thyristor and a switch thyristor composed of a light emitting thyristor, and the anode of the selection thyristor is connected to the gate electrode of the switch thyristor, and the gate of each selection thyristor An electrode is connected to the first selection signal transmission line, and a gate electrode of each switch thyristor is individually connected to the control signal transmission line,
Each light emitting element is constituted by a light emitting thyristor composed of a light emitting thyristor, and a gate electrode of each light emitting thyristor is connected to any one of the control signal transmission lines,
The clock thyristor, the trigger thyristor, the selection thyristor, the switch thyristor, and the light emitting thyristor have either one of an anode and a cathode grounded in common, and the clock thyristor, the switch thyristor, and the light emitting thyristor The clock signal, the second selection signal, and the light emission signal are respectively input to the other electrode of the anode and the cathode, and the other electrode of the selection thyristor is in the forward direction in synchronization with the clock signal. Is applied as a set signal,
The clock thyristor is configured to change the voltage between the gate electrode and the ground when the input trigger signal is input to the gate electrode and the threshold voltage is lowered and the clock signal is input to make a transition to the on state. Output to the first selection signal transmission line as one selection signal;
The trigger thyristor outputs a voltage between an anode and a cathode as the output trigger signal when the clock thyristor is on.
The switch thyristor has the second selection signal in a state where the voltage between the anode and the cathode of the selection thyristor that has been turned on by the first selection signal is input to the gate electrode and the threshold voltage is lowered. Is input to the control signal transmission line, the voltage between the gate electrode and the ground is output as the control signal to the control signal transmission line.

In the light emitting element array of the present invention, the first switch unit further includes a first resistor, and one end of the first resistor is connected to the first selection signal transmission path. A positive constant voltage is applied to the other end when the cathodes of the respective light emitting thyristors are commonly grounded, and a negative constant voltage is applied when the anodes of the respective light emitting thyristors are commonly grounded,
The second switch unit further includes a second resistor, and one end of the second resistor is connected to a gate electrode of the switch thyristor, and the other end of the second resistor is connected to the selection thyristor. The set signal is input so that the anode and the cathode are biased in the forward direction.

  In the light-emitting element array according to the present invention, the second selection signal input to each switch thyristor is provided via a third resistor connected to an anode or a cathode of each switch thyristor. To do.

  The light emitting element array of the present invention is characterized in that the first switch part, the second switch part and the light emitting element are composed of light emitting thyristors having the same layer structure.

  The light emitting element array of the present invention includes a light shielding means or a light reducing means for shielding or dimming light emitted from the light emitting thyristors constituting the first switch section and the second switch section. .

  In the light-emitting element array according to the present invention, the first and second resistors may be arranged from the side close to the substrate, one of a P-type or N-type first semiconductor layer and a second type of conductive type. Among the semiconductor films laminated in the order of two semiconductor layers and a third semiconductor layer of one conductivity type, the third semiconductor layer is used.

  The light emitting element array according to the present invention further includes a light shielding means or a light reducing means for covering the first and second resistors in order to shield or reduce light incident on the first and second resistors. It is characterized by being.

In the light-emitting device of the present invention, when the light-emitting element array includes a plurality of the second switch parts each including a diode and a switch thyristor, four or more light-emitting element arrays are arranged in a row. A light emitting element array group;
A plurality of clock signal transmission lines connected to at least one light emitting element array to supply the clock signal;
An input trigger signal drive circuit connected to the first switch portion of the light emitting element array provided at one end in the arrangement direction of the light emitting element array group and supplying the input trigger signal to the first switch portion. When,
A clock signal drive circuit connected to the plurality of clock signal transmission paths and supplying the clock signal individually to each clock signal transmission path;
A second selection signal driving circuit that is individually connected to each second switch section in each light emitting element array and supplies the second selection signal common to each light emitting element array for each second switch section;
A light emission signal drive circuit that is individually connected to each light emitting element block in each light emitting element array and supplies the light emission signal common to each light emitting element array for each light emitting element block;
In the light emitting element array group, the input trigger of the light emitting element array in which the output trigger signal of the light emitting element array arranged on the one end side in the arrangement direction is arranged adjacent to the other end side in the arrangement direction. Input as a signal,
Each light emitting element array adjacent along the arrangement direction is individually connected to the plurality of clock signal transmission paths.

In the light-emitting device of the present invention, when the light-emitting element array includes a plurality of the second switch units each including a selection thyristor and a switch thyristor, four or more light-emitting element arrays are arranged in a row. A light emitting element array group,
A plurality of clock signal transmission lines connected to at least one light emitting element array to supply the clock signal;
An input trigger signal drive circuit connected to the first switch portion of the light emitting element array provided at one end in the arrangement direction of the light emitting element array group and supplying the input trigger signal to the first switch portion. When,
A clock signal drive circuit connected to the plurality of clock signal transmission paths and supplying the clock signal individually to each clock signal transmission path;
A set signal drive circuit connected to the other electrode of the anode and cathode of the selection thyristor of each second switch portion of each light emitting element array and supplying the set signal common to the light emitting element arrays When,
A second selection signal driving circuit that is individually connected to each second switch section in each light emitting element array and supplies the second selection signal common to each light emitting element array for each second switch section;
A light emission signal drive circuit that is individually connected to each light emitting element block in each light emitting element array and supplies the light emission signal common to each light emitting element array for each light emitting element block;
The light emitting element array group includes the input trigger signal of the light emitting element array in which the output trigger signal of the light emitting element array arranged on the one end side in the arrangement direction is adjacent to the other side in the arrangement direction. Entered as
Each light emitting element array adjacent along the arrangement direction is individually connected to the plurality of clock signal transmission paths.

In the light-emitting device of the present invention, when the light-emitting element array includes a plurality of the second switch sections including a selection thyristor and a switch thyristor, the set signal drive circuit includes the clock signal. When the driving circuit for changing the clock signal transmission path to which the clock signal is supplied, a signal substantially equal to the potential of the common electrode is supplied, and then the set signal is supplied,
The second selection signal drive circuit and the light emission signal drive circuit supply the second selection signal and the light emission signal after the set signal drive circuit starts supplying the set signal, respectively. Features.

In the image forming apparatus of the present invention, when the light emitting element array includes a plurality of the second switch units each including a diode and a switch thyristor, the light emitting apparatus including a plurality of the light emitting element arrays;
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
Fixing means for fixing the developer transferred to the recording sheet,
The input trigger signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive circuit are configured to generate the input trigger signal, the clock signal, and the second selection based on image information. A signal and the light emission signal are supplied, respectively.

The image forming apparatus according to the present invention includes the light emitting device including a plurality of the light emitting element arrays when the light emitting element array includes a plurality of the second switch units each including a selection thyristor and a switch thyristor. ,
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
Fixing means for fixing the developer transferred to the recording sheet,
The input trigger signal drive circuit, the set signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive circuit are based on image information, The set signal, the clock signal, the second selection signal, and the light emission signal are supplied, respectively.

  According to the present invention, the light emitting element array includes the first switch unit that outputs the first selection signal and the output trigger signal when both the clock signal and the input trigger signal are input from the outside of the light emitting element array; When the second selection signal from the first selection signal and the first selection signal from the first switch unit are both input, n (n is an integer of 2 or more) second switch units that output a control signal, and external And a plurality of (n or more) light emitting elements that emit light when both the light emission signal from and the control signal from the second switch section are input.

  Here, paying attention to a signal input from the outside of the light emitting element array, a clock signal and an input trigger signal are input from the outside to a first switch unit provided for each light emitting element array, and the first switch A second selection signal is input from the outside to the second switch unit connected to the light emitting element connected to the light emitting element via the control signal transmission line. When a light emission signal is input from, the light emitting element can emit light. That is, in order for the light emitting element to emit light, all of the clock signal, the input trigger signal, the second selection signal, and the light emission signal need to be supplied from the outside. The element does not emit light.

  Accordingly, when a light-emitting device is configured by arranging a plurality of light-emitting element arrays in a line and the light-emitting elements belonging to each light-emitting element array emit light in a predetermined order, first, one light-emitting element array is provided for each light-emitting element array. A clock signal and an input trigger signal are individually given to one switch unit in a predetermined order. Accordingly, even if the same second selection signal and light emission signal are given among the plurality of light emitting element arrays, it is possible to select which light emitting element array to emit light (hereinafter, the first signal is the first signal). The input light emitting element array or the first switch portion of the light emitting element array is said to be in a selected state or a selected state). If the light emitting element array can be sequentially switched to the selected state, a second selection signal is given to the n second switch units in a predetermined order using a common wiring between the light emitting element arrays, By giving light emitting signals to the light emitting elements in a predetermined order, desired light emitting elements can be made to emit light sequentially.

  Here, the light emitting element array according to the present invention is configured so that the output trigger signal is output from the first switch unit when the clock signal and the input trigger signal are given. Can be transferred one after another as an input trigger signal of adjacent light emitting elements. Hereinafter, the input trigger signal and the output trigger signal are collectively referred to as a trigger signal. The direction in which the trigger signal is transferred is called the trigger transfer direction.

  Specifically, the output trigger signal of the light emitting element array arranged on one end side in the arrangement direction is arranged on the other end side in the arrangement direction between the light emitting element arrays adjacent to each other along the arrangement direction of the light emitting element array. The light emitting element arrays are arranged so as to be input as input trigger signals of adjacent light emitting element arrays, and the first input trigger signal is externally input to the light emitting element array at the one end in the arrangement direction. Further, at least two transmission lines for supplying a clock signal are provided so that clock signals are given to the light emitting element arrays adjacent to each other at different timings. Then, when the first input trigger signal and the clock signal are input to the one end light emitting element array, the output trigger signal is input as an input trigger signal to the light emitting element arrays adjacent in the arrangement direction. Next, when a clock signal is given to the adjacent light emitting element array, an output trigger signal is given as an input trigger signal to the light emitting element array further adjacent to the light emitting element array in the trigger transfer direction. In this manner, the trigger signal is sequentially transferred in synchronization with the timing at which the clock signal is supplied.

  As described above, according to the configuration of the light emitting element array of the present invention, by providing at least one input trigger signal driving IC and at least two clock signal driving ICs, a plurality of light emitting device arrays belong to the light emitting device. The light emitting element arrays can be selected in a predetermined order in the arrangement direction. Furthermore, the driving IC for supplying the second selection signal and the light emission signal, and the wiring between each light emitting element and the driving IC can be shared by a plurality of light emitting element arrays. Therefore, when the light emitting device is configured using the light emitting element array of the present invention, the driving IC and the wiring are shared between the light emitting element arrays by adding the driving IC and the wiring for supplying at least three signals. Therefore, a light emitting device configured with a small number of driving ICs and wirings can be realized.

  According to the invention, in order to reduce the number of wirings for supplying light emission signals to the plurality of light emitting elements, the plurality of light emitting elements constitute a light emitting element block including n or less light emitting elements. At this time, the light emitting element block composed of a plurality of light emitting elements is individually connected to the control signal transmission paths that are different from each other and given different control signals, and is further common to the plurality of light emitting elements. A light emission signal is provided. Here, when the entire light emitting element array is selected by the clock signal and the input trigger signal, when the second selection signal is sequentially applied to each second switch portion of the light emitting element array, The control signal is also transmitted in order to the control signal transmission path connected to the two switch units, and the control signal is also given in order to each light emitting element in each light emitting element block. Therefore, time-division driving in the light emitting element block can be realized by giving a common third signal to each light emitting element block in accordance with the timing at which the control signal is given.

  As described above, in the present invention, since the plurality of light emitting element blocks in the same light emitting element array can be time-division driven, the number of output terminals of the driving IC that supplies the light emission signal, and the driving IC and the light emitting element The number of wirings with the array can be reduced, and a small light emitting device with a small number of wirings can be realized. In addition, since the number of control signal transmission lines in the light emitting element array and the number of bonding pads for inputting light emitting signals can be reduced, a small light emitting element array capable of increasing the density of the light emitting elements can be realized.

According to the invention, the light emitting element block is composed of n-1 light emitting elements, which is 1 less than the number of control signal transmission lines (n: n is an integer of 4 or more). Here, the direction from the one along the arrangement direction of the other light emitting element (hereinafter, x of ₁ direction), the numbered from # 1 in order to light-emitting element blocks, further emission constituting each light emitting element blocks X _{1 in the} element
Numbers are assigned in order from the first to the (n-1) th, and numbers are assigned to the n control signal transmission lines from the first to the nth in a predetermined order. According to the present invention, in the odd-numbered light emitting element block, the i ₁ (1 ≦ i ₁ ≦ n−1) th light emitting element and the j ₁ (1 ≦ j ₁ ≦ n−1) th light emitting element block are provided. The control signal transmission path is connected so as to satisfy i ₁ = j _{1. In} the even-numbered light emitting element block, the i ₂ (1 ≦ i ₂ ≦ n−1) th light emitting element and the j ₂ ( 2 ≦ j ₂ ≦ n) the control signal transmission line is connected so as to satisfy i ₂ + j ₂ = n + 1.

In this case, the light emitting elements adjacent to the arrangement direction of the light emitting elements connected to the first control signal transmission path are connected to the second control signal transmission path. The light emitting elements adjacent to the arrangement direction of the light emitting elements connected to the j ₃ (2 ≦ j ₃ ≦ n−1) th control signal transmission line are j ₃ −1 th or j ₃ +1. It is connected to one of the control signal transmission lines. The light emitting elements adjacent to the arrangement direction of the light emitting elements connected to the nth control signal transmission path are connected to the (n-1) th control signal transmission path. Accordingly, the second selection signal is sequentially input to the second switch portion of the light emitting element array which is in the selected state when the clock signal and the input trigger signal are input, and the first to nth control signal transmission lines are connected to the second selection signal. When the control signals are output in order in the division, the time lag of the light emission timing of the light emitting elements adjacent to each other can be reduced, and further, the adjacent light emitting elements are not connected to the same control signal transmission path, It is possible to prevent the light emitting elements adjacent to the light from being emitted simultaneously.

  As a result, when the light-emitting device constituted by the light-emitting element array of the present invention is used as an exposure device that exposes the photosensitive drum, it is possible to prevent the timing of light emission between adjacent light-emitting elements from being greatly shifted. No discontinuity occurs at the exposure position where the photosensitive drum is exposed. Furthermore, by preventing the light emitting elements adjacent to each other from emitting light at the same time, it is possible to suppress unevenness in heat generation when each light emitting element emits light and to align the light emitting characteristics due to temperature changes of each light emitting element. Further, since it is possible to prevent light generated from light emitting elements adjacent to each other from interfering with each other, the photosensitive drum can be exposed with high accuracy. As a result, in the image forming apparatus using the light emitting element array of the present invention, a recorded image with excellent image quality can be obtained.

  Further, according to the present invention, the light emitting elements constituting the light emitting element array are arranged in a substantially straight line on one surface of the substrate (hereinafter, this surface is referred to as a main surface), and the n control signal transmissions are performed. The path is wired along the arrangement direction of the light emitting elements, and the bonding pad for supplying the clock signal, the input trigger signal, the second selection signal, and the light emission signal and outputting the output trigger signal is arranged in the arrangement of the light emitting elements. The first switch part and the second switch part are disposed between the adjacent bonding pads. Here, an input trigger signal bonding pad connected to the first switch unit for inputting an input trigger signal, and a clock signal bonding pad connected to the first switch unit for inputting a clock signal; At least one output trigger bonding pad connected to the first switch unit for outputting an output trigger signal is required for each light emitting element array. The number of second selection signal bonding pads that are individually connected to the second switch unit and individually supply the second selection signal is at least equal to the number of second switch units. Further, at least one light emitting signal bonding pad connected to the light emitting element included in each light emitting element block and supplying a light emitting signal individually for each light emitting element block is required for each light emitting element block, It is sufficient that the total number of light emitting signal bonding pads in the entire light emitting element array is smaller than the number of light emitting elements.

  Therefore, assuming that the number of light emitting element blocks is m and each light emitting element block is composed of n light emitting elements, at least the necessary bonding in the entire light emitting element array is required for the number of light emitting elements of m × n. Since the number of pads is m + n + 3, when a light emitting element array composed of a large number of light emitting elements is configured, the number of bonding pads is smaller than the number of light emitting elements, and a space is created between bonding pads. Therefore, the switch element can be arranged by effectively utilizing the space, and the increase in the size of the entire light-emitting element array can be avoided by providing the switch element. As a result, a small light-emitting element array can be obtained. realizable.

  According to the invention, the input trigger signal bonding pad is provided at one end of the substrate along the arrangement direction of the light emitting elements, and the output trigger signal bonding pad is provided at the other end. As described above, when a light emitting device is configured by arranging a plurality of light emitting element arrays in a row, one output trigger signal in the arrangement direction of the light emitting element arrays is input as the other input trigger signal between adjacent light emitting element arrays. Therefore, if the input trigger signal bonding pad is provided at one end of the substrate and the output trigger signal bonding pad is provided at the other end, the wiring for transferring the trigger signal can be shortened. Good.

  According to the present invention, the first switch part constituting the light emitting element array can include a clock thyristor and a trigger thyristor, and the second switch part includes a switch thyristor and a diode. In addition, the light emitting element can include a light emitting thyristor. Here, each light emitting thyristor constituting the first switch unit, the second switch unit, and the light emitting element is used as a common electrode (potential is Vg = 0 volts (V)). Here, when the cathode is a common electrode, an N gate electrode is used as the gate electrode of each light emitting thyristor constituting the light emitting element array, and when the anode is a common electrode, the gate electrode of each light emitting thyristor. A P gate electrode is used.

  Hereinafter, regarding a specific circuit configuration and operation in the case where the cathode is a common electrode, the first switch unit related to the transfer of the trigger signal between the light emitting element arrays constituting the light emitting device, and the inside of each light emitting element array The second switch part and the light emitting element related to the time division driving will be described separately.

  First, the first switch unit will be described. In the first switch unit, the gate electrodes of the clock thyristor and the trigger thyristor are connected to the first selection signal transmission path. Here, it is defined that a clock signal is input to the anode of the clock thyristor when a high level voltage is applied to the anode of the clock thyristor. Further, it is defined that an input trigger signal is input to the gate electrode of the clock thyristor when a low level voltage is applied to the gate electrode of the clock thyristor.

  When a light-emitting device is configured using a plurality of light-emitting element arrays, the trigger thyristor constituting the first switch unit has the anode of the adjacent light-emitting element array in order to transfer the trigger signal described above. A positive voltage is applied to the first selection signal transmission path of each light emitting element array via a pull-up resistor, for example, connected to the one selection signal transmission path. Then, since the anode of the trigger thyristor of each light emitting element array is connected to the first selection signal transmission path of the light emitting element array adjacent in the trigger transfer direction, a positive voltage is applied to the anode of the trigger thyristor. Further, the N gate electrode of the trigger thyristor is connected to the first selection signal transmission path, and the anode of the trigger thyristor is connected to the first selection signal transmission path of the light emitting element array adjacent in the trigger transfer direction. The first selection signal transmission lines of the adjacent light emitting element arrays are connected by a forward-biased PN junction diode.

  The operation when the light emitting device is configured as described above will be described more specifically. Here, it is assumed that a clock thyristor of a certain light-emitting element array is in an on-state by receiving a clock signal and an input trigger signal. Then, the light emitting element array is in a selected state, and the potential of the first selection signal transmission path is almost 0V. Here, the light emitting element array in the selected state is described as a light emitting element array (A), the light emitting element array adjacent in the trigger transfer direction is described as a light emitting element array (A), and further, with respect to the light emitting element array (A). A light emitting element array adjacent to the trigger transfer direction is referred to as a light emitting element array (c). As described above, since the potential of the first selection signal transmission path of the light emitting element array (A) is substantially equal to the diffusion potential of the PN junction, one diffusion potential is applied to the gate electrode of the clock thyristor of the light emitting element array (A). This is a state in which the threshold voltage is lowered by applying a low level potential for 1 minute. In this state, when a high level voltage is applied to the anode of the clock thyristor of the light-emitting element array (A), the clock thyristor can be turned on. That is, when the potential of the first selective transmission line of the light emitting element array (a) is substantially equal to the diffusion potential of the PN junction, the input trigger signal is applied to the gate electrode of the clock thyristor of the light emitting element array (a). In this state, when a clock signal is applied to the anode of the clock thyristor, the light emitting element array (A) can be turned on. Further, when the light emitting element array (a) transitions to the on state, the potential of the first selection signal transmission path of the light emitting element array (c) further adjacent in the trigger transfer direction from the light emitting element array (a) is the diffusion potential of the PN junction. Therefore, an output trigger signal is output from the light emitting element array (A) and is input to the light emitting element array (C) as an input trigger signal. In this way, the light emitting element array can be sequentially selected by applying the clock signal in accordance with the trigger signal transfer timing.

  Next, specific circuit configurations and operations of the second switch units and the light emitting elements will be described. In the light emitting element array in the selected state, as described above, the clock thyristor has transitioned to the on state, and the potential of the first selection signal transmission path is approximately 0V. This potential of 0V is used as a first selection signal input to the second switch unit.

  In each second switch unit, the gate electrode of the switch thyristor is individually connected to the corresponding control signal transmission path, and the gate electrode of the switch thyristor is further connected to the first selection signal transmission path via a diode. . Here, a positive voltage is applied to the gate electrode of the switching thyristor via a pull-up resistor, for example. Thus, when the first switch unit is not in the selected state, the voltage of the gate electrode of the switching thyristor is equal to a positive voltage. When the first switch unit is in the selected state and the first selection signal is input to the second switch unit, the gate potential of the switching thyristor is approximately the diffusion potential of the diode through the diode biased in the forward direction. A potential of minutes occurs. Accordingly, although the threshold voltage of the switch thyristor is in a lowered state, when the second selection signal is not input to the anode of the switch thyristor, that is, the low level voltage is applied to the anode of the switch thyristor. Sometimes the switch thyristor remains off. At this time, a potential approximately equal to the diffusion potential is generated in the control signal transmission line individually connected to the switch thyristor in the off state, and the gate of the light emitting thyristor whose gate electrode is connected to the control signal transmission line. A potential substantially equal to the diffusion potential is also generated in the electrode. In such a case, even if a high-level voltage is applied to the anode of the light emitting thyristor, that is, even if a light emission signal is applied to the anode of the light emitting thyristor, the light emitting thyristor transitions to the ON state. The signal level of the light emission signal is determined so as not to emit light.

  On the other hand, when the first selection signal is input to the second switch unit and the threshold voltage of the switch thyristor constituting the second switch unit is lowered, the second thyristor for the switch further has a high level second signal. When the selection signal is given, the switch thyristor is turned on. At this time, the potential of the control signal transmission line connected to the gate electrode of the switch thyristor is substantially 0 V, and the potential of the gate electrode of the light emitting thyristor whose gate electrode is connected to the control signal transmission line is also substantially 0 V. become. That is, a control signal of approximately 0 V is output from the gate electrode of the switch thyristor, transmitted through the control signal transmission path, and input to the light emitting thyristor. In such a case, when a high-level light emission signal is input to the anode of the light-emitting thyristor, the signal level of the light-emitting signal is determined so that the light-emitting thyristor shifts to the on state and emits light.

  As described above, when the high level clock signal and the input trigger signal substantially equal to the diffusion potential of the diode are input, the first selection signal of approximately 0V and the output trigger signal substantially equal to the diode diffusion potential are output. When the first switch unit, the first selection signal of approximately 0V, and the second selection signal of high level are input, the second switch unit that outputs a control signal of approximately 0V, and the control signal of approximately 0V and the high level A light emitting element that emits light when a level light emission signal is input can be realized using a light emitting thyristor. Also, when the anode of the light emitting thyristor is used as a common electrode, the polarity of the light emitting thyristor and the diode are reversed, the conductivity type of the gate electrode of the light emitting thyristor is reversed, and the polarity of the voltage applied to the gate electrode is reversed. Then, a similar logic circuit can be realized. Therefore, according to the present invention, a logic circuit that selectively emits light from a light-emitting element can be configured with a simple circuit configuration using a light-emitting thyristor without using a complicated semiconductor device such as a NAND gate or an inverter. Thus, a light-emitting element array that is easy to design and that has a simple manufacturing process can be realized.

  The pull-up resistor connected to the gate electrode of the switch thyristor operates the switch thyristor stably even when the current flowing through the control signal transmission path changes when a plurality of light emitting elements emit light simultaneously. It has the effect that it can be done.

  According to the invention, a constant voltage is applied to the first selection signal transmission line via the first resistor as a pull-up resistor. As a result, when the light emitting device is configured by connecting a plurality of light emitting element arrays as described above, the potential of the first selection signal transmission path is diffused by the PN junction diode between the light emitting element arrays adjacent in the trigger transfer direction. It can be varied by the potential. As a result, in the non-selected light emitting element array to which the clock signal and the input trigger signal are not applied, the clock thyristor is reliably maintained in the off state.

  A constant voltage is applied to the gate electrode of the switch thyristor via a second resistor as a pull-up resistor so that the diode is biased in the forward direction. As a result, the switch thyristor to which the first selection signal is not applied as described above is reliably maintained in the OFF state.

  According to the present invention, the second switch section includes a switch thyristor and a selection thyristor, and the diode of the second switch section is replaced with a selection thyristor. Other configurations are the same as those of the light-emitting element array described above. In the following, the difference in operation and effect between the diode and the selection thyristor will be described in the case where the cathode of each thyristor is a common electrode.

  Even when a selection thyristor is used instead of a diode in the second switch section, the first selection signal transmission path is connected to the N gate electrode of the selection thyristor, and the N gate electrode of the switch thyristor is the selection thyristor. This is the same in that the first selection signal transmission line and the gate electrode of the switch thyristor are connected via one PN junction diode. Therefore, the selection thyristor basically operates in the same manner as the above-described diode. However, when the light emitting thyristor transitions from the off state to the on state, the on state may be stored without transitioning to the off state even when the voltage of the gate electrode varies. In order to reset this state and shift the light-emitting thyristor to the on state in accordance with the fluctuation of the voltage of the gate electrode, it is necessary to reduce the potential difference between the anode and the cathode. Therefore, the anode of the selection thyristor is given a set signal to which a positive voltage is applied in almost all time zones, but once the clock signal is switched from a high level to a low level and from a low level to a high level, the anode is temporarily A set signal that is synchronized with the clock signal is applied such that the potential of is reset to 0V. Thus, similarly to the circuit configuration described above, a logic circuit that selectively causes the light emitting elements to emit light is configured with a simple circuit configuration using a light emitting thyristor without using a complicated semiconductor device such as a NAND gate or an inverter. Therefore, a light-emitting element array that is easy to design and that has a simple manufacturing process can be realized. Further, since the current flowing into the gate electrode of the selection thyristor is small, the line width of the first selection signal transmission path can be reduced. As a result, it is possible to reduce the size of the light emitting element array.

  According to the present invention, a constant voltage is applied to the first selection signal transmission line via a first resistor as a pull-up resistor, and a gate electrode of the switch thyristor is applied as a pull-up resistor. A constant voltage is applied via the second resistor so that the selection thyristor is forward-biased. The functions of the first resistor and the second resistor as the pull-up resistors are the same even if the diode of the second switch unit is replaced with a selection thyristor.

  According to the invention, in the configuration of the light emitting element array including the light emitting thyristor, the second selection signal is input to the anode or cathode of each switch thyristor via the third resistor.

  When a light-emitting device is configured using a light-emitting element array, for the purpose of speeding up, a clock signal and an input trigger signal may be simultaneously applied to the plurality of light-emitting element arrays to simultaneously select the plurality of light-emitting element arrays. it can. At this time, since the second selection signal is shared between the plurality of light emitting element arrays in the selected state, the plurality of switch thyristors are switched at the same time. In general, when the light-emitting thyristor is switched to be turned on, a main current flows between the anode and the cathode, so that the output voltage of the drive circuit for supplying the second selection signal decreases. Therefore, when the timing of the second selection signal input to the anodes of the plurality of switch thyristors is shifted, when the switch thyristor to which the second selection signal is input first switches and the main current flows, there is a delay. The switch thyristor to which the second selection signal is input may not be switched due to insufficient voltage of the second selection signal. Therefore, according to the present invention, by providing the second selection signal via the third resistor connected to the anode or the cathode of each switch thyristor, a decrease in the output voltage of the drive circuit is suppressed, and a plurality of switches The thyristor can be switched reliably.

  According to the invention, the semiconductor layers of the light emitting thyristors constituting the first switch portion, the second switch portion, and the light emitting element have the same layer configuration. In this case, since the semiconductor layers constituting each light-emitting thyristor can be formed at the same time in the same film forming process, the structure of the present invention in which a light-emitting thyristor for switching is provided in addition to a plurality of light-emitting elements for light-emitting. The manufacturing process is not complicated.

  According to the invention, there is also provided a light blocking means or a light reducing means for blocking or reducing light emitted from the light emitting thyristor constituting the first switch section, the second switch section, and the light emitting element. The light shielding means or the dimming means works so that light emitted when the switching light emitting thyristors used in the first switch unit and the second switch unit are switched does not enter the light emitting thyristor. It is possible to prevent fluctuation of the threshold voltage of the thyristor. Therefore, when the first switch unit, the second switch unit, and the light emitting element are configured by light emitting thyristors, the light emitting element array can be stably operated.

  According to the invention, the first and second resistors use a P-type semiconductor and an N-type semiconductor, and the third of the semiconductor layers stacked in order of NPN or PNP from the substrate side. It is composed of three semiconductor layers. Since each light emitting thyristor constituting the first switch unit, the second switch unit, and the light emitting element is configured using the first to fourth semiconductor layers stacked in order of NPNP or PNPN from the substrate, each light emitting thyristor The semiconductor layers for the first and second resistors can be formed on the same substrate on which is formed by the same film forming process. In this case, the first and second resistors are obtained by stacking four semiconductor layers of NPNP or PNPN and then etching the uppermost P-type or N-type semiconductor layer. Therefore, even if it is the structure of this invention provided with the 1st switch part containing a 1st resistor and the 2nd switch part containing a 2nd resistor other than a some light emitting element, a manufacturing process is complicated. There is no.

  The first and second resistors are formed of an N-type semiconductor layer when a cathode of each light-emitting thyristor is used as a common electrode, and a positive voltage is applied to the common electrode at one end thereof. . When the anode of each light-emitting thyristor is used as a common electrode, the first and second resistors are composed of a P-type semiconductor layer, and a negative voltage is applied to the common electrode at one end thereof. That is, since a reverse bias voltage is applied between the third semiconductor layer used as the first and second resistors and the adjacent second semiconductor layer, the depletion layer spreads and is shared. Insulation with respect to the electrode is ensured. Therefore, by configuring the first and second resistors as described above, an unnecessary current path is hardly generated, and the operation as the resistor can be stabilized.

  According to the present invention, as described above, when the first and second resistors are constituted by the third semiconductor layer, the light shielding means or the light reducing means is used to suppress the influence of light incident from the outside. A light shielding film is provided. When electron / hole pairs are generated by light incident on the interface of the semiconductor layer having the NPN or PNP structure provided with the first and second resistors, carriers are accumulated in the second semiconductor layer like the phototransistor. Therefore, the insulation at the interface between the second semiconductor layer and the third semiconductor layer is impaired, and the operation as a resistor becomes unstable. Therefore, by providing a light shielding unit or a light reducing unit, excitation by incident light at the interface of the semiconductor layer can be suppressed, and the operation of the first and second resistors can be stabilized.

  According to the invention, in the case where the light emitting element array includes a plurality of the second switch portions each including a diode and a switch thyristor, the light emitting element array is arranged to emit four or more light emitting elements arranged in a line. There is provided a light emitting device including an element array group and a drive circuit for supplying the clock signal, the input trigger signal, the second selection signal, and the light emission signal to each light emitting element array. As described above, by providing at least one input trigger signal drive circuit and at least two clock signal drive circuits, a plurality of light emitting element arrays included in the light emitting device are selected in a predetermined order in the arrangement direction. Can be in a state. Further, the light emitting device can be stably operated by time division driving in which the second selection signal driving circuit and the light emitting signal driving circuit are shared among the plurality of light emitting element arrays. Therefore, the number of driving circuits and the number of layers of the board on which the driving circuits are mounted can be reduced, and the area of the light emitting element array and the driving circuit mounting board can be reduced, resulting in a small and stable. A light emitting device that operates in a short time can be realized.

  According to the invention, when the light-emitting element array includes a plurality of the second switch sections each including a selection thyristor and a switch thyristor, four or more light-emitting element arrays are arranged in a line. There is provided a light emitting device including the light emitting element array group and a driving circuit for supplying the light emitting element array with the clock signal, the input trigger signal, the set signal, the second selection signal, and the light emitting signal. Also in this case, as described above, by providing at least one input trigger signal drive circuit and at least two clock signal drive circuits, a plurality of light emitting element arrays included in the light emitting device are predetermined in the arrangement direction. Can be selected in order. Further, the light emitting device can be stably operated by time division driving in which the second selection signal driving circuit and the light emitting signal driving circuit are shared among the plurality of light emitting element arrays. Therefore, the number of driving circuits and the number of layers of the board on which the driving circuits are mounted can be reduced, and the area of the light emitting element array and the driving circuit mounting board can be reduced, resulting in a small and stable. A light emitting device that operates in a short time can be realized.

  According to the invention, in the configuration of the light emitting device using the set signal drive circuit, when the clock signal drive circuit changes the supply destination of the clock signal, the set signal drive circuit supplies 0V equal to the common electrode. After the voltage is supplied and reset, supply of the set signal is started, and then the second selection signal and the light emission signal are supplied from the second selection signal drive circuit and the light emission signal drive circuit, respectively. If the second selection signal and the light emission signal are supplied before supplying the set signal, the light emitting element emits light without supplying the clock signal because the control signal transmission path is at a voltage of approximately 0V. Inconvenience occurs.

  According to the invention, when the light-emitting element array includes a plurality of the second switch portions each including a diode and a switch thyristor, an image using the light-emitting device including a plurality of the light-emitting element arrays is used. A forming apparatus is provided. In the image forming procedure, first, the light emitting device is driven by an input trigger signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive circuit based on image information. The light from the light emitting device is condensed on the charged photosensitive drum by the condensing means, whereby the photosensitive drum is exposed and an electrostatic latent image is formed on the surface thereof. Next, when the developer is supplied to the photosensitive drum on which the electrostatic latent image is formed by the developer supplying means, the developer adheres to the photosensitive drum and an image is formed. Finally, the image formed on the photosensitive drum is transferred to the recording sheet by the transfer unit, and the developer transferred to the recording sheet is fixed by the fixing unit to form an image on the recording sheet. The Since the light emitting device is small and has high reliability that operates stably, the image forming device can stably form a good image.

  According to the invention, when the light emitting element array is configured to include a plurality of the second switch units each including a selection thyristor and a switch thyristor, the light emitting device including a plurality of the light emitting element arrays, and a set An image forming apparatus further including a signal driving circuit is provided. The light emitting device is configured to drive the light emitting device based on image information into an input trigger signal drive circuit, the set signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive. By being driven by a circuit, it operates in the same manner as the light-emitting device described above. As a result, an image forming apparatus capable of stably forming a good image is realized in the same manner as the image obtaining and forming apparatus described above.

  Hereinafter, a light-emitting element array, a light-emitting device, and an image forming apparatus of the present invention will be described in detail with reference to the drawings. Here, in each of the following embodiments, a case where the cathode of the light emitting thyristor used in the light emitting element array is grounded as a common electrode is illustrated. Even when the anode of the light-emitting thyristor is grounded as a common electrode, the polarity of the light-emitting thyristor and the diode is reversed, the polarity of the voltage applied to the resistor is reversed, and the conductivity type of the gate electrode of the light-emitting thyristor is reversed. In this case, a similar logic circuit can be realized.

  FIG. 1 is a schematic equivalent circuit diagram showing a light emitting element array chip 1 as a first embodiment of the light emitting element array of the present invention.

  The light emitting element array chip 1 includes k (symbol k is a natural number) light emitting elements, one first switch unit, n second switch units, one select signal transmission line CSL, n The gate lateral wirings GH1 to GHn are included. Each of the k light emitting elements includes a light emitting thyristor. The first switch unit includes a clock thyristor CL formed of a light emitting thyristor, a trigger thyristor TR formed of a light emitting thyristor, and a first pull-up resistor RQ. The n second switch units include n switch thyristors S1 to Sn including light emitting thyristors, n selection thyristors U1 to Un including light emitting thyristors, and n second pull-up resistors RP1 to RPn. Including. In the present embodiment, n = 4. Hereinafter, the k light emitting elements may be referred to as light emitting thyristors T1 to Tk, respectively. In addition, a plurality of light emitting thyristors T1 to Tk, a plurality of switch thyristors S1 to Sn, a plurality of selection thyristors U1 to Un, and a plurality of second pull-up resistors RP1 to RPn are collectively referred to or unspecified. In some cases, the light-emitting thyristor T, the switch thyristor S, the selection thyristor U, and the second pull-up resistor RP may be described. In the present embodiment, the first pull-up resistor RQ corresponds to the first resistor, the second pull-up resistor RP corresponds to the second resistor, and the select signal transmission path CSL transmits the first select signal transmission. The horizontal gate line GH corresponds to the control signal transmission line.

  The clock thyristor CL constituting the first switch unit has an anode r connected to a clock signal input terminal CLA for clock signal input, an N gate electrode v connected to a select signal transmission line CSL, and a cathode as a common electrode. Grounded. The N gate electrode v may be simply referred to as a gate electrode v. In the trigger thyristor TR constituting the first switch unit, the anode q is connected to the trigger signal output terminal TRA for trigger signal output, the N gate electrode w is connected to the select signal transmission line CSL, and the cathode is a common electrode. As grounded. The N gate electrode w may be simply referred to as a gate electrode w. The first pull-up resistor RQ constituting the first switch unit has one end connected to the select signal transmission line CSL and the other end to which a positive voltage Vcc is applied. Here, the select signal transmission path CSL is used as a transmission path for the select signal as the first selection signal described above, and is connected to the trigger signal input terminal CSG. The trigger signal input terminal CSG is used for inputting an input trigger signal.

  In the switch thyristors S1 to S4 constituting the second switch unit, anodes c1 to c4 and N gate electrodes d1 to d4 are used as electrodes for controlling the operation. The cathode of the switch thyristor S is grounded as a common electrode. Similarly, the anodes c1 to c4 and the N gate electrodes d1 to d4 may be simply referred to as the anode c and the N gate electrode d when referring to a plurality of elements or when referring to an unspecified one. In some cases, the N gate electrode d is simply referred to as a gate electrode d. The selection thyristors U1 to U4 constituting the second switch section use anodes e1 to e4 and N gate electrodes f1 to f4 as electrodes for controlling the operation. The cathode of the selection thyristor U is grounded as a common electrode. Similarly, the anodes e1 to e4 and the N gate electrodes f1 to f4 are sometimes simply referred to as the anode e and the N gate electrode f when referring to a plurality of elements or indicating an unspecified one. In some cases, the N gate electrode f is simply referred to as a gate electrode f.

The N gate electrodes d1 to d4 of the switching thyristors S1 to S4 are individually connected to the anodes e1 to e4 of the selection thyristors U1 to U4, one end of the second pull-up resistors RP1 to RP4, and the gate lateral wirings GH1 to GH4, respectively. The Reference numerals of elements connected to each other are denoted by the same reference numerals. For example, the N gate electrode d1 of the first switch thyristor S1 is connected to the anode e1, the first second pull-up resistor RP1, and the first gate horizontal wiring GH1 of the first selection thyristor U1. The The _{i 4 (1 ≦ i 4 ≦} n, except n = 4) th N gate electrode di ₄ of the switch thyristor Si ₄ is the i ₄ th anode ei ₄ selection thyristor Ui _4, second pull-up The resistor RPi ₄ and the gate horizontal wiring GHi ₄ are connected. Further, the N gate electrodes f1 to f4 of the selection thyristor U are electrically connected to each other by being connected to the select signal transmission line CSL. The other end of the second pull-up resistor RP is connected to a set signal input terminal CSA to which a common set signal is input. The control signal output from the N gate electrode d of the switch thyristor S is transmitted to the gate horizontal wiring GH.

  The anodes c1 to c4 of each switch thyristor S are individually connected to the gate signal input terminals G1 to G4, respectively. As a preferred configuration, current limiting resistors RI1 to RI4 are connected between the anodes c1 to c4 of the switch thyristor S and the gate signal input terminals G1 to G4, respectively. When the plurality of gate signal input terminals G1 to G4 and the current limiting resistors RI1 to RI4 are collectively referred to or unspecified, they may be simply referred to as the gate signal input terminal G and the current limiting resistor RI, respectively. In the present embodiment, the gate signal corresponds to the second selection signal, and the current limiting resistor RI corresponds to the third resistor.

  The light emitting thyristors T1 to Tk constituting the light emitting element employ anodes a1 to ak and N gate electrodes b1 to bk as electrodes for controlling the operation thereof. The cathodes of the light emitting thyristors T are grounded as a common electrode. Similarly, the anodes a1 to ak and the N gate electrodes b1 to bk may be simply referred to as the anode a and the N gate electrode b when referring to a plurality of elements or referring to an unspecified one. In some cases, the N gate electrode b is simply referred to as a gate electrode b.

The light emitting thyristor T used as the light emitting element is composed of m light emitting element blocks B1 to Bm, and one light emitting element block is composed of a group of n or less light emitting thyristors T. Here, when collectively referring to the plurality of light emitting element blocks B1 to Bm or indicating an unspecified one, the light emitting element block B may be simply described. The number of light-emitting thyristors T constituting one light-emitting element block B needs to be n or less. In this embodiment, n = 4, and the number of light-emitting thyristors T constituting all the light-emitting element blocks is set to n (= 4). Therefore, the relationship between the number k of light emitting thyristors T and the number m of light emitting element blocks B is k = 4 m. The light emitting thyristors T are numbered from No. 1 to No. k from one to the other along the arrangement direction of the light emitting thyristors T, and each light emitting element block also has the number from the one in the arrangement direction. When the numbers from 1 to m are assigned to the other side, the i ₅ (1 ≦ i ₅ ≦ m) th light emitting element block Bi ₅ is assigned to the 4i ₅ −3th to 4i _5th . The light-emitting thyristor T belongs.

Each light emitting element block B1 to Bm is individually provided with light emitting signal input terminals A1 to Am for inputting light emitting signals. The light emission signal input terminals A1 to Am may be simply referred to as the light emission signal input terminal A when a plurality of light emission signal input terminals A1 to Am are collectively referred to or unspecified. The light emitting thyristors T constituting each light emitting element block B are electrically connected to each other by connecting the anode a to the common light emitting signal input terminal A for each light emitting element block B. Further, the N gate electrodes b of the light emitting thyristors T constituting each light emitting element block B are respectively connected to different gate lateral wirings GH. In the present embodiment, the light emitting thyristors T are numbered from No. 1 to No. k from one to the other along the arrangement direction of the light emitting thyristors T, and the one along the arrangement direction from the one to the other. The light emitting element block B is numbered from No. 1 to m, and the numbers from No. 1 to No. 4 are assigned in the wiring order of the gate lateral wiring, so that i ₆ (1 ≦ i ₆ ≦ in m) th light emitting element blocks Bi _6, a gate electrode of the 4i ₆ -3 -th light emitting thyristor T4i ₆ -3 is connected to the first horizontal gate line GH1, a 4i ₆ -2 -th light emitting thyristor The gate electrode of T4i ₆ -2 is connected to the second gate horizontal wiring GH2, the gate electrode of the 4i ₆ -1th light emitting thyristor T4i ₆ -1 is connected to the third gate horizontal wiring GH3, and the fourth i _6th light emitting thyristor T 4i ₆ gate electrodes are respectively connected to the fourth gate horizontal wiring GH4. Further, the _{i 6 (1 ≦ i 6 ≦} m) th anode a of all of the light emitting thyristor T belonging to the light-emitting element block Bi ₆ are connected to a common light emission signal input terminal Ai _6.

  Next, the configuration and operation of the light emitting thyristor T used in the light emitting element array chip 1 will be described.

  In general, a light emitting thyristor is a semiconductor element having a PNPN structure in which direct transition type P-type semiconductors and N-type semiconductors are alternately stacked, and has negative resistance characteristics similar to those of a reverse blocking three-terminal thyristor. If each semiconductor layer is a first semiconductor layer (N type), a second semiconductor layer (P type), a third semiconductor layer (N type), and a fourth semiconductor layer (P type) in order from the cathode side to the anode side, The N gate electrode is a control electrode provided in the third semiconductor layer (N type), and the P gate electrode is a control electrode provided in the second semiconductor layer (P type). An N gate electrode is used when the cathode is grounded as a common electrode, and a P gate electrode is used when the anode is grounded. Which type of gate electrode is used depends on whether the anode or the cathode is used as a common electrode. If a common electrode is determined, it may be simply referred to as a gate electrode.

  FIG. 2 is a graph showing a forward voltage-current characteristic that is a relationship between the anode voltage and the anode current of the light emitting thyristor T. The anode voltage represents the anode potential when the cathode potential is 0 (zero) volts (V), and the anode current represents the current flowing into the anode. In FIG. 2, the horizontal axis represents the anode voltage, and the vertical axis represents the anode current. FIG. 2 also shows a load line 70. Since the threshold voltage of the light-emitting thyristor T is lowered by giving a control signal to the gate electrode b, the operating point is in an off state where the characteristic curve 71 representing the forward voltage-current characteristic and the load line 70 intersect. Light is emitted by transition from the point q2 to the point q1 in the on state where the characteristic curve 71 and the load line 70 intersect. A main current flows between the anode and the cathode at the point q1 in the on state.

  The operation of the light emitting thyristor T will be described specifically using numerical values. Here, when the cathode potential is 0 volt (V), when the anode voltage is high (H) level, a potential of 5 V is applied to the anode a, and when the anode voltage is low (L) level, 0 V is applied to the anode a. A potential shall be applied. When the voltage of the gate electrode b is high (H) level, a potential of 5 V is applied to the gate electrode b, and when the voltage of the gate electrode b is low (L) level, a potential of 0 V is applied to the gate electrode b. To do. In the light emitting thyristor T, when the anode voltage is high (H) level, it is said that a light emission signal is input to the light emitting thyristor T. When the voltage of the gate electrode b is low (L) level, the light emitting thyristor T It is said that a control signal is input to.

  First, when the voltage of the gate electrode b is high (H) level, the potential of the gate electrode b is 5V. Therefore, in order to flow the anode current, the third semiconductor layer ( It is necessary to apply a potential higher to the anode a by the forward drop voltage (diffusion potential) of the diode formed by the N-type) and the fourth semiconductor layer (P-type). The forward drop voltage is about 1.5V when the light emitting thyristor is made of GaAs or AlGaAs. Therefore, even if the anode voltage is set to the high (H) level, the light emitting thyristor T is turned off at the point q2 and does not emit light. That is, even if a light emission signal is input, if the control signal is not input, the light emitting thyristor T does not emit light. Next, when the voltage of the gate electrode b is at a low (L) level, the potential of the gate electrode b is 0 V. Therefore, in order to flow the anode current, the third semiconductor layer is more than the potential of 0 V of the gate electrode b. It is necessary to apply a potential higher to the anode a by the forward drop voltage of the diode formed by the (N type) and the fourth semiconductor layer (P type). Accordingly, when the anode voltage is set to a high (H) level, the light emitting thyristor T is turned on at the point q1, and an anode current flows to emit light. That is, when both the light emission signal and the gate signal are input, the light emitting thyristor T emits light.

  The configuration and operation of the switch thyristor S, the selection thyristor U, the clock thyristor CL, and the trigger thyristor TR can be described in the same manner as in the case of the light emitting thyristor T.

  Next, the operation of the schematic equivalent circuit diagram of the light emitting element array chip 1 shown in FIG. 1 will be described. The functions of the light emitting element array chip 1 are the first switch part related to the function of transferring the trigger signal, the second switch part related to time-division driving and light emission in each light emitting element array, and the light emitting thyristor T. Can be divided. In the following, first, the operation of the second switch unit and the light emitting thyristor T will be described with reference to FIGS. 3 to 5, and then the operation of the first switch unit will be described with reference to FIGS. 6 and 7. To do.

  3 is a part of the equivalent circuit diagram shown in FIG. 1 for explaining the operation of each second switch section and the light emitting thyristor T constituting the light emitting element chip array L1, and is a light emitting thyristor T1. FIG. 4 shows the connection between the switch thyristor S1 and the selection thyristor U1 and the wiring. Portions corresponding to those in FIGS. 3 and 1 are denoted by the same reference numerals, and description thereof is omitted. Here, in FIG. 3, load resistors RL1 and RL2 having a magnitude of 100Ω are provided between the light emission signal input terminal A1 and the light emission signal output terminal λ1 and between the gate signal input terminal G1 and the gate signal output terminal μ1. Provided. Further, the magnitude of the second pull-up resistor RP1 is set to 2 kΩ, and 5V is input as a set signal to the other end of the second pull-up resistor RP. Note that the current limiting resistor RI illustrated in FIG. 1 is illustrated as a more preferable configuration, and thus is not used in FIG. 3 and FIG. 5 described later. Regardless of the presence or absence of the current limiting resistor RI, the basic operation of the light emitting element array chip 1 is the same.

  FIG. 5 is a graph showing an example of measurement results of operating characteristics in the light emitting element array chip 1 of the present embodiment. The horizontal axis represents time (unit: microsecond (μs) / div), and the vertical axis represents the potential of each terminal (unit: volts (V) / div). 3 and 5, the thick solid line indicates the potential of the gate electrode d1 of the switch thyristor S1, the thin solid line indicates the potential of the select signal transmission line CSL, and the thick broken line indicates the anode of the switch thyristor S1. The potential of c1 and the thin broken line indicate the potential of the anode a1 of the light emitting thyristor T1, respectively. Here, the measurement is performed for the first light-emitting thyristor T1, the switch thyristor S1 and the selection thyristor U1 shown in FIG. 3, but the same results are obtained for the other second and subsequent elements. . In some cases, the voltage between the terminal and the ground is simply referred to as the terminal voltage. In this case, the terminal potential and the terminal voltage have the same meaning.

  In the measurement of the operating characteristics shown in FIG. 5, when the voltage of the light emission signal output terminal λ1 is high (H) level, the light emission signal output terminal λ1 outputs a voltage of 2.5V, and when the voltage is low (L) level, 0V. Is output. As described above, when the voltage of the light emission signal output terminal λ1 is high (H) level, the light emission signal is applied to the anode a of the light emitting thyristor T. When the voltage of the gate signal output terminal μ1 is high (H) level, the gate signal output terminal μ1 outputs a potential of 3.5V, and when it is low (L) level, it outputs a voltage of 0V. When the voltage of the gate signal output terminal μ1 is high (H) level, the gate signal is applied to the anode c of the switching thyristor S. When the voltage of the select signal transmission line CSL is high (H) level, a potential of 5V is applied to the select signal transmission line CSL, and when it is low (L) level, a potential of 0V is applied. When the voltage of the select signal transmission line CSL is at a low (L) level, the select signal is transmitted through the select signal transmission line CSL and applied to the gate electrode f of the selection thyristor U. During measurement, a voltage of 5 V is applied as a set signal between the other end of the second pull-up resistor RP1 and the ground. The size of the load resistances RL1 and RL2 and the second pull-up resistor RP1, which are other parameters, is set to be the same as that shown in FIG. The current limiting resistor RI is not used.

  First, in the time zone tm1 shown in FIG. 5, the voltage of the gate signal output terminal μ1 connected to the switch thyristor S1 is set to high level (3.5V), and the voltage of the select signal transmission line CSL is set to low level ( 0V), and the voltage of the light emission signal output terminal λ1 connected to the light emitting thyristor T1 is set to a high level (2.5V).

  In this case, as indicated by a thin solid line, the potential of the select signal transmission line CSL is approximately 0V, and the set signal input terminal CSA is 5V. Therefore, the selection thyristor U1 is in the ON state. If the switch thyristor S1 and the light-emitting thyristor T1 are in the OFF state, the potential of the gate electrode d1 indicates about 1.6 V, which is the diffusion potential of the selection thyristor U. In the time zone t1, Since the high-level (3.5 V) gate signal is supplied to the anode c1 of the switching thyristor S1, the switching thyristor S1 transitions to the ON state. As a result, the potential of the gate electrode d1 indicated by the thick solid line is almost 0V. At this time, since the gate electrode d1 of the switching thyristor S1 and the gate electrode b1 of the light emitting thyristor T1 are connected by the gate horizontal wiring GH1, the potential of the gate electrode b1 of the light emitting thyristor T1 also shows substantially 0V. It will be. This means that a low level (0 V) control signal is input from the gate electrode d1 of the switching thyristor S1 via the gate horizontal wiring GH1 to the gate electrode b1 of the light emitting thyristor T1. Furthermore, a high level (2.5 V) light emission signal is also applied to the anode a1 of the light emitting thyristor T1, and this value is about 1.5 V (the potential of the gate electrode b1) which is the threshold voltage in this case. 0V and a value obtained by adding about 1.5 V of the forward drop voltage described above), the light-emitting thyristor T1 also shifts to the ON state and emits light. Thus, when the light emitting thyristor T1 is in the ON state, the potential of the anode a1 of the light emitting thyristor T1 indicated by the thin broken line indicates about 1.8 V that is the drive voltage level of the light emitting thyristor T. The difference from the voltage of the light emission signal output terminal λ1 at the high level (2.5 V) corresponds to the magnitude of the voltage drop in the load resistor RL1 generated due to the main current flowing from the anode c1 to the cathode of the light emitting thyristor T. Further, the potential of the anode c1 of the switch thyristor S1 indicated by a thick broken line indicates about 2 V that is the drive voltage level of the switch thyristor S when the switch thyristor S1 is turned on. The difference from the voltage of the high level (3.5 V) gate signal output terminal μ1 is a voltage drop in the load resistor RL2.

  Next, in the time zone tm2 shown in FIG. 5, the voltage of the gate signal output terminal μ1 connected to the switch thyristor S1 is set to low level (0V), and the potential of the select signal transmission line CSL is set to low level (0V). ) And the voltage of the light emission signal output terminal λ1 connected to the light emitting thyristor T1 is set to a high level (2.5 V).

Also in this case, as shown by a thin solid line, the potential of the select signal transmission line CSL is almost 0 V, so that the selection thyristor U1 is biased in the forward direction. However, unlike the time zone t1, the voltage of the gate signal output terminal μ1 connected to the anode c1 of the switching thyristor S1 is low level (0 V), so that the anode c1 of the switching thyristor S1 indicated by a thick broken line is shown. The potential is 0 V, and the switch thyristor S1 is in an off state. Therefore, the potential of the gate electrode d1 of the switching thyristor S1 indicated by the thick broken line is about 1.6 V, which is the diffusion potential in the ON state of the selection thyristor U, and the light emitting thyristor T1 connected to the gate electrode d1. The potential of the gate electrode b1 is also about 1.6V. A high level (2.5 V) light emission signal is applied to the anode a1 of the light emitting thyristor T1. In this case, the threshold voltage of the light emitting thyristor T1 is about 3 V (the potential of the gate electrode b1). Since it is lower than the value obtained by adding about 1.5 V of the forward drop voltage described above to 1.6 V), the state is turned off. Therefore, the potential of the anode a1 of the light emitting thyristor T1 indicated by the thin broken line indicates 2.5 V that is the voltage of the light emitting signal output terminal λ1.

  Next, in the time zone tm3 shown in FIG. 5, the voltage of the gate signal output terminal μ1 connected to the switch thyristor S1 is set to a high level (3.5 V), and the potential of the select signal transmission line CSL is set to a high level. The voltage of the light emission signal output terminal λ1 connected to the light emitting thyristor T1 is set to a high level (2.5V).

  In this case, as indicated by a thin solid line, the potential of the select signal transmission line CSL is approximately 5V. Although the potential of the gate electrode d1 of the switch thyristor S1 indicated by the thick solid line is also approximately 5V, the experimental result shown in FIG. 5 shows a potential of 3 to 5V in the time zone tm3 due to the CR time constant. . A high level (3.5 V) gate signal is applied to the anode c1 of the switch thyristor S1, but the threshold voltage becomes higher than the voltage level of the gate signal because the potential of the gate electrode d1 is high, and the switch thyristor. S1 is turned off. Therefore, the potential of the anode c1 of the switching thyristor S1 indicated by the thick broken line indicates 3.5 V that is the voltage of the gate signal output terminal μ1. Similarly, a high level (2.5 V) light emission signal is given to the light emitting thyristor T1, but since the potential of the gate electrode b1 connected to the gate electrode d1 of the switch thyristor S1 is high, the light emitting thyristor T1 is light emitting. The thyristor T1 is turned off. Therefore, the potential of the anode a1 of the light emitting thyristor T1 indicated by the thin broken line indicates 2.5 V that is the voltage of the light emitting signal output terminal λ1.

  Finally, in the time zone tm4 shown in FIG. 5, the voltage of the gate signal output terminal μ1 connected to the switch thyristor S1 is set to low level (0V), and the potential of the select signal transmission line CSL is set to high level (5V). ) And the voltage of the light emission signal output terminal λ1 connected to the light emitting thyristor T1 is set to a high level (2.5 V).

  In this case, as indicated by the thin solid line, the select signal transmission line CSL is approximately 5V, and the potential of the gate electrode d1 of the switch thyristor S1 indicated by the thick solid line is also approximately 5V. Further, since the voltage of the gate signal output terminal μ1 connected to the anode c1 of the switch thyristor S1 is low level (0V), the potential of the anode c1 of the switch thyristor S1 indicated by the thick broken line indicates 0V. The thyristor S1 is in an off state. On the other hand, a high level (2.5 V) light emission signal is given to the light emitting thyristor T1, but since the potential of the gate electrode b1 connected to the gate electrode d1 of the switch thyristor S1 is as high as 5 V, the light emission is performed. The thyristor T1 is turned off. Therefore, the potential of the anode a1 of the light emitting thyristor T1 indicated by the thin broken line indicates 2.5 V that is the voltage of the light emitting signal output terminal λ1.

  As described above, in the time zone tm1, when the potential of the select signal transmission line CSL is low level (0 V), the gate signal is applied to the anode c1 of the switch thyristor S1, thereby the switch thyristor S1. The potential of the gate electrode d1 becomes low level (0V). Since the gate electrode b1 of the light emitting thyristor T1 is connected to the gate electrode d1 of the switching thyristor S1 by the gate horizontal wiring GH1, the potential of the gate electrode b1 of the light emitting thyristor T1 is also 0V. When a light emission signal is given to the anode a1 of the light emitting thyristor T1, the light emitting thyristor T1 can emit light.

  FIG. 4 is a logic circuit diagram representing the equivalent circuit diagram shown in FIG. 3 with logic circuit diagram symbols. Table 1 summarizes the truth tables of the circuits shown in FIGS. In Table 1, when the output is high (H) level, the light emitting thyristor T1 emits light, and when the output is low (L) level, the light emitting thyristor T1 is off. As can be seen from Table 1, only when the potential of the select signal transmission line CSL is low (L) level, the gate signal input terminal G1 is high (H) level, and the light emission signal input terminal A1 is high (H) level. The light emitting thyristor T1 can selectively emit light.

The same applies to the light-emitting element array chip 1 shown in FIG. As will be described later, when a clock signal and an input trigger signal are given to the first switch portion of the light emitting element array chip 1, the potential of the select signal transmission line CSL becomes almost 0V. This state is the selected state. Since the gate electrode d of each switch thyristor S of the light emitting element array chip 1 is connected to the common select signal transmission line CSL via the corresponding individual selection thyristor U, the common select signal transmission line CSL When a low level select signal is input to the gate electrode f of the selection thyristor U, the potentials of the gate electrodes d1 to d4 of all the switch thyristors S1 to S4 are the diffusion potential levels of the selection thyristors U1 to U4 (about 1). .6V). At this time, the gate signal to the _{i 7 (1 ≦ i 7 ≦} 4) th gate signal input anode ci ₇ from the terminal Gi ₇ the i ₇ th switch thyristor Si ₇ has been entered the input The i-th _7th switch thyristor Si ₇ is turned on. Then, the voltage of the gate electrode di ₇ of the i ₇ th switch thyristor Si ₇ becomes substantially 0V, as a result, the i ₇ th horizontal gate line GHi ₇ connected to its gate electrode di _7, and The voltage of the gate electrode b of the light emitting thyristor T connected to the i _7th gate horizontal wiring becomes approximately 0V. This means that a low level (0 V) control signal is input from the gate electrode di ₇ of the switching thyristor Si ₇ to the gate electrode b of the light emitting thyristor T by transmitting the gate horizontal wiring GHi ₇ . Further, by giving a light emission signal to the anode a of the light emitting thyristor T connected to the i _7th gate horizontal wiring GHi ₇ , the light emitting thyristor T can be made to emit light selectively.

  As described above, when a low level (approximately 0 V) select signal is input to the gate electrode f of the selection thyristor U in the light emitting element array chip 1 in the selected state, the gate signal of the switch thyristor S is the anode. The switch thyristor S input to c transitions to the ON state. When the switching thyristor S transitions to the ON state, the potential of the gate electrode d becomes 0V, and the potential of the gate electrode b of the light emitting thyristor T connected to the switching thyristor S by the gate lateral wiring GH also becomes zero. In this state, when a light emission signal is input to the anode a of the light emitting thyristor T, the light emitting thyristor T shifts to the on state and emits light. When the light emitting element array chip 1 is not in the selected state, even if a gate signal is input to the anode c of the switching thyristor S of the light emitting element array chip 1, the switching thyristor S does not transition to the on state. Therefore, even if a light emission signal is given to the anode a of the light emitting thyristor T connected to the switch thyristor S by the gate lateral wiring GH, the light emitting thyristor T cannot emit light. In this way, the clock signal and the input trigger signal are given to the first switch portion of the light emitting element array chip 1 to place the light emitting element array chip 1 in the select state, whereby the gate signal is changed from the switching thyristor S to the light emitting thyristor T. In the light emitting device using a plurality of light emitting element array chips, the light emitting signal and the gate signal can be shared between the light emitting element array chips and the time division driving can be performed. .

  Further, in the light emitting element array chip 1 shown in FIG. 1, since the anode a is connected to the common light emission signal input terminal A in the light emitting element block B, dynamic driving can be realized also in the light emitting element array chip 1. . In FIG. 1, the light emission signal is input to a light emission signal input terminal A installed for each light emitting element block B. The light emission signal is given to the anodes a of all the light emitting thyristors T of the selected light emitting element block B, but the light emitting thyristors T belonging to the same block are connected to different gate horizontal wirings GH. The light-emitting thyristor T that emits light can selectively emit light.

  In this way, since the gate horizontal wiring GH can be shared by the plurality of light emitting element blocks B, time division driving can be performed between the plurality of light emitting element blocks, and the number of light emitting thyristors T is large. In addition, the number of gate lateral wirings GH can be reduced, and the chip width can be reduced. In addition, since the number of gate horizontal wirings GH is reduced, the number of switch thyristors S can be reduced and the configuration can be simplified.

  Further, in the light emitting element array chip 1 shown in FIG. 1, as a preferred configuration, there is a current between the anodes c1, c2, c3, and c4 of the switching thyristor S and the gate signal input terminals G1, G2, G3, and G4. Limiting resistors RI1 to RI4 are connected. When a light-emitting device is configured using a light-emitting element array, a clock signal and an input trigger signal are simultaneously applied to a plurality of light-emitting element array chips 1 for the purpose of speeding up, and the plurality of light-emitting element array chips 1 are simultaneously selected. Can be in a state. At this time, since the gate signal is shared between the plurality of light emitting element array chips 1 in the selected state, the plurality of switch thyristors S are switched at the same time. In general, when the light emitting thyristor is switched to be turned on, a main current flows between the anode and the cathode, so that the output voltage of the drive circuit for supplying the gate signal decreases. Therefore, when the timing of the gate signal input to the anodes c of the plurality of switch thyristors S is shifted, when the switch thyristor S to which the gate signal is input first switches and the main current flows, the gate is delayed. The switch thyristor S to which a signal is input may not be switched due to insufficient voltage of the gate signal. Therefore, by applying a gate signal via the current limiting resistor RI connected to the anode c of each switch thyristor S, a decrease in the output voltage of the drive circuit is suppressed, and a plurality of switch thyristors are switched reliably. Can do.

  In the above-described measurement shown in FIGS. 3 and 5, the set signal is a constant voltage of 5V. However, when the light emitting element array chip 1 is actually operated, the set signal is interrupted and 0V is applied to the set signal input terminal CSA. And the selection thyristor U1 is reliably reset to the off state.

  Next, in the light emitting element array chip L1 shown in FIG. 1, a specific configuration and operation of the first switch unit related to the transfer of the trigger signal will be described.

FIG. 6 is an equivalent circuit diagram showing the connection relationship of the first switch portions of each light emitting element array chip 1 when four or more light emitting element array chips 1 are arranged in a line to form a light emitting device. Since FIG. 6 shows a part of the equivalent circuit diagram shown in FIG. 1, the corresponding parts are denoted by the same reference numerals and description thereof is omitted. In FIG. 6, numbers are assigned in order from the first in the arrangement direction of the light emitting element arrays, and in the case of showing the light emitting element arrays in a specific order, the reference numerals are appended with numbers to distinguish them. . For example, the i ₁₇ (i ₁₇ is a natural number) light emitting element array chip 1 in the arrangement direction is referred to as an i _17th clock thyristor CLi ₁₇ .

  As shown in FIG. 6, when a light emitting device is configured using four or more light emitting element array chips 1, a plurality of clock signal transmission paths are provided so that the light emitting element array chips 1 adjacent to each other are different. A clock signal with a predetermined timing is input. FIG. 6 illustrates a case where two clock signal transmission paths CLL1 and CLL2 (reference numerals are collectively referred to or simply referred to as CLL when indicating an unspecified one) are illustrated. From the output terminals φ1 and φ2 of the driving IC that supplies the clock signal to the two clock signal transmission lines CLL1 and CLL2, voltages in which the high (H) level and the low (L) level are inverted from each other are output. It is assumed that the clock signal is supplied when the voltage at the clock signal output terminals φ1 and φ2 is high (H) level. Load resistors RC1 and RC2 are connected to the clock signal output terminals φ1 and φ2, respectively, and a clock signal is supplied to the clock thyristor CL of each light emitting element array chip 1 through the load resistors RC1 and RC2. Here, the anode r1 of the first clock thyristor CL1 is connected to the first clock signal transmission path CLL1, and the anode r2 of the second clock thyristor CL2 is connected to the second clock signal transmission path CLL2. Connected. Similarly, the odd-numbered clock thyristor CL is connected to the first clock signal transmission line CLL1 and the even-numbered clock thyristor CL is connected to the second clock signal transmission line CLL2 along the arrangement direction of the light emitting element array. Connected to. Thus, the anodes r of the clock thyristors CL of the light emitting element array chips 1 adjacent to each other are respectively connected to different clock signal transmission paths CLL, and clock signals with different timings are given thereto.

Further, as shown in FIG. 6, the anode q1 of the first trigger thyristor TR1 is connected to the second trigger signal input terminal CSG2, and the anode q2 of the second trigger thyristor TR2 is the third trigger thyristor TR2. The trigger signal input terminal CSG3 is connected. Similarly, in the two light emitting element array chips 1 adjacent to each other, the anode q of the trigger thyristor TR on the side close to the first light emitting element array chip 1 is connected to the trigger signal input terminal CSG on the far side. Connected. With this connection, a positive voltage Vcc is applied to the anode q of the trigger thyristor TR of each light emitting element array chip 1. Further, the first trigger signal input terminal CSG1 is connected to the N gate electrode w1 of the first trigger thyristor TR1, and the second trigger signal input terminal CSG2 is the anode q1 of the first trigger thyristor TR1. The first trigger signal input terminal CSG1 and the second trigger signal input terminal CSG2 are configured by the anode q1 and the N gate electrode w1 of the first trigger thyristor TR1. It is connected via a PN junction diode. Similarly, the second trigger signal input terminal CSG2 and the third trigger signal input terminal CSG3 are formed by a PN junction diode formed by the anode q2 and the N gate electrode w2 of the second trigger thyristor TR2. Connected. In this way, the i ₁₇ (i ₁₇ is a natural number) th trigger signal input terminal CSGi ₁₇ in the order of arrangement of the light emitting element array chip 1 is the anode qi ₁₇ and the N gate electrode of the i ₁₇ th trigger thyristor TRi _17. It is connected to the (i ₁₇ +1) th trigger signal input terminal CSGi ₁₇ +1 through a PN junction diode constituted by wi ₁₇ .

  Next, in the equivalent circuit diagram shown in FIG. 6, the principle that the input trigger signal input to the trigger signal input terminal of the first light emitting element array chip 1 is sequentially transferred in the arrangement order of the light emitting element array chip 1 will be described. To do.

FIG. 7 is a timing chart showing the operation of the equivalent circuit diagram shown in FIG. 6. The horizontal axis represents the elapsed time from the reference time, and the vertical axis represents the voltage or current magnitude of each terminal. In FIG. 7, the voltage waveforms of the output terminals φ1 and φ2 of the driving IC for supplying the clock signals transmitted through the clock signal transmission paths CLL1 and CLL2, and the input trigger signal are supplied to the first trigger signal input terminal CSG1. 2 shows the voltage waveform at the output terminal φS of the driving IC and the voltage waveforms at the trigger signal input terminals CSG1 to CSG4 of the first to fourth light emitting element array chips 1. Clock signal output terminals φ1 and φ2 and input trigger signal output terminal φS output a constant voltage of 5 V when they are high (H) level, and output a constant voltage of 0 V when they are low (L) level.

The operation of the equivalent circuit diagram shown in FIG. 6 will be described in order of the passage of time with reference to FIG. At time t0, the clock signal output terminals φ1 and φ2 are at the low (L) level and the input trigger signal output terminal φS is at the high (H) level, so that the clock thyristor CL of any light emitting element array chip 1 is also turned off. State. At this time, the voltage of the trigger signal input terminals CSG1 to CSG4 is equal to the positive voltage Vcc applied to the other end of the first pull-up resistor RQ.

  At the next time t1, the voltage of the output terminal φ1 that supplies the clock signal to the first clock signal transmission line CLL1 becomes high (H) level, and the voltage of the input trigger signal output terminal φS becomes low (L) level. become. At this time, a high (H) level voltage is applied to the anode r1 of the first clock thyristor CL1, and a low (level) voltage is applied to the gate electrode v1. This state corresponds to a clock signal being input to the anode r1 of the clock thyristor CL1 and an input trigger signal being input to the gate electrode v1. Then, since the first clock thyristor CL1 is turned on, the potential of the first trigger signal input terminal CSG1 becomes almost 0V. At this time, the first light emitting element array chip 1 is said to be in a selected state. Since the potential of the gate electrode w1 of the first trigger thyristor TR1 is also substantially 0 V, the first trigger thyristor TR1 is also turned on. Further, since the first clock thyristor CL1 is turned on and the main current flows between the anode r1 and the cathode, a voltage drop occurs in the load resistor RC1 connected to the first clock signal output terminal φ1. As a result, the potential of the first clock signal transmission line CLL1 is substantially equal to Vd of the drive voltage of the first clock thyristor.

  As described above, since the second trigger signal input terminal CSG2 is connected to the first trigger signal input terminal CSG2 via the forward-biased PN junction diode, the potential is PN junction. Is equal to the diffusion potential Vd (approximately 1.5 V). Further, since the potential of the third trigger signal input terminal CSG3 is higher than the potential of the second trigger signal input terminal CSG2 by the diffusion potential Vd of the PN junction, the potential is substantially equal to 2 × Vd, and similarly The potential of the fourth trigger signal input terminal CSG4 is approximately equal to 3 × Vd. Of course, the potential of the trigger signal input terminal CSG does not exceed the positive voltage Vcc. In the present embodiment, a potential substantially equal to the diffusion potential of the PN junction corresponds to the voltage levels of the input trigger signal and the output trigger signal. Therefore, at time t1, the output trigger signal is output from the anode q1 of the first trigger thyristor TR1, and is input as the input trigger signal to the gate electrode v2 of the second clock thyristor CL2. It has been transferred.

  At the next time t2, the voltage of the second clock signal output terminal φ2 becomes high (H) level and the input trigger signal output terminal φS becomes high (H) level. At this time, since the voltage of the first clock signal output terminal φ1 remains at the high (H) level, the first clock thyristor CL1 maintains the on state. Therefore, the potential of the first trigger signal input terminal CSG1 remains almost 0V. On the other hand, the second clock thyristor CL2 is turned on since a high (H) level voltage is applied to the anode r2 and a potential substantially equal to the diffusion potential Vd of the PN junction is applied to the gate electrode v2. Transition. Then, since the second trigger signal input terminal CSG2 is connected to the gate electrode v2 of the second clock thyristor CL2 that is in the ON state, the potential thereof is approximately 0V. Further, since the third trigger signal input terminal CSG3 is connected to the second trigger signal input terminal CSG2 via a forward-biased PN junction, its potential is substantially equal to Vd. Further, the potential of the fourth trigger signal input terminal CSG4 is substantially equal to 2 × Vd. At time t2, this corresponds to the clock signal being input to the anode r2 of the second clock thyristor CL2, the input trigger signal being input to the gate electrode v2, and the clock thyristor CL2 being turned on.

  Here, at time t2, the gate electrode v3 of the third clock thyristor CL3 is supplied with a potential substantially equal to Vd, but the third clock thyristor CL3 transitions to the ON state. do not do. This is because, as described above, the voltage drop at the load resistor RC1 decreases until the potential of the first clock signal transmission line CLL1 becomes substantially equal to Vd, so the anode r3 of the third clock thyristor CL3. This is because the potential of is substantially equal to Vd. Since the potential of the anode q1 of the first trigger thyristor TR1 is equal to the potential of the second trigger signal input terminal CSG2 and is substantially 0 V, the first trigger thyristor TR1 shifts to the off state. On the other hand, since the potential of the gate electrode w2 of the second trigger thyristor TR2 is equal to the second trigger signal input terminal CSG2 and 0 V, the second trigger thyristor TR2 is turned on.

  At the next time t3, the voltage of the first clock signal output terminal φ1 becomes low (L) level. At this time, since a low (L) level voltage is applied to the anode r1 of the first clock thyristor CL1, the first clock thyristor CL1 transitions to the off state. Then, the first trigger signal input terminal CSG1 becomes equal to the positive voltage Vcc given through the first first pull-up resistor RQ1. Here, the reason why the voltage of the first clock signal output terminal φ2 is changed behind the second clock signal output terminal φ2 is to ensure the transfer of the trigger signal described above.

  At the next time t4, the voltage of the first clock signal output terminal φ1 becomes high (H) level. At this time, a high (H) level voltage is applied to the anode r3 of the third clock thyristor CL3, and the potential of the gate electrode v3 of the third clock thyristor CL3 is substantially equal to Vd from time t2. Therefore, the third clock thyristor CL3 shifts to the on state. Then, the potential of the third trigger signal input terminal CSG3 connected to the gate electrode v3 of the third clock thyristor CL3 becomes approximately 0 volts. As described above, the potential of the fourth trigger signal input terminal CSG4 connected to the third trigger signal input terminal CSG3 through the PN junction biased in the forward direction is substantially equal to Vd. Further, since the potential of the anode q2 of the second trigger thyristor TR2 is equal to the potential of the third trigger signal input terminal CSG3 and is substantially 0 V, the second trigger thyristor TR2 shifts to the off state. On the other hand, since the potential of the gate electrode w3 of the third trigger thyristor TR3 is equal to the third trigger signal input terminal CSG3 and 0 V, the third trigger thyristor TR3 is turned on.

  At the next time t5, the voltage of the second clock signal output terminal φ2 becomes low (L) level. At this time, since a low (L) level voltage is applied to the anode r2 of the second clock thyristor CL2, the second clock thyristor CL2 transitions to the off state. Then, the second trigger signal input terminal CSG2 becomes equal to the positive voltage Vcc applied through the second first pull-up resistor RQ2.

  Similarly, at time t6, the fourth clock thyristor CL4 transitions to the on state and enters the select state, and at time t7, the third clock thyristor CL3 transitions to the off state to select. It is no longer in a state.

  As described above, the trigger signals are sequentially transferred in the order of the arrangement direction of the light emitting element array chips 1, and the clock signal is given in accordance with the timing, whereby the light emitting element array chip 1 is selected in the order of the arrangement direction. A logic circuit is realized. In the present embodiment, a plurality of light emitting element array chips 1 are sequentially selected along the arrangement direction using a total of three signal output terminals, that is, an input trigger signal output terminal φS and clock signal output terminals φ1 and φ2. In other words, time division driving between a plurality of light emitting element array chips is possible. Therefore, a light emitting device configured with a small number of driving ICs and wirings can be realized.

Next, the configuration of the light emitting element array chip 1 of the present embodiment will be specifically described.
FIG. 8 is a partial plan view showing the basic configuration of the light-emitting element array chip 1 of the first embodiment. This figure shows the plane of the light emitting element array chip 1 arranged with the light emitting direction of each light emitting thyristor T as the front side perpendicular to the paper surface. The gate horizontal wirings GH1 to GH4, the select signal transmission line CSL, the set signal Transmission path 11, set signal bonding pad CSA, input trigger signal bonding pad CSG, light emitting thyristor T, switch thyristor S, first pull-up resistor RQ, second pull-up resistor RP, selection thyristor U, for clock The thyristor CL and the trigger thyristor TR are indicated by hatching for easy illustration.

  The plurality of light emitting thyristors T included in the light emitting element array chip 1 are arranged with an interval W1 therebetween. The light emitting thyristor T is a light emitting element for exposure. In the present embodiment, the light emitting thyristors T are arranged at equal intervals and in a straight line. Hereinafter, the arrangement direction X of the light emitting thyristors T may be simply referred to as the arrangement direction X. A direction along the light emission direction of each light emitting thyristor T is defined as a thickness direction Z, and a direction perpendicular to the arrangement direction X and the thickness direction Z is defined as a width direction Y. The light emitting thyristor T is formed so as to emit light having a wavelength of 600 nm to 800 nm.

  Since the light emitting thyristor T is formed by a light emitting thyristor having a PNPN structure, the light emitting thyristor T can be realized with a simple configuration in which P-type semiconductors and N-type semiconductors are alternately stacked, and the device can be easily manufactured. As described above, the light emitting thyristor T applies the control signal to the gate electrodes b1 to bk, so that the light emitting signal is applied to the anodes a1 to ak in a state where the threshold voltage is lower than the voltage of the light emitting signal. Emits light when hit.

The light emitting thyristors T1 to Tk are divided into light emitting element blocks B1 to Bm, and the anodes a of the light emitting thyristors T belonging to the same light emitting element block B are connected to a bonding pad as a common light emitting signal input terminal A. A bonding pad as the light emission signal input terminal A may be simply referred to as a light emission signal bonding pad A. Further, in the present embodiment, four light emitting thyristors T equal to the number of the gate horizontal wirings GH constitute one light emitting element block B. For example, from one to the other along the arrangement direction of the light emitting thyristors T, the light emitting thyristors T are numbered from No. 1 to k, and from the one along the arrangement direction to the other, If the number to the light emitting element block B subjected from No. 1 to No. m-th, the _{i 6 (1 ≦ i 6 ≦} m) th light emitting elements from the 4i ₆ -3 th belonging to the block Bi ₆ first 4i ₆ th A connection portion 60 is provided between the anodes a of all the light emitting thyristors T4i ₆ -3 to T4i ₆ and the light emitting signal bonding pads Ai ₆ to be electrically connected. The anode a of the light emitting thyristor T, the light emitting signal bonding pad A, and the connection portion 60 are integrally formed at the same time. Further, in the present embodiment, as a preferred configuration, the light emitting signal bonding pad A is disposed along the arrangement direction X of the light emitting thyristor T on the opposite side of the light emitting thyristor T with the gate horizontal wiring GH interposed therebetween.

  The interval W1 between the light emitting thyristors T in the arrangement direction X and the length W2 in the arrangement direction X of the light emitting thyristors T depend on the resolution of an image to be formed in an image forming apparatus 87 described later on which the light emitting element array chip 1 is mounted. For example, when the resolution of the image is 600 dot per inch (dpi), the interval W1 is selected to be about 24 μm (micrometer), and the length W2 is selected to be about 18 μm.

  Each gate horizontal wiring GH extends in the arrangement direction X along the light emitting element array chip 1 from one end to the other end in the arrangement direction X of the light emitting element array chip 1. Each gate horizontal wiring GH is arranged at intervals in the width direction Y. In the present embodiment, the gate horizontal wiring GH4, the gate horizontal wiring GH3, the gate horizontal wiring GH2, and the gate horizontal wiring GH1 are arranged in order from the side close to the light emitting thyristor T. Further, in the present embodiment, the select signal transmission line CSL for supplying the select signal to the gate electrode f of the selection thyristor U is arranged in parallel to the gate lateral wiring GH1 on the side away from the light emitting thyristor T. . The select signal transmission line CSL is connected to a bonding pad as a trigger signal input terminal CSG via a connection unit 75. A bonding pad as the trigger signal input terminal CSG may be simply referred to as an input trigger signal bonding pad CSG. As a preferred configuration, the input trigger signal bonding pad CSG is provided at one end in the arrangement direction X on the substrate, following the arrangement of the light emission signal bonding pads A. With this arrangement, when configuring a light-emitting device that drives a plurality of light-emitting element array chips 1, a connection for inputting an output trigger signal output from an adjacent light-emitting element array chip 1 as an input trigger signal is provided. It becomes easy. Further, the interval W3 between the gate horizontal lines GH and between the gate horizontal line GH1 and the select signal transmission line CSL is between the gate horizontal lines GH adjacent to each other and between the gate horizontal line GH1 and the select signal transmission line CSL. The distance is selected so as not to cause a short circuit, for example, 5 μm.

In the present embodiment, the gate electrodes b1 to bk of the light emitting thyristor T are configured by the third semiconductor layer 24, and the connecting portions GV1, GV2, GV3, and GV4 are formed between any one of the gate lateral wirings GH1 to GH4. Is done. Here, from one to the other along the arrangement direction of the light emitting thyristors T, the light emitting thyristors T are numbered from the first to the kth, and the light emitting elements from the one to the other in the arrangement direction. If the blocks B are numbered from No. 1 to m-th, the i ₆ (1 ≦ i ₆ ≦ m) -th light emitting element block Bi ₆ along the arrangement direction will be described.
For the 4i ₆ −3 th to 4i ₆ th light-emitting thyristors T belonging to, the 4i ₆ −
Connecting portion GV1 is formed the third gate electrode of the light emitting thyristor T4i ₆ -3 between a first horizontal gate line GH1, the gate electrode of the 4i ₆ -2 -th light emitting thyristor T4i ₆ -2 And the second gate horizontal wiring GH2 is formed with a connection portion GV2, and the fourth i ₆ -1
Th connecting unit GV3 between the gate electrode and the third horizontal gate line GH3 of the light emitting thyristor T4i ₆ -1 is formed, the gate electrode and the fourth of the 4i ₆ -th light emitting thyristor T4i ₆ A connecting portion GV4 is formed between the gate horizontal wiring GH4. Further, between the anodes a of all the light emitting thyristors T belonging to the i ₆ (1 ≦ i ₆ ≦ m) th light emitting element block Bi ₆ and the i _6th light emitting signal input terminal Ai ₆ along the arrangement direction. The connection portion 60 is formed in the above. As described above, the light emitting thyristors T belonging to the same light emitting element block B are connected to the different gate horizontal wirings GH, so that the light emitting thyristors T can be dynamically driven as described above.

  The switch thyristor S is preferably arranged in a space formed between the light emitting signal bonding pads A. Since one light-emitting element block B composed of a plurality of light-emitting thyristors T is provided with one bonding pad for supplying a light-emitting signal, a space is generated between the light-emitting signal bonding pads A, and the space It is possible to arrange switch elements and the like by effectively utilizing the above. A bonding pad as a gate signal input terminal G for supplying a gate signal to the anode c of each switch thyristor S is also arranged utilizing the space generated between the bonding pads. A bonding pad as the gate signal input terminal G may be simply referred to as a gate signal bonding pad G. In the present embodiment, the gate signal bonding pad G corresponds to the second selection signal bonding pad. The anode c and the gate signal bonding pad G are integrally formed. With this arrangement, even if a switch thyristor S is provided, it is possible to avoid an increase in the size of the entire light emitting element array chip, and a small light emitting element array chip can be configured. . The number n of switch thyristors S is equal to the number of gate horizontal wirings GH, and n = 4 in the present embodiment. Further, the selection thyristor U is also disposed in the vicinity of the switch thyristor S by utilizing the space generated between the bonding pads as the light emission signal input terminal A.

  In the present embodiment, the gate electrode d of the switch thyristor S is composed of the third semiconductor layer 34. A connection portion 65 is formed between the gate electrode d of the switch thyristor S and the anode e of the selection thyristor U, and a connection portion 66 is also formed between the gate electrode d and the corresponding gate horizontal wiring GH. To be electrically connected. The connecting portion 65 that connects the gate electrode d and the selection thyristor U and the connecting portion 66 that connects the gate electrode d and the gate lateral wiring GH are integrally formed. Further, the N gate electrode f1 of the selection thyristor U is configured by the third semiconductor layer 44, and a connection portion 67 is formed between the N gate electrode f1 of the selection thyristor U and the select signal transmission line CSL.

  In the present embodiment, the second pull-up resistor RP is formed integrally with the switch thyristor S by using a part of the semiconductor layer constituting the switch thyristor S. The second pull-up resistor RP uses the sheet resistance of the semiconductor film. A connection portion 68 is formed between a part of the second pull-up resistor RP and the set signal transmission line 11, and a set signal is given to the connection portion 68 side of the second pull-up resistor.

  The set signal transmission path 11 is wired in parallel with the gate horizontal wiring GH, and in this embodiment, the set signal transmission path 11 is disposed on the side away from the gate horizontal wiring GH with the light emitting signal bonding pad A interposed therebetween. The set signal transmission path 11 is electrically connected to the bonding pad as the set signal input terminal CSA by the connecting portion 69. A bonding pad as the set signal input terminal CSA may be simply referred to as a set signal bonding pad CSA.

  The bonding pad as the trigger signal output terminal TRA for outputting the output trigger signal from the trigger thyristor TR is arranged in the arrangement direction X in order to facilitate the connection for transferring the trigger signal between the adjacent light emitting element array chips 1. Are preferably provided at the other end on the opposite side of the input trigger signal bonding pad CSG. In some cases, the bonding pad is simply referred to as an output trigger signal bonding pad TRA as the trigger signal output terminal TRA. The trigger thyristor TR is provided close to the output trigger signal bonding pad TRA. The anode q of the trigger thyristor TR is formed integrally with the output trigger signal bonding pad TRA. The gate electrode w of the trigger thyristor TR is constituted by the third semiconductor layer 154 and is connected to the select signal transmission line CSL via the connection portion 144.

  The clock thyristor CL and the bonding pad (clock signal bonding pad CLA) as the clock signal input terminal CLA are arranged between the plurality of light emitting signal bonding pads A, and these configurations are the trigger thyristor TR and the output trigger signal. The configuration is the same as that of the bonding pad TRA for use. Specifically, the anode r of the clock thyristor CL and the clock signal bonding pad CLA are integrally formed, and the third semiconductor layer used as the gate electrode v is connected via the select signal transmission line CLS and the connection portion 143. Connected.

  The first pull-up resistor RQ uses a sheet resistance of a semiconductor film, and is formed between a plurality of light emitting signal bonding pads A using a part of a semiconductor layer constituting each thyristor. One end portion of the first pull-up resistor RQ is connected to the select signal transmission line CSL via the connection portion 142, and the other end portion of the first pull-up resistor RQ is bonded to the power source for applying the positive voltage Vcc. Connected to pad Vs.

  Anode a of light emitting thyristor T, anode c of switching thyristor S, anode e of selection thyristor U, anode r of clock thyristor, anode q of trigger thyristor, horizontal gate line GH, select signal transmission line CSL, set Signal transmission path 11, connection portions 60, 65 to 69, 75, 142 to 144, GV1 to GV4, light emitting signal bonding pad A, gate signal bonding pad G, input trigger signal bonding pad CSG, output trigger signal bonding The pad TRA, the set signal bonding pad CSA, the power supply bonding pad Vs and the clock signal bonding pad are formed of a conductive material such as a metal material and an alloy material. Specifically, it is formed of gold (Au), an alloy of gold and germanium (AuGe), an alloy of gold and zinc (AuZn), nickel (Ni), aluminum (Al), or the like.

  The light-emitting element array chip 1 shown in FIG. 8 is preferably configured to shield light from the switching thyristor S, the selection thyristor U, the clock thyristor CL, and the trigger thyristor TR as light shielding means. A film 12 is provided. The switch thyristor S and the selection thyristor U emit light at the time of switching in the same manner as the light emitting thyristor T. However, the light emission is unnecessary, and light emitted by the light emission enters the light emitting thyristor T and emits light. This is because it is necessary to avoid changing the threshold value of the thyristor T for use. As the light shielding film 12, the surface may be covered with a member made of a material opaque to the light emission. When an appropriate interlayer insulating film is applied, a gold (Au) thin film used for the gate lateral wiring GH is preferable. It is also effective to dispose the switch thyristor S and the light emitting thyristor T as far as possible. As shown in the plan view of FIG. 8, the light emitting thyristor T and the other light emitting thyristor T are arranged on one side across the gate horizontal wiring GH. Other thyristors S, U, CL, TR may be arranged on the side.

  Although the above-described current limiting resistor RI may be added as a more preferable configuration, it is not used in the plan view of the light emitting element array chip 1 shown in FIG.

Hereinafter, the configuration of the light emitting element array chip 1 will be described in more detail.
FIG. 9 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as viewed from the section line IX-IX in FIG.

  In the light emitting thyristor T, the first semiconductor layer 22, the second semiconductor layer 23, the third semiconductor layer 24, the fourth semiconductor layer 25, and the ohmic contact layer 27 are stacked in this order on one surface in the thickness direction Z of the substrate 21. Structure to be included. Here, for the first semiconductor layer 22 and the third semiconductor layer 24, either N-type or P-type conductivity type is used, and for the second semiconductor layer 23 and the fourth semiconductor layer 25, the other conductivity type is used. By using the mold, an NPNP or PNPN thyristor structure is formed. For the ohmic contact layer 27, a semiconductor having the same conductivity type as that of the fourth semiconductor layer 25 is used.

  Since the switch thyristor S is formed simultaneously with the light emitting thyristor T in this embodiment, the configuration of each layer is the same. Specifically, the switch thyristor S has the first semiconductor layer 32, the second semiconductor layer 33, and the third semiconductor layer 34 on the same surface of the surface of the substrate 21 as the surface on which the light emitting thyristor T is formed. The fourth semiconductor layer 35 and the ohmic contact layer 37 are stacked in this order. In the following description, the description of the light emitting thyristor T is the same for the switch thyristor S.

  In the present embodiment, a semiconductor substrate having the same conductivity type as that of the first semiconductor layer 22 is used for the substrate 21. In the thickness direction Z of the substrate 21, a back electrode 26 is formed over the entire surface on the surface opposite to the surface on which the semiconductor layers 22 to 25 are stacked. The back electrode 26 is formed of a conductive material such as a metal material and an alloy material. Specifically, the back electrode 26 is formed of gold (Au), an alloy of gold and germanium (AuGe), an alloy of gold and zinc (AuZn), or the like. The back electrode 26 is used as a common electrode for each light emitting thyristor T.

  In the present embodiment, the conductivity type of the first semiconductor layer 22 and the third semiconductor layer 24 is N-type, and the conductivity type of the second semiconductor layer 23 and the fourth semiconductor layer 25 is P-type. Therefore, the cathodes of the light emitting thyristor T and the switch thyristor S are connected to the back electrode 26 as a common electrode, and an N gate electrode is used as the gate electrode. If the back electrode 26 is grounded and the cathode potential is zero (0) volts (V), it is preferable because a positive power source can be used as a power source for applying a voltage or current to the anode a of each light emitting thyristor T.

  The insulating layer 28 is formed along the surfaces of the light-emitting thyristor T and the switch thyristor S, and is also formed between the light-emitting thyristor T and the switch thyristor S. The thyristors S are electrically insulated from each other by the insulating layer 28. The insulating layer 28 is formed of a resin material having electrical insulation, translucency, and flatness. For example, a resin material that transmits 95% or more of light having a wavelength emitted by the light emitting thyristor T, such as polyimide and benzocyclobutene (BCB), is used.

  A through hole 29 is formed in a part of the insulating layer 28 that covers the surface of the ohmic contact layer 27 (side away from the substrate). A part of the anode a is formed in the through hole 29 and is in contact with the ohmic contact layer 27. The through hole 29 is formed so that the center of the light emitting thyristor T in the arrangement direction X and the center of the light emitting thyristor T in the width direction Y are exposed from the insulating layer 28, and the current from the anode a is The light emitting thyristor T can emit light by being efficiently supplied to the central portion of the light emitting thyristor T. In the light emitting thyristor T, light is generated mainly in the vicinity of the interface between the third semiconductor layer 24 and the fourth semiconductor layer 25 and in the region near the third semiconductor layer 24.

  The length W3 in the arrangement direction X of the anodes a of the light emitting thyristors T is formed to be 1/3 or less of the length W2 in the arrangement direction X of the light emitting thyristors T. The anode a covers a part of the light emitting thyristor T in the light emission direction, but the light emitted from the light emitting thyristor T is prevented from being blocked as much as possible by selecting the length W3 as described above.

  The materials of the substrate 21, the semiconductor layers 22 to 25, and the ohmic contact layer 27 will be described more specifically.

  The substrate 21 is a semiconductor substrate capable of crystal growth such as III-V group compound semiconductor and II-VI group compound semiconductor. For example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), silicon It is formed of a semiconductor material such as (Si) and germanium (Ge).

The first semiconductor layer 22 is formed of a semiconductor material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and indium gallium phosphide (InGaP). The carrier density of the first semiconductor layer 22 is desirably about 1 × 10 ¹⁸ cm ⁻³ .

The second semiconductor layer 23 is formed of a semiconductor material such as aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs). The semiconductor material that forms the second semiconductor layer 23 is the same as the energy gap of the semiconductor material that forms the first semiconductor layer 22 or has an energy gap that is smaller than the energy gap of the semiconductor material that forms the first semiconductor layer 22. Is selected. The carrier density of the second semiconductor layer 23 is desirably about 1 × 10 ¹⁷ cm ⁻³ .

The third semiconductor layer 24 is formed of a semiconductor material such as aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs). The semiconductor material forming the third semiconductor layer 24 is the same as the energy gap of the semiconductor material forming the second semiconductor layer 23, or has an energy gap smaller than the energy gap of the semiconductor material forming the second semiconductor layer 23. Is selected. The carrier density of the third semiconductor layer 24 is desirably about 1 × 10 ¹⁸ cm ⁻³ . By forming the third semiconductor layer 24 from a semiconductor material such as aluminum gallium arsenide (AlGaAs) or gallium arsenide (GaAs), a high internal quantum efficiency can be obtained as a light emitting element.

The fourth semiconductor layer 25 is formed of a semiconductor material such as aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs). The semiconductor material forming the fourth semiconductor layer 25 is the same as the energy gap of the semiconductor material forming the second semiconductor layer 23 and the third semiconductor layer 24, or the second semiconductor layer 23 and the third semiconductor layer 24 are formed. A material having an energy gap larger than that of the semiconductor material is selected. The carrier density of the fourth semiconductor layer 25 is desirably about 1 × 10 ¹⁸ cm ⁻³ .

The ohmic contact layer 27 is a semiconductor layer having the same conductivity type as the fourth semiconductor layer 25 formed of a semiconductor material such as gallium arsenide (GaAs) and indium gallium phosphide (InGaP), and performs ohmic contact with the anode e. belongs to. The carrier density of the ohmic contact layer 27 is desirably 1 × 10 ¹⁹ cm ⁻³ or more.

  The first semiconductor layer 22, the second semiconductor layer 23, the third semiconductor layer 24, the fourth semiconductor layer 25, and the ohmic contact layer 27 are formed on one surface of the substrate 21 by molecular beam epitaxy and chemical vapor deposition (CVD). The layers can be sequentially stacked using an epitaxial growth method. Thereafter, the light emitting thyristors T and the switch thyristors S are formed by patterning and etching using photolithography. Therefore, since the light emitting thyristor T and the switch thyristor S are formed simultaneously in a series of manufacturing processes, the semiconductor layers constituting the switch thyristor S and the light emitting thyristor T have the same layer configuration. As a result, both the switch thyristor S and the light emitting thyristor T have both the light emitting function and the switch function, but the switch thyristor S uses only the switch function. In this way, the same structure and stable characteristics can be easily manufactured at a time, and the manufacturing cost can be reduced.

  The insulating layer 28 is formed by forming each semiconductor layer, spin-coating the above-described resin material such as polyimide, and then curing the insulating layer 28. Further, the through holes 29 and 30 necessary for connecting the electrode and the light emitting thyristor T are used. In order to form, patterning and etching by photolithography are performed.

  FIG. 10 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line XX of FIG.

  As shown in FIG. 10, the shape of the light emitting thyristor T in the width direction Y is the gate lateral wiring GH of the first semiconductor layer 22, the second semiconductor layer 23, and the third semiconductor layer 24 of the light emitting thyristor T. The end near the gate protrudes toward the gate horizontal wiring GH from the end near the gate horizontal wiring GH between the fourth semiconductor layer 25 and the ohmic contact layer 27, and the connected portion 101 with the gate horizontal wiring GH is formed. Constitute. The length of the connected portion 101 in the arrangement direction X is equal to the length W2 described above. In addition, the part which comprises the to-be-connected part 101 among the 3rd semiconductor layers 24 is smaller than the part in which the 4th semiconductor layer 25 is laminated | stacked. This is because, when the connected portion 101 is formed by exposing the surface of the third semiconductor layer 24 by the etching process, the fourth semiconductor layer 25 is over-etched so as not to remain.

  Similarly for the shape of the switch thyristor S in the width direction Y, the end portions of the switch thyristor S near the gate lateral wiring GH of the first semiconductor layer 32, the second semiconductor layer 33, and the third semiconductor layer 34 are as follows. The fourth semiconductor layer 35 and the ohmic contact layer 37 protrude toward the gate horizontal wiring GH from the end portion near the gate horizontal wiring GH, and form a connected portion 102 with the gate horizontal wiring GH. Further, in order to perform overetching, the thickness of the portion of the third semiconductor layer 34 that constitutes the connected portion 102 is formed smaller than the thickness of the portion where the fourth semiconductor layer 35 is laminated.

  The insulating layer 28 is formed along the surfaces of the light-emitting thyristor T and the switch thyristor S, and is also formed between the light-emitting thyristor T and the switch thyristor S, and the light-emitting thyristor T and the switch thyristor S. Are electrically insulated by the insulating layer 28. On the surface of the insulating layer 28 formed between the light emitting thyristor T and the switch thyristor S, the gate horizontal wiring GH and the select signal transmission line CSL are formed, and further, the insulating layer 103 is formed along these surfaces. Is done. Further, a set signal transmission path 11 is formed on the surface of the insulating layer 28 on the side away from the gate lateral wiring across the switch thyristor S, and an insulating layer 103 is further formed along the surface.

  In the formed insulating layers 28 and 103, through-holes 104 and 105 are formed in portions of the light emitting thyristor T that are stacked on the connected portion 101 and the surface of the gate horizontal wiring GH (on the side away from the substrate). Is done. A connecting portion GV1 that electrically connects the third semiconductor layer 24 (corresponding to the gate electrode b) of the light emitting thyristor T and the gate lateral wiring GH is formed of the through holes 104 and 105 and the through holes 104 and 105. The insulating layers 28 and 103 sandwiched between the layers are stacked. In addition, through holes 105 and 106 are also formed in portions of the insulating layers 28 and 103 that are stacked on the connected portion 102 of the switch thyristor S and the surface of the gate lateral wiring GH (on the side away from the substrate). The A connection portion 66 that electrically connects the third semiconductor layer 34 (corresponding to the gate electrode d) of the switch thyristor S and the gate lateral wiring GH is connected to the through holes 105 and 106 and the through holes 105 and 106. It is provided by being laminated on the sandwiched insulating layers 28 and 103. As shown in FIG. 10, when the through holes 105 provided in the insulating layer 103 in the portion stacked on the gate horizontal wiring GH are common, the connecting portions GV1 and GV66 are integrally formed.

  Further, as described above, a through hole 29 is formed in a part of the insulating layer 28 laminated on the light emitting thyristor T on the surface of the ohmic contact layer 27 (the side away from the substrate). The A part of the anode a is formed in the through hole 29 and is in contact with the ohmic contact layer 27. The anode a is integrally formed with the connection portion 60 with the light emission signal input terminal A. The connection portion 60 covers part of the end portions of the light emitting thyristor T near the gate lateral wiring GH of the fourth semiconductor layer 25 and the ohmic contact layer 27 and is laminated on the connected portion 101 provided in the third semiconductor layer 24. A part of the surface of the insulating layer 28 (side away from the substrate) is also laminated. Similarly, a through-hole 107 is formed in a part of the insulating layer 28 stacked on the switch thyristor S, which is stacked on the surface of the ohmic contact layer 37 (on the side away from the substrate). A part of the anode c is formed in the through hole 107 and is in contact with the ohmic contact layer 37.

  The switch thyristor S is covered with a light shielding film 12. One end of the light shielding film 12 in the width direction Y covers the ends of the fourth semiconductor layer 35 and the ohmic contact layer 37 of the switching thyristor S opposite to the light emitting thyristor T, and the width direction Y of the light shielding film 12 The other end of the switch covers the connected portion 102 of the third semiconductor layer 34 of the switch thyristor S and extends to the vicinity of the center between the select signal transmission line CSL and the switch thyristor S.

  FIG. 11 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line XI-XI in FIG.

  In this embodiment, the selection thyristor U and the second pull-up resistor RP form the semiconductor layers 22 to 25 and 32 to 35 and the ohmic contact layers 27 and 37 constituting the light emitting thyristor T and the switch thyristor S. Since it is formed at the same time, a new manufacturing process is not required. In the present embodiment, the second pull-up resistor RP uses the third semiconductor layer 54 among the semiconductor thin films constituted by the first semiconductor layer 52, the second semiconductor layer 53, and the third semiconductor layer 54. Yes.

  When the cathodes of the light emitting thyristors used in the light emitting element array are commonly grounded as in the present embodiment, it is preferable to use the third semiconductor layer 54 that is an N-type semiconductor as a thin film resistor. This is because when a positive voltage is applied to one end of the pull-up resistor RP as a set signal, a PN junction composed of the second semiconductor layer 53 that is a P-type semiconductor and the third semiconductor layer 54 that is an N-type semiconductor is formed. This is because a reverse bias voltage is applied and the depletion layer expands, so that insulation between the second semiconductor layer 53 and the third semiconductor layer 54 is ensured.

  Here, as the thin film resistor, it is also possible to use a fourth semiconductor layer that is laminated in order from the first semiconductor layer 52 to the fourth semiconductor layer. When the cathodes of the light emitting thyristors are grounded in common, the fourth semiconductor layer is a P-type semiconductor, and therefore has a lower mobility and higher resistance than the third semiconductor layer 54 that is an N-type semiconductor. There is an advantage. However, when a forward bias is applied unintentionally between the fourth semiconductor layer and the third semiconductor layer 54, the first semiconductor layer 52, the second semiconductor layer 53, the third semiconductor layer 54, and There may be a case where the thyristor constituted by the fourth semiconductor layer transitions to the ON state and a latch-up phenomenon occurs. When the latch-up occurs, the second semiconductor layer 53 and the third semiconductor layer 54 are electrically connected, so that the insulation between the thin film resistor and the back electrode 26 cannot be maintained. When the anodes of the light emitting thyristors are commonly grounded, the third semiconductor layer 54 is a P-type semiconductor, and therefore it is preferable to use the third semiconductor layer 54 for the thin film resistor.

  Further, for the current limiting resistor RI not shown in the plan view of the light emitting element array chip 1 of FIG. 8, it is preferable to use the third semiconductor layer as in the pull-up resistor RQ.

  The ends of the first semiconductor layer 42, the second semiconductor layer 43, and the third semiconductor layer 44 of the selection thyristor U near the gate lateral wiring GH are gates of the fourth semiconductor layer 45 and the ohmic contact layer 47. It protrudes toward the gate horizontal wiring GH from the end near the horizontal wiring GH, and constitutes a connected portion 108 with the gate horizontal wiring GH. In the present embodiment, the connected portion 108 corresponds to the N gate electrode f of the selection thyristor U. Further, a part of the connection portion 65 provided on the surface of the ohmic contact layer 47 (on the side away from the substrate) with the gate electrode d of the switch thyristor S corresponds to the anode of the selection thyristor U. Note that, in the third semiconductor layer 44, the portion constituting the connected portion 108 is thinner than the portion where the fourth semiconductor layer 45 is laminated. This is because, when the connected portion 108 is formed by exposing the surface of the third semiconductor layer 44 by an etching process, the fourth semiconductor layer 45 is over-etched so as not to remain. Note that the formation of the connected portion 108 of the selection thyristor U is performed simultaneously with the formation of the connected portions 101 and 102 of the light emitting thyristor T and the switch thyristor S, so that a new manufacturing process is not required.

  An etching process for determining the total thickness of the first semiconductor layer 52, the second semiconductor layer 53, and the third semiconductor layer 54 constituting the second pull-up resistor RP is also performed by the connected portions 101, 102, 108. Performed simultaneously with formation. Therefore, the thickness of the second pull-up resistor RP is equal to the thickness of the connected parts 101, 102, 108.

  In FIG. 11, the insulating layer 28 is formed along the surfaces of the selection thyristor U and the second pull-up resistor RP, and is also formed between the selection thyristor U and the second pull-up resistor RP. The thyristor U for use and the second pull-up resistor RP are electrically insulated by the insulating layer 28. As described above, the gate horizontal wiring GH, the select signal transmission line CSL, and the set signal transmission line 11 are formed on the surface of the insulating layer 28, and the insulating layer 103 is further formed along these surfaces.

  In the formed insulating layers 28 and 103, through holes 109 and 110 are formed in portions of the select signal transmission line CSL and the selection thyristor U that are stacked on the surface of the connected portion 108 (on the side away from the substrate). A connecting portion 67 is provided to electrically connect them. A through hole 111 is also formed in a portion of the insulating layer 28 that is stacked on the surface of the ohmic contact layer 47 of the selection thyristor U (on the side away from the substrate), and is connected to the gate electrode d of the switch thyristor S. A connecting portion 65 is provided. Further, in the formed insulating layers 28 and 103, through-holes 112 and 113 are also formed in a portion laminated on the second pull-up resistor RP and the set signal transmission path 11, and a connection portion for electrically connecting them. 68 is formed.

  In the present embodiment, the third semiconductor layer 44 and the fourth semiconductor layer 45 constituting the selection thyristor U are formed at the same time as the light emitting thyristor T, so that the selection thyristor U emits light in the ON state. Therefore, in order to block or reduce the light emitted from the selection thyristor U, the light shielding film 12 covering the selection thyristor U is formed.

  Further, a light shielding film 12 that covers the second pull-up resistor RP is also formed. When light enters the interface of the second pull-up resistor RP from the outside, electrons / electrons are incident on the interfaces of the first semiconductor layer 52, the second semiconductor layer 53, and the third semiconductor layer 54 where the pull-up resistor RP is provided. Hole pairs are generated. Then, like the phototransistor, carriers are accumulated in the second semiconductor layer 53, resulting in poor insulation between the second semiconductor layer 53 and the third semiconductor layer 54. Originally, the third semiconductor layer 54 The carrier to be conducted inside flows to the substrate 21 side, and the operation as a resistor becomes unstable. Therefore, the second pull-up resistor RP is also covered with the light shielding film 12 in order to stabilize the operation of the second pull-up resistor RP. Even when the current limiting resistor RI is formed on the substrate 21, it is preferable to cover it with the light shielding film 12.

  As shown in FIG. 11, one side in the width direction Y of the light shielding film 12 covers the surface of the insulating layer 28 laminated on the surface of the second pull-up resistor RP, extends to the vicinity of the set signal transmission path 11, and 12 in the width direction Y covers the insulating layer 28 laminated on the surface of the connected portion 108 of the selection thyristor U, and a part of the connection portion 67 between the selection thyristor U and the select signal transmission line CSL. Cover to the surface.

  FIG. 12 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line XII-XII in FIG.

  In the present embodiment, the trigger thyristor TR is formed simultaneously with the formation of the semiconductor layers 22 to 25 and 32 to 35 and the ohmic contact layers 27 and 37 constituting the light emitting thyristor T and the switch thyristor S. Therefore, no new manufacturing process is required. The end of the trigger thyristor TR near the gate lateral wiring GH of the first semiconductor layer 152, the second semiconductor layer 153, and the third semiconductor layer 154 is the gate of the fourth semiconductor layer 155 and the ohmic contact layer 157. From the end near the horizontal wiring GH, it protrudes toward the gate horizontal wiring GH, and a connected portion 158 with the gate horizontal wiring GH is formed. In the present embodiment, the connected portion 158 corresponds to the gate electrode w of the trigger thyristor TR. Since the connected portion 158 of the trigger thyristor TR is formed simultaneously with the formation of the connected portions 101 and 102 of the light emitting thyristor T and the switch thyristor S, no new manufacturing process is required.

  In FIG. 12, the insulating layer 28 is formed so as to cover the surface of the substrate 21 and the trigger thyristor TR. As described above, the gate horizontal wiring GH, the select signal transmission line CSL, and the set signal transmission line 11 are formed on the surface of the insulating layer 28, and the insulating layer 103 is further formed along these surfaces. In the formed insulating layers 28 and 103, through holes 161 and 162 are formed in portions of the select signal transmission line CSL and the trigger thyristor TR that are stacked on the surface of the connected portion 158 (on the side away from the substrate). A connecting portion 144 is provided to electrically connect them. A through-hole 160 is also formed in a portion of the insulating layer 28 that is stacked on the surface of the ohmic contact layer 47 of the trigger thyristor TR (on the side away from the substrate), and an anode q is provided. Further, a light shielding film 12 that covers the trigger thyristor TR is formed in order to shield or reduce light emitted when the trigger thyristor TR is in the ON state. One of the light shielding films 12 in the width direction Y covers the end portion of the trigger thyristor TR near the set signal transmission path 11, and the other of the light shielding films 12 in the width direction Y is the surface of the connected portion 108 of the selection thyristor U. The insulating layer 28 stacked on the first and second thyristors U and the select signal transmission line CSL is covered up to a part of the surface.

  The configuration of the clock thyristor CL is the same as that of the trigger thyristor TR shown in FIG.

  FIG. 13 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line XIII-XIII in FIG.

  In the present embodiment, the first pull-up resistor RQ is a semiconductor thin film composed of the first semiconductor layer 172, the second semiconductor layer 173, and the third semiconductor layer 174, similarly to the second pull-up resistor RP described above. Of these, the third semiconductor layer 174 is used. An etching process for determining the total thickness of the first semiconductor layer 172, the second semiconductor layer 173, and the third semiconductor layer 174 constituting the first pull-up resistor RQ is also performed by the connected portions 101, 102, 108, At the same time as the formation of 158. Therefore, the thickness of the first pull-up resistor RQ is equal to the thickness of the connected portions 101, 102, 108, 158.

  In FIG. 13, the insulating layer 28 is formed so as to cover the surface of the substrate 21 and the first pull-up resistor RQ. As described above, the gate horizontal wiring GH, the select signal transmission line CSL, and the set signal transmission line 11 are formed on the surface of the insulating layer 28, and the insulating layer 103 is further formed along these surfaces. Of the formed insulating layers 28 and 103, the portion laminated on the surface of the select signal transmission line CSL (the side away from the substrate) and the surface of the end of the first pull-up resistor RQ near the select signal transmission line CSL Through holes 165 and 166 are formed in a portion laminated on the side separated from the substrate, and a connection portion 142 for electrically connecting them is provided. A through hole 164 is also provided on the insulating layer 28 stacked on the first pull-up resistor RQ on the side away from the select signal transmission line CSL, and a part of the power supply bonding pad Vs covers the through hole 164. Formed as follows.

  Further, similarly to the second pull-up resistor RP, a light shielding film 12 that covers the first pull-up resistor RQ is also formed. As shown in FIG. 13, the light shielding film 12 includes the insulating layer 28 laminated on the surface of the first pull-up resistor RQ, a part of the connection part 142 with the select signal transmission line CSL, and a part of the power supply bonding pad. Is further laminated on the surface of the first pull-up resistor RQ to cover from one end side to the other end side in the width direction Y of the first pull-up resistor RQ.

  FIG. 14 is a block circuit diagram schematically showing the light emitting device 10 according to the embodiment of the present invention. The light emitting device 10 emits light as a plurality of light emitting element array chips L1, L2,..., Lp-1, Lp (the symbol p is a positive integer of 2 or more) and a drive circuit for the light emitting element array chips 1 to Lp. A light emission signal driving IC (Integrated Circuit) 130 for supplying a signal, a gate signal driving IC 131 for supplying a gate signal, a clock signal, an input trigger signal, and a set signal are supplied to select each light emitting element array chip L1 to Lp. And a select signal driving IC 132 and a positive voltage source Vcc. Each drive IC outputs image information based on a control means 96 described later. Each of the light emitting element array chips 1 to Lp is simply referred to as a light emitting element array chip L when collectively referring to each of the light emitting element array chips 1 to Lp. Further, the light emitting element array chip L may be simply referred to as an array chip L. In the present embodiment, the light-emitting element array chip 1 according to the first embodiment shown in FIG. The select signal driving IC 132 corresponds to the input trigger signal driving circuit, the clock signal driving circuit, and the set signal driving circuit, and the gate signal driving IC 131 corresponds to the second selection signal driving circuit. The signal drive IC 130 corresponds to the light emission signal drive circuit.

  In each array chip L, the light emitting elements T are arranged in a line along the arrangement direction X, and the light emitting directions from the respective light emitting elements T are aligned and mounted on the circuit board. However, the circuit board is not shown in FIG. The light emission signal driving IC 130, the gate signal driving IC 131, the select signal driving IC, and the positive power source Vcc are mounted on the circuit board. The circuit board is further formed with a pattern wiring for connecting each of the drive ICs 130 to 132 and the output terminal of the positive power supply to the bonding pad of each array chip L, and the pattern wiring and the bonding pad are connected by a bonding wire. The

As described above, the light emitting element array chip 1 according to the first embodiment shown in FIGS. 1 and 8 includes m light emitting signal bonding pads A, one input trigger signal bonding pad CSG, and one. Clock signal bonding pad CLA, one set signal bonding pad CSA, one power supply bonding pad Vs, one output trigger signal bonding pad TRA, and four gate signal bonding pads G. . In FIG. 14, each array chip is numbered from No. 1 to No. p from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L, and the light emitting elements in a specific order When an array is shown, it is distinguished by adding a number to the end of the reference symbol. For example, the input trigger signal bonding pad CSG of the i ₁₀ (1 ≦ i ₁₀ ≦ p) th array chip Li ₁₀ is referred to as the i _10th input trigger signal bonding pad CSGi ₁₀ . When referring to the input trigger signal bonding pads CSG1 to CSGp of the unspecified array chip L, or when collectively referring to the input trigger signal bonding pads CSG1 to CSGp, the input trigger signal bonding pads CSG may be simply described.

The light emission signal drive IC 130 has the same number (m) of light emission signal output terminals λ1 to λm as the light emission signal bonding pads A1 to Am of each array chip L. The light emission signal output terminals λ1 to λm may be simply referred to as the light emission signal output terminal λ when collectively referring to a plurality of light emission signal outputs terminals λ1 to λm. Each light emitting signal bonding pad A and the light emitting signal output terminal λ are connected by sharing wiring between different array chips. In the case of this embodiment in which p array chips are mounted, light emitting signal bonding pads A1 to Am from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L. the first numbered up to the m-th from th and light emission signal output terminal to λ1~λm when numbered from No. 1 to No. m-th, p pieces of the array each of the i ₈ chips (1 ≦ i ₈ ≦ m) The light emitting signal bonding pads Ai ₈ are electrically connected to each other and further electrically connected to the i _8th light emitting signal output terminal λi ₈ .

The gate signal driving IC 131 has the same number (four) of gate signal output terminals μ1 to μ4 as the gate signal bonding pads G1 to G4 of each array chip L. The gate signal output terminals μ1 to μ4 may be simply referred to as the gate signal output terminal μ when collectively referring to a plurality of gate signal output terminals μ1 to μ4 or when referring to an unspecified one. Each gate signal bonding pad G and the gate signal output terminal μ are connected by sharing wiring between different array chips. In the case of the present embodiment in which p array chips are mounted, the gate signal bonding pads G1 to G4 are directed from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L. Are numbered from No. 1 to No. 4 and gate signal output terminals μ1 to μ4 are also numbered from No. 1 to No. 4, respectively, and the i ₉ (1 ≦ 1) of each of the p array chips. i ₉ ≦ 4) The gate signal bonding pads Gi ₉ are electrically connected to each other, and further electrically connected to the i _9th gate signal output terminal μi ₉ .

The select signal driving IC 132 has one set signal output terminal η, one input trigger signal output terminal φS, and two clock signal output terminals φ1 and φ2. The set signal output terminal η is connected in common between the set signal bonding pads CSA1 to CSAp of the light emitting element array chips L1 to Lp. The input trigger signal output terminal φS is connected to the input trigger signal bonding pad CSG1 of the first light emitting element array chip L1. The two clock signal output terminals φ1 and φ2 are individually connected to the two clock signal transmission paths CLL1 and CLL2, respectively. The clock signal bonding pads CLA between the light emitting element array chips L adjacent to each other are connected to different clock signal transmission paths CLL1 and CLL2, respectively. Specifically, in the case of the present embodiment in which p array chips (here, p is an even number of 4 or more) are mounted, in the arrangement direction X of the light emitting elements T constituting each array chip L. When each array chip is numbered from No. 1 to No. p from one side to the other along the line, the odd-numbered 2i ₁₈ −1 (1 ≦ i ₁₈ ≦ p / 2) array chip L a clock signal bonding pads CLA2i ₁₈ -1 and the first clock signal transmission line CLL1 are electrically connected, the 2i ₁₈ th is an even-numbered array chip L of _{(1 ≦ i 18 ≦ p /} 2) The clock signal bonding pad CLA2i ₁₈ and the second clock signal transmission line CLL2 are electrically connected.

Further, as described above, the output trigger signal bonding pad TRAi ₁₉ of the i ₁₉ (1 ≦ i ₁₉ ≦ p−1) th light emitting element array chip Li ₁₉ is adjacent to the light emitting element array chip L in the arrangement direction. It is electrically connected to the i ₁₉ + 1st input trigger signal bonding pad CSGi ₁₉ +1. With such a connection, the output trigger signal can be sequentially transferred as an input trigger signal adjacent in the arrangement direction in synchronization with the clock signal. Accordingly, the first light emitting element array chip L1 to the light emitting element array chip L can be sequentially selected in synchronization with the clock signal in the order of arrangement.

  As described above, by switching the array chips L in the selected state in order, it is possible to stably operate time-division driving in which the gate signal driving IC 131 and the light emitting signal driving IC 130 are shared among the plurality of light emitting element arrays. Accordingly, the number of driving ICs and the number of layers of the substrate on which the driving ICs are mounted can be reduced, and the area of the light emitting element array and the driving IC mounting substrate can be reduced. As a result, it is small and stable. A light emitting device that operates in a short time can be realized.

  FIG. 15 is a timing chart showing the operation of the light emitting device 10, where the horizontal axis represents the elapsed time from the reference time, and the vertical axis represents the magnitude of the voltage or current at the output terminals of the driving ICs 130 to 132. In FIG. 15, the signal output terminals (light emission signal output terminal λ, gate signal output terminal μ, input trigger signal output terminal φS, clock signal output terminal φ1) of the light emission signal drive IC 130, the gate signal drive IC 131, and the select signal drive IC 132, respectively. , Φ2 and the set signal output terminal η) are shown as voltage or current waveforms. In addition, in FIG. 15, the reference symbol of the bonding pad (signal input terminal) connected to each signal output terminal may be used as the reference symbol of the output waveform.

  In the present embodiment, the light emission signal driving IC 130 outputs a constant current of 5 mA when the level is high (H) and 0 mA when the level is low (L). The gate signal driving IC 131 outputs a constant voltage of 5V when the level is high (H) and 0V when the level is low (L). The select signal driving IC 132 outputs a constant voltage of 5V when the level is high (H) and 0V when the level is low (L).

  The operation of the light emitting device 10 will be described in the order of time passage with reference to FIG. At time t0, the voltage of the input trigger signal output terminal φS is high (H) level, and the voltage of the first clock signal output terminal φ1 is low (L) level. Not selected. At time t1, the voltage of the input trigger signal output terminal φS input to the first array chip L1 is set to low (L) level, and the voltage of the first clock signal output terminal φ1 is set to high (H) level. As a result, the first array chip L1 is in the selected state, and the output trigger signal output from the first array chip L1 is input as the input trigger signal of the second array chip L2. At time t2, a high (H) level voltage is applied to the first gate signal input terminal G1 of each array chip L. Then, only in the selected first array chip L1, the first switch thyristor S1 switches to the ON state, and the gate horizontal wiring GH1 connected to the gate electrode d1 of the switch thyristor S1 is switched. The potential is almost low (0 V). Next, at time t3, light emission signals are input to the light emission signal input terminals A1 to Am of each array chip. Then, the light emitting thyristor T connected to the first gate horizontal wiring GH1 in the first array chip L1 in the selected state emits light. Since the light emission signal returns to the low (L) level at time t4, it is turned off. Next, at time t5, the voltage of the gate signal output terminal μ1 connected to the first gate signal input terminal G1 returns to the low (L) level, and the gate connected to the second gate signal input terminal G2 The voltage of the signal output terminal μ2 becomes high (H) level. Then, only in the selected first array chip L1, the second switch thyristor S2 is switched to be turned on. From time t6 to t7, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Then, the light emitting thyristor T connected to the second gate horizontal wiring GH2 in the first array chip L1 in the selected state emits light. Similarly, from time t8 to t11, since the voltage of the gate signal output terminal μ3 connected to the third gate signal input terminal G3 becomes high (H) level, the first array chip in the selected state is used. In L1, the third switch thyristor S3 switches to be turned on. In this state, at time t9 to t10, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Therefore, among the first array chips L1 in the selected state, the third one is selected. The light emitting thyristor T connected to the gate lateral wiring GH3 emits light. At time t11 to t14, the voltage of the gate signal output terminal μ4 connected to the fourth gate signal input terminal G4 becomes high (H) level, so that the first array chip L1 in the selected state is in the selected state. Among them, the fourth switch thyristor S4 is switched to be turned on. In this state, at time t12 to t13, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Therefore, among the first array chips L1 in the selected state, the fourth one. The light emitting thyristor T connected to the gate lateral wiring GH4 emits light. At time t15, the voltage of the set signal output terminal η connected to the set signal input terminal CSA of each array chip L returns from the high (H) level to the low (L) level, so that the first array chip L1 The selection thyristor U transitions to the off state. At time t16, the voltage of the input trigger signal output terminal φS connected to the trigger signal input terminal CSG1 of the first array chip L1 returns to the high (H) level, and the clock signal input terminal of the first array chip L1 The voltage of the first clock signal output terminal φ1 connected to CLA1 becomes low (L) level, and the second clock signal output terminal connected to the clock signal input terminal CLA2 of the second array chip L2 The voltage of φ2 becomes high (H) level. Then, the first array chip L1 is not in the selected state, and the second array chip L2 to which the input trigger signal is input from time t1 is in the selected state. Note that, as described above with reference to FIG. 7, in order to surely switch the selection state from the first array chip L1 to the second array chip L2, the second of the next selection state is selected. The rise of the voltage of the second clock signal output terminal φ2 connected to the array chip L2 may be preceded by the fall of the voltage of the first clock signal output terminal φ2.

  With respect to the second array chip L2, the light emitting thyristor T can be made to emit light sequentially in the same procedure. That is, at time t18 after the voltage of the set signal output terminal η connected to the set signal input terminal CSA returns from the high (H) level to the low (L) level, the first of each array chip L The voltage of the gate signal output terminal μ1 connected to the gate signal input terminal G1 becomes high (H) level. At subsequent time t19, light emission signals are input to all the light emission signal input terminals A1 to Am of each array chip L, whereby the first gate horizontal wiring GH1 of the second array chip L2 in the selected state is input. The connected light emitting thyristor T emits light. Note that the gate signal and the light emission signal need not be input while the voltage of the set signal output terminal η connected to the set signal input terminal CSA remains at the low (L) level. When the voltage of the set signal output terminal η is low (L) level, the voltage of the gate horizontal wiring GH of each light emitting element array chip L is low (L) level. This is because light is emitted.

  As described above, by selecting the array chips in the order in which the array chips L are arranged, time-division driving for each array chip L is possible. Further, the gate signal is sequentially applied from the first switch thyristor, so that time-division driving in the array chip L is possible.

  FIG. 16 is a side view showing a basic configuration of an image forming apparatus using the light emitting device 10 including the light emitting element array chip 1 of the present embodiment.

  The image forming apparatus 87 is an electrophotographic image forming apparatus, and the light emitting devices 10Y, 10M, 10C, and 10K are used as an exposure device for the photosensitive drum 90. The light emitting devices 10Y, 10M, 10C, and 10K are mounted on a circuit board on which each driving IC (light emitting signal driving IC 130, gate signal driving IC 131, and select signal driving IC 132) is provided.

  The image forming apparatus 87 is an apparatus that employs a tandem system that forms four color images of Y (yellow), M (magenta), C (cyan), and K (black), and is roughly divided into four light emitting elements. Circuit boards and lens arrays on which the devices 10Y, 10M, 10C, and 10K, the lens arrays 88C, 88M, 88Y, and 88K as the light condensing means, the light emitting devices 10Y, 10M, 10C, and 10K, and the driving ICs 130, 131, and 132 are mounted First holders 89C, 89M, 89Y, 89K for holding 88, four photosensitive drums 90C, 90M, 90Y, 90K, four developer supply means 91C, 91M, 91Y, 91K, a transfer belt 92 as transfer means, Four cleaners 93C, 93M, 93Y, 93K, four chargers 94C, 94M, 94Y, 94K, fixing means 95 and control Configured to include a means 96.

  Each light emitting device 10Y, 10M, 10C, 10K is driven by each driving IC based on the color image information of each color. For example, the length of the four light emitting devices 10Y, 10M, 10C, and 10K in the arrangement direction X is selected from 200 mm to 400 mm, for example.

  Light from the light emitting thyristors T of the light emitting devices 10Y, 10M, 10C, and 10K is condensed and irradiated on the photosensitive drums 90C, 90M, 90Y, and 90K via the lens array 88. The lens array 88 includes, for example, a plurality of lenses disposed on the optical axis of the light emitting element, and is configured by integrally forming these lenses.

  The circuit board on which the light emitting devices 10Y, 10M, 10C, and 10K are mounted and the lens array 88 are held by the first holder 89. By the first holder 89, the light irradiation direction of the light emitting thyristor T and the optical axis direction of the lens of the lens array 88 are aligned so as to be aligned.

  Each of the photoconductor drums 90C, 90M, 90Y, and 90K is formed by, for example, attaching a photoconductor layer to the surface of a cylindrical substrate, and the outer peripheral surface thereof receives light from the light emitting devices 10Y, 10M, 10C, and 10K. Then, an electrostatic latent image forming position where the electrostatic latent image is formed is set.

  In the peripheral portions of the photosensitive drums 90C, 90M, 90Y, and 90K, the exposed photosensitive drums 90C, 90M, 90Y, and 90K are sequentially exposed toward the downstream side in the rotation direction with reference to the electrostatic latent image forming positions. Developer supply means 91C, 91M, 91Y, 91K for supplying developer to the transfer belt 92, cleaners 93C, 93M, 93Y, 93K, and chargers 94C, 94M, 94Y, 94K are arranged, respectively. A transfer belt 92 that transfers an image formed on the photosensitive drum 90 with a developer onto a recording sheet is provided in common to the four photosensitive drums 90C, 90M, 90Y, and 90K.

  The photosensitive drums 90C, 90M, 90Y, and 90K are held by a second holder (not shown), and the second holder and the first holder 89 are relatively fixed. The alignment is performed such that the rotation axis direction of each of the photoconductive drums 90C, 90M, 90Y, and 90K and the arrangement direction X of each of the light emitting devices 10Y, 10M, 10C, and 10K substantially coincide with each other.

  The recording sheet is conveyed by the transfer belt 92, and the recording sheet on which an image is formed by the developer is conveyed to the fixing unit 95. The fixing unit 95 fixes the developer transferred to the recording sheet. The photosensitive drums 90C, 90M, 90Y, and 90K are rotated by a rotation driving unit.

  The control means 96 gives a clock signal and image information to each of the drive ICs 130, 131, 132 described above, and also rotational drive means for rotating the photosensitive drums 90C, 90M, 90Y, 90K, developer supply means 91C, 91M, 91Y, 91K, transfer means 92, charging means 94C, 94M, 94Y, 94K, and fixing means 95 are controlled.

  In the image forming apparatus 87 having such a configuration, whether each light emitting element is in a light emitting state or a non-light emitting state is transmitted through the gate horizontal wiring GH connected to the gate electrode b through which no main current flows. Since switching is performed according to the gate signal, the transmission path of the gate signal formed on the circuit board side for mounting the light emitting devices 10Y, 10M, 10C, and 10K can be narrowed, and the circuit board can be downsized. Further, since the main current is not switched in the gate signal driving IC (Integrated Circuit), the capacity of the IC can be reduced, so that downsizing and cost reduction can be realized.

  As described above, according to the light emitting element array chip 1 of the present embodiment, only the light emitting element array chip 1 in the selected state by receiving the clock signal and the input trigger signal passes the gate signal to the light emitting thyristor T side. Therefore, in the case where a plurality of such light emitting element array chips 1 are arranged and driven, the driving that gives a light emission signal and a gate signal without connecting a driving IC to each of the plurality of light emitting element array chips 1 is performed. Therefore, it is possible to perform time-division driving by using the common IC and wiring, so that there is a basic effect that time-division driving can be performed with a small number of driving ICs and wires. Further, when driving a plurality of light emitting element array chips 1, if an input trigger signal is input from an adjacent light emitting element array chip 1 in a selected state, at least two clock signals and one input trigger signal are provided. By simply adding a driving IC and wiring for supplying the light emitting element array chip 1, the light emitting element array chip 1 can be brought into a selected state sequentially in synchronization with the clock signal in the arrangement order.

  When a plurality of light emitting element blocks B in which the anode a is shared by a plurality of light emitting thyristors T are provided and the gate horizontal wiring GH is shared by the plurality of light emitting element blocks B, one light emitting element array chip 1 is provided. In FIG. 5, time-division driving can be performed among the plurality of light emitting element blocks B. As a result, the number of gate horizontal wirings GH to be connected to the driving IC can be reduced, and thus light emission that can be time-division driven with a small number of driving ICs using a driving IC with a small number of gate signal output ports. Equipment can be provided.

  Further, bonding pads A, G, CSG, CLA, Vs for supplying a light emission signal, a gate signal, an input trigger signal, a clock signal and a positive voltage, and a bonding pad TRA for outputting an output trigger signal are provided for the light emitting element. When arranged in the arrangement direction X, one light emitting signal bonding pad A is provided for one light emitting element block B, and one light emitting signal block is arranged for each adjacent light emitting element block B. A space is generated between the bonding pads A. Therefore, the switch thyristor S and the like can be arranged by effectively utilizing the space, and therefore the increase in the size of the light emitting element array chip can be avoided even if the switch thyristor S or the like is provided. This is advantageous in that it is possible to provide a small light-emitting element array chip that can be easily densified.

  Further, since the first switch unit, the second switch unit, and the light emitting element are configured to include a light emitting thyristor, a gate signal can be input with a simple configuration without using a complicated semiconductor device such as a NAND gate or an inverter. Since a logic circuit for selecting the light emitting element array chip 1 to be formed can be configured, it is advantageous in that the design is facilitated and the manufacturing process can be simplified.

  Further, since the current flowing into the N gate electrode f of the selection thyristor U is small, the line width of the select signal transmission line CSL can be reduced. As a result, the light emitting element array chip 1 can be miniaturized.

  When the second pull-up resistor RP, the selection thyristor U, or the like is used, the voltage of the gate electrode to which the selection thyristor U is connected is stabilized at a predetermined value by the second pull-up resistor RP. Therefore, it is advantageous in that the switching operation of the switch thyristor S can be stabilized and the operation as the AND circuit can be ensured.

  Further, when the current limiting resistor RI is connected between the gate signal bonding pad G and the anode c of the switch thyristor S, when the plurality of switch thyristors S are simultaneously turned on for the purpose of speeding up, Even if the switching timing is slightly different between the plurality, the signal voltage of the gate signal is not lowered by the first switching, and the potentials of the anodes c of the plurality of switching thyristors S are stably secured. Therefore, since the plurality of switch thyristors can be switched reliably, the plurality of light emitting element array chips 1 can have the same time division timing, which is advantageous for speeding up.

  When the semiconductor layer constituting the switch thyristor S and the semiconductor layer constituting the light emitting thyristor T are formed to have the same layer structure, the light emitting thyristor T and the switch thyristor S are simultaneously manufactured in the same process. can do. Therefore, even in the configuration of the present invention in which the switch thyristor S is provided in addition to the light emitting thyristor T as a light emitting element, a manufacturing process is not complicated and a light emitting element array advantageous in manufacturing is provided. Can do.

  Further, when a metal thin film or the like is provided on the surface of the switch thyristor S as a light shielding means, the light emitted from the switch thyristor S is incident on the light emitting thyristor T to change the threshold value of the light emitting thyristor T. This is advantageous in that it can be avoided.

  Further, the third semiconductor layer 174 is used as the first pull-up resistor RQ, and the third semiconductor layer 54 is used as the second pull-up resistor RP so as to cover the first pull-up resistor RQ and the second pull-up resistor RP. By providing the light shielding film 12 on the surface, the insulation of the pull-up resistor RP with respect to the back electrode 26 can be improved, and the operation can be stabilized.

  Further, by using the light-emitting element array chip 1 having the above-described configuration, the light-emitting device is small in size and has high reliability that operates stably. Therefore, an image forming apparatus that can stably form a good image. Can provide.

  Thus, according to the present invention, a light-emitting element array that can be time-divisionally driven with a small number of driving ICs and can increase the density of light-emitting elements by reducing the number of bonding pads, and a small light-emitting device using the same In addition, an image forming apparatus including the light emitting device can be provided.

  FIG. 17 is a schematic equivalent circuit diagram showing a light emitting element array chip 2 as a second embodiment of the light emitting element array of the present invention. The difference in configuration from the light emitting element array chip 1 as the first embodiment shown in FIG. 1 is that the light emitting element block B is not provided, and the other configurations are common. Accordingly, common parts are denoted by the same reference numerals and description thereof is omitted.

  As in the first embodiment, the light emitting element array chip 2 as the second embodiment includes light emitting thyristors T1 to Tk as k light emitting elements and a clock as one first switch unit. Thyristor CL for trigger, thyristor TR for trigger, switch thyristors S1 to Sn and selection thyristors U1 to Un as n second switch sections, n gate lateral wires GH1 to GHn, and one select signal A transmission line CSL. In addition, the first switch unit includes one first pull-up resistor RQ, and the second switch unit includes n second pull-up resistors RP1 to RPn. Also in this embodiment, the cathodes of the thyristors CL, TR, S, U, and T are installed as a common electrode. As in the first embodiment, the first selection signal corresponds to the select signal, the second selection signal corresponds to the gate signal, the first selection signal transmission path corresponds to the select signal transmission path CSL, The control signal transmission line corresponds to the gate horizontal wiring GH. The current limiting resistor RI as the resistor may be added as a more preferable configuration, but is not used in the present embodiment.

As described above, since the light emitting thyristors T of the light emitting element array chip 2 are not divided for each light emitting element block B, the anodes a of the light emitting thyristors T are connected to the light emission signal input terminal A one by one. For example, in FIG. 17, the _{i 15 (1 ≦ i 15 ≦} k) th anode ai ₁₅ is the i ₁₅ th light emitting signal input terminal of the light emitting thyristor Ti ₁₅ from one arrangement direction of the light emitting thyristor T to the other Connected to Ai ₁₅ . The gate electrode b of the light emitting thyristor T is connected to any one of the gate lateral wirings GH. Since the number n of the gate lateral wirings GH and the number k of the light emitting thyristors T are not necessarily equal, the gate electrodes b of the plurality of light emitting thyristors T may be connected to the same gate lateral wiring GH. In this case, in order to selectively emit light from the light emitting thyristor T connected to the same gate horizontal wiring GH, it is necessary to give different light emission signals.

  The operational effects of the light emitting element array chip 2 of the second embodiment are basically the same as those of the light emitting element array chip 1 of the first embodiment. In the light emitting element array chip 2, the switch thyristor S provided as a switch element operates so as to deliver the gate signal to the light emitting thyristor T side only at a time selected by the clock signal and the input trigger signal. Therefore, in the case where a plurality of such light emitting element array chips 1 are arranged and driven, a driving IC and a wiring for providing a light emission signal and a gate signal without connecting a driving IC to each of the plurality of light emitting element array chips 1. Therefore, the time division drive can be performed with a small number of driving ICs and the number of wires. In addition, when driving a plurality of light emitting element array chips 2, if the input trigger signal is input from the adjacent light emitting element array chip 2 in the selected state, at least two clock signals and one input trigger are provided. The time-division driving between the array chips as described above can be performed only by adding a driving IC for supplying a signal and wiring. Other functions and effects are the same, but the light emitting element block B is not provided unlike the light emitting element array chip 1 of the first embodiment, so that time-division driving in one light emitting element array chip 1 is not possible. Can not. Instead, all the light emitting thyristors in the light emitting element array chip 2 selected by the select signal can selectively emit light.

  FIG. 18 is a schematic equivalent circuit diagram showing a light emitting element array chip 3 as a third embodiment of the light emitting element array of the present invention.

  The light emitting element array chip 3 according to the third embodiment shown in FIG. 18 has the light emitting element array chip 1 according to the first embodiment shown in FIG. 1 and the light emission according to the second embodiment shown in FIG. Unlike the element array chip 2, a switch element and a light emitting element are configured without using a light emitting thyristor. Since parts other than the configuration of the switch element and the light emitting element are the same as those in FIG. 17, the same reference numerals are given and description thereof is omitted.

  The light emitting element array chip of the third embodiment shown in FIG. 18 includes n switch elements and k light emitting elements. FIG. 17 illustrates a case where n = k = 4. Hereinafter, the case of n = k = 4 shown in FIG. 17 will be described, but the circuit operation is the same as the general case.

  The light emitting element includes field effect transistors FET1 to FET4 and light emitting diodes LED1 to LED4. The field effect transistor has a source electrode, a drain electrode, and a gate electrode, and the anode of the diode and the source electrode of the field effect transistor are connected. The cathode of the diode is grounded as a common electrode. The drain electrodes α1 to α4 of the field effect transistor are individually connected to the light emission signal input terminals A1 to A4. The gate electrodes β1 to β4 of the field effect transistor are connected to any one of the gate horizontal wirings GH1 to GH4. The drain electrode of the field effect transistor and the cathode of the diode may be connected. In this case, the anode of the diode is grounded as a common electrode, and each source electrode of the field effect transistor is individually connected to each light emission signal input terminal A1 to A4.

  The first switch unit is an AND circuit element AND0 that outputs a logical product of two inputs, and can be configured, for example, by a circuit combining a NAND circuit element and a NOT circuit element. One input terminal γ0 of the AND circuit element AND0 is connected to the clock signal input terminal CLA, and the other input terminal δ0 is connected to the trigger signal input terminal CSG. The output terminal ε0 of the AND circuit element AND0 is connected to the select signal transmission line CSL. Further, a trigger signal output terminal TRA is connected to the select signal transmission line CSL.

  The second switch unit includes n AND circuit elements AND1 to AND4 that output a logical product of two inputs. In this embodiment, n = 4. One input terminals γ1 to γ4 of the AND circuit elements AND1 to AND4 are individually connected to the gate signal input terminals G1 to G4, and the other input terminals δ1 to δ4 are connected to the common select signal transmission line CSL. The output terminals ε1 to ε4 of the AND circuit elements are individually connected to the gate horizontal wirings GH1 to GH4.

  The AND circuit elements AND1 to AND4 can be constituted by generally well-known logic circuits (logic) such as a gallium arsenide (GaAs) MES-FET integrated circuit, a silicon (Si) TTL, and a CMOS. The light emitting element array chip 3 can be manufactured by forming such a logic circuit, LED and field effect transistor on a GaAs or Si substrate.

Next, the operation of the light emitting element array chip 3 shown in FIG. 18 will be described.
In the light emitting element array chip 3 shown in FIG. 18, when a true value (high level voltage) is input from the trigger signal input terminal CSG and a true value (high level voltage) is input from the clock signal input terminal CLA, A true value (high level voltage) is output from the output terminal ε0 of the AND circuit element AND0 constituting the first switch unit, and the potential of the select signal transmission line CSL becomes high level. This state corresponds to the selected state. In the selected state, a high level voltage is output from the trigger signal output terminal TRA connected to the select signal transmission line CSL, and is used as an input trigger signal for the adjacent light emitting element array chip 3. It is done.

  In the selected state, a high level voltage is input to one of the input terminals δ1 to δ4 of the AND circuit elements AND1 to AND4 constituting each of the second switch units connected to the select signal transmission line CSL. At this time, when high level gate signals are input from the gate signal input terminals G1 to G4, the AND circuit elements AND1 to AND4 output high level signals from the output terminals (first control electrodes) ε1 to ε4. Since the gate horizontal wirings GH1 to GH4 are individually connected to the output terminals (first control electrodes) ε1 to ε4 of the AND circuit elements AND1 to AND4, the output high level signals are passed through the gate horizontal wirings GH1 to GH4. The signal is transmitted and inputted to the gate electrodes β1 to β4 of the field effect transistors FET1 to FET4 connected to the gate lateral wirings GH1 to GH4. In this state, when high-level light emission signals are input from the light emission signal input terminals A1 to A4, the light emitting diodes LED1 to LED4 emit light.

  Thus, the AND circuit elements AND1 to AND4 provided as the switch elements operate so as to deliver the gate signal to the light emitting diodes LED1 to LED4 only during the time selected by the clock signal and the input trigger signal. Therefore, when a light-emitting device is configured using a plurality of light-emitting element array chips 3, a driving IC and a driving IC and a light-emitting signal input can be provided without connecting a driving IC for each of the plurality of light-emitting element array chips 3. Since the wiring with the terminals A1 to A4 and the gate signal input terminals G1 to G4 can be shared and driven in a time division manner, a light emitting element device that can be driven in a time division manner with a small number of driving ICs and wirings can be realized.

  FIG. 19 is a schematic equivalent circuit diagram showing a light emitting element array chip 4 as a fourth embodiment of the light emitting element array of the present invention. The difference in configuration from the light emitting element array chip 1 as the first embodiment shown in FIG. 1 is that in FIG. 8, the number of switch thyristors S is n = 5, and therefore the wiring of the gate lateral wiring GH The number is equal to n = 5, whereas the number of light emitting thyristors T constituting the light emitting element block B is one less than that, n−1 = 4. Further, there is a feature in the connection between the gate lateral wiring GH and the light emitting thyristor T constituting the light emitting element block B. Since other configurations are common, common portions are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 19, along the arrangement direction X of the light emitting thyristors T, the direction from the side close to the switch thyristor S to the side away from the switching thyristor S is defined as the X1 direction, and the opposite direction is defined as the X2 direction. The X direction is the sum of the X1 direction and the X2 direction. Here, numbers 1 to m are assigned to the light emitting element blocks in the X1 direction, and the light emitting thyristors T constituting the light emitting element blocks are sequentially numbered from the first to the nth in the X1 direction. Number up to -1. The n gate horizontal wirings GH are numbered from No. 1 to No. n in a predetermined order.

In the present embodiment, in the odd-numbered light emitting element block, the i ₁ (1 ≦ i ₁ ≦ n−1) th light emitting thyristor T and the j ₁ (1 ≦ j ₁ ≦ n) in the light emitting element block. -1) The horizontal gate line GHj ₁ is connected so as to satisfy i ₁ = j _{1. In} the even-numbered light emitting element block, the i ₂ (1 ≦ i ₂ ≦ n−1) in the light emitting element block is connected. ) Th light emitting thyristor T and the j ₂ (2 ≦ j ₂ ≦ n) th gate lateral wiring GHj ₂ are i ₂ + j ₂ = n + 1.
Connected to meet.

In this case, the light emitting thyristor T adjacent to the light emitting thyristor T connected to the first gate horizontal wiring GH1 in the X direction is connected to the second gate horizontal wiring GH2. The light emitting thyristor T connected to the j ₃ (2 ≦ j ₃ ≦ n−1) th gate horizontal wiring GHj _3.
The light-emitting thyristor T adjacent to each other in the X direction is connected to the j ₃ -1-th or the j ₃ +1 th one of horizontal gate line. The light emitting thyristor T adjacent to the Xth direction of the light emitting thyristor T connected to the nth gate horizontal wiring GHn is connected to the (n-1) th gate horizontal wiring GHn-1. Therefore, a gate signal (second selection signal) is input to the switch elements of the light emitting element array in the selected state, and is time-sequentially sequentially from the first gate horizontal wiring GH1 to the nth gate horizontal wiring GHn-1. When the control signal is output, the time lag of the light emission timing of the light emitting thyristors T adjacent to each other can be reduced, and further, the adjacent light emitting thyristors T are not connected to the same control signal transmission path. It is possible to prevent the light emitting thyristor T adjacent to the light from being emitted simultaneously.

  As a result, when the light-emitting device constituted by the light-emitting element array of the present invention is used as an exposure device that exposes the photosensitive drum, it is possible to suppress a significant shift in the timing of light emission between the light-emitting thyristors adjacent to each other. Therefore, discontinuous points do not occur at the exposure position where the photosensitive drum is exposed. Further, by preventing the light emitting thyristors T adjacent to each other from emitting light at the same time, unevenness in heat generation when the light emitting thyristors T emit light is suppressed, and light emission due to temperature changes of the light emitting thyristors T is achieved. Since the characteristics can be made uniform and the light generated from the light emitting thyristors T adjacent to each other can be prevented from interfering with each other, the photosensitive drum can be exposed accurately. As a result, in the image forming apparatus using the light emitting element array of the present invention, a recorded image with excellent image quality can be obtained.

  FIG. 20 is a schematic equivalent circuit diagram showing the light emitting element array chip 5 as the fifth embodiment of the invention. FIG. 21 is a part of a schematic equivalent circuit diagram showing the light-emitting element array chip 5 shown in FIG. 20, and shows the connection between the light-emitting thyristor T1, the switch thyristor S1, and the diode D1 and the wiring. is there. The light emitting element array chip 5 according to the embodiment of the present invention has a configuration in which the selection thyristor U of the light emitting element array chip 1 according to the first embodiment is replaced with a diode D. The set signal input terminal CSA is connected to a positive constant voltage source (Vcc). That is, the set signal is constant with respect to time. Since the light emitting element array chip 5 according to the embodiment of the present invention is the same as the light emitting element array chip 1 according to the first embodiment described above, the corresponding parts are denoted by the same reference numerals and description thereof is omitted. .

  In the present embodiment, the second switch unit includes n switch thyristors S1 to Sn, n diodes D1 to Dn, and n second pull-up resistors RP1 to RPn. In the present embodiment, n = 4. Hereinafter, the diodes D1 to Dn may be collectively referred to as the diode D when collectively referring to the diode D1 to Dn or when referring to an unspecified one.

  The anodes g1 to g4 of the diode D of the present embodiment (when generically referred to or unspecified, simply described as g) correspond to the anode e of the selection thyristor U of the above-described embodiments. The switch thyristor S is electrically connected to the N gate electrode d and one end of the second pull-up resistor RP. The cathodes h1 to h4 of the diode D of the present embodiment (when collectively referring to the unspecified one, simply described as h) are connected to the N gate electrode f of the selection thyristor U of each of the foregoing embodiments. Correspondingly, it is connected to the select signal transmission line CSL.

  Unlike the thyristor U for selection, the diode D does not have the gate electrode f, and is switched between the on state and the off state only by the potential difference between the anode g and the cathode h. Therefore, even if the set signal is a constant voltage, the ON state and the OFF state of the diode D can be switched by giving the select signal.

  FIG. 22 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 5. The plan view of the light-emitting element array chip 5 of the present embodiment is the same as the plan view shown in FIG. 8, and FIG. 22 is a cross-sectional view of the light-emitting element array chip 5 as seen from the section line VIII-VIII in FIG. It corresponds to.

  The diode D is changed from the fourth semiconductor layer 45 of the selection thyristor U and the ohmic contact layer 47 to the end of the third semiconductor layer 44 of the selection thyristor U near the second pull-up resistor RP. It is the structure which laminated | stacked. The metal layer 81 is made of, for example, titanium (Ti). The metal layer 81 and the third semiconductor layer 44 constitute a Schottky barrier diode.

  As shown in FIG. 22, the diode D is also preferably covered with the light shielding film 12 for the same reason as the first pull-up resistor RQ and the second pull-up resistor RP. This is to prevent the insulation between the second semiconductor layer 43 and the third semiconductor layer 44 from being impaired by excitation of electron-hole pairs by incident light from the outside.

  FIG. 23 is a block circuit diagram schematically showing a light emitting device 82 according to an embodiment of the present invention. Since the light-emitting device 82 of the present embodiment has the same configuration as the light-emitting device 10 of the first embodiment described above, the corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  In the light emitting device 82 of the present embodiment, the connection between the set signal output terminal η and the set signal bonding pad CSA of the light emitting device 10 of the first embodiment is connected to the positive voltage source (Vcc) and the set signal. In this configuration, the light emitting element array chip 1 of the light emitting device 10 according to the first embodiment is replaced with the light emitting element array chip 5 according to the fifth embodiment.

  FIG. 24 is a timing chart showing the operation of the light emitting device 82, where the horizontal axis represents the elapsed time from the reference time, and the vertical axis represents the signal level in terms of voltage or current. In the light emitting device 82 of the present embodiment, the selection thyristor U of the light emitting device 10 of the above-described embodiment is replaced with the diode D. Therefore, it is not necessary to supply a set signal to the set signal bonding pad CSA, and the high ( H) A constant voltage is applied at the level.

  The light emitting device 82 of the present embodiment performs the same operation as the light emitting device 10 of the above-described embodiment from time t1 to time t14. At time t15, the voltage of the input trigger signal output terminal φS connected to the trigger signal input terminal CSG1 of the first array chip L1 returns to the high (H) level, and the clock signal input terminal of the first array chip L1. The voltage of the first clock signal output terminal φ1 connected to CLA1 becomes low (L) level, and the second clock signal output terminal connected to the clock signal input terminal CLA2 of the second array chip L2 The voltage of φ2 becomes high (H) level. Then, the first array chip L1 is not in the selected state, and the second array chip L2 to which the input trigger signal is input from time t1 is in the selected state. Note that, as described in FIG. 7, in order to surely switch the selection state from the first array chip L1 to the second array chip L2, the second of the next selection state is performed. The rising of the voltage of the second clock signal output terminal φ2 connected to the array chip L2 may precede the falling of the first clock signal output terminal φ2.

  As described above, by selecting the array chips in the order in which the array chips L are arranged, time-division driving for each array chip L is possible. Further, the gate signal is sequentially applied from the first switch thyristor, so that time-division driving in the array chip L is possible. Further, in the light emitting element array chip 5 of the present embodiment, it is not necessary to provide a set signal, so that the configuration of the apparatus is simplified.

  FIG. 25 is a block circuit diagram schematically showing another embodiment of the light emitting device of the present invention. The light emitting device 83 shown in FIG. 25 is different from the light emitting device 82 shown in FIG. 14 by using two light emission signal drive ICs, for example, to a photosensitive drum by light emission when used in an image forming apparatus. This is to improve the writing speed. Portions common to FIGS. 23 and 25 are denoted by the same reference numerals, and description thereof is omitted.

  The light emitting device 83 according to the present embodiment includes a plurality of light emitting element array chips L1, L2,..., Lp-1, Lp (the symbol p is a positive even number) and a drive circuit for the light emitting element array chips 1 to Lp. A first light emission signal drive IC (Integrated Circuit) 133a and a second light emission signal drive IC 133b that supply a light emission signal, a gate signal drive IC 134 that supplies a gate signal, a clock signal, an input trigger signal, and a set signal It includes a select signal drive IC 135 for setting the light emitting element array chips L1 to Lp to the select state and a positive voltage source Vcc. In each array chip L, the light emitting elements T are arranged in a line along the arrangement direction X, and the light emitting directions from the respective light emitting elements T are aligned and mounted on the circuit board. Each drive IC outputs image information based on the control means 96 described above. In the present embodiment, the light-emitting element array chip 1 according to the first embodiment shown in FIG.

The first light emission signal drive IC 133a and the second light emission signal drive IC 133b have the same number (m) of light emission signal output terminals λ1 to λm as the light emission signal bonding pads A1 to Am of each array chip L, respectively. When each array chip L is numbered from one to the other in the arrangement direction X, the light emission signal bonding pads A of the first to p / 2th array chips are the light emission signal output terminals of the first light emission signal drive IC 133a. connected to λ. The light emission signal bonding pads A of the (p / 2 + 1) th to pth array chips L are connected to the second light emission signal driving IC. More specifically, when the light emitting signal output terminals λ1 to λm are numbered in order from the first to the m-th, the i ₁₂ (1) for each of the first to p / 2th array chips. ≦ i ₁₂ ≦ m) The light emission signal bonding pads Ai ₁₂ are electrically connected to each other, and further electrically connected to the i _12th light emission signal output terminal λi ₁₂ of the first light emission signal driver IC 133a. For the p / 2 + 1th to pth array chips, the i ₁₃ (1 ≦ i ₁₃ ≦ m) th light emitting signal bonding pads Ai ₁₃ are electrically connected to each other, and the first The light emission signal drive IC 133a is electrically connected to the i _13th light emission signal output terminal λi ₁₃ .

The gate signal driving IC 134 has the same number (four) of gate signal output terminals μ1 to μ4 as the gate signal bonding pads G1 to G4 of each array chip L. Each gate signal bonding pad G and the gate signal output terminal μ are connected by sharing wiring between different array chips. In this embodiment, the gate signal bonding pads G1 to G4 are numbered from No. 1 to No. 4 from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L. And the gate signal output terminals μ1 to μ4 are numbered from No. 1 to No. 4 to bond the i ₁₃ (1 ≦ i ₁₃ ≦ 4) th gate signal of each of the p array chips. The pads Gi ₁₃ are electrically connected to each other, and are further electrically connected to the i _13th gate signal output terminal μi ₁₃ .

The select signal driving IC 135 has one set signal output terminal η, one input trigger signal output terminal φS, and two clock signal output terminals φ1 and φ2. Among these, the set signal output terminal η is commonly connected between the set signal bonding pads CSA1 to CSAp of the respective light emitting element array chips L1 to Lp. The input trigger signal output terminal φS is an input trigger signal for the input trigger signal bonding pad CSG1 of the first light emitting element array chip L1 of the light emitting element array chip L and the input trigger signal of the (p / 2 + 1) th light emitting element array chip Lp / 2 + 1. Bonding pad CSGp / 2 + 1. The two clock signal output terminals φ1 and φ2 are individually connected to the two clock signal transmission paths CLL1 and CLL2, respectively. The clock signal bonding pads CLA between the light emitting element array chips L adjacent to each other are connected to different clock signal transmission paths CLL1 and CLL2, respectively. Specifically, in the case of the present embodiment in which p array chips (here, p is an even number of 4 or more) are mounted, in the arrangement direction X of the light emitting elements T constituting each array chip L. When each array chip is numbered from No. 1 to No. p from one side to the other along the line, the odd-numbered 2i ₁₈ −1 (1 ≦ i ₁₈ ≦ p / 2) array chip L a clock signal bonding pads CLA2i ₁₈ -1 and the first clock signal transmission line CLL1 are electrically connected, the 2i ₁₈ th is an even-numbered array chip L of _{(1 ≦ i 18 ≦ p /} 2) The clock signal bonding pad CLA2i ₁₈ and the second clock signal transmission line CLL2 are electrically connected.

  Thus, one input trigger signal output terminal φS is connected to the input trigger signal bonding pads CSG of the first and p / 2 + 1th two array chips L, and the first and p / 2 + 1th. Since both the clock signal bonding pads CLA of the second array chip L are connected to the first clock signal transmission line CLL1, the first and p / 2 + 1th two array chips L are used as clock signals first. Synchronously, the selected state is entered almost simultaneously. In this selected state, the output trigger signal output from the first array chip L1 is input as the input trigger signal of the adjacent second array chip L2, and from the p / 2 + 1th array chip Lp / 2 + 1. The output trigger signal thus output is input as an input trigger signal for the adjacent p / 2 + 2th array chip Lp / 2 + 2. When a high level clock signal is applied to the second clock signal transmission CLL2 at the next timing, the second and p / 2 + 2th array chips L are in the selected state. Subsequently, the first array chip L1 to the p / 2th array chip Lp / 2 are sequentially selected, and in parallel, the p / 2 + 1th array chip Lp / 2 + 1 to the pth array. Chip Lp is selected. Here, the first to p / 2th array chips L and the p / 2 + 1th to pth array chips L include first and second light emission signal driving ICs 133a and 133b. Therefore, it is possible to write image information by light emission at a speed twice that of the case of FIG.

  The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.

1 is a schematic equivalent circuit diagram showing a light-emitting element array chip 1 as a first embodiment of a light-emitting element array of the present invention. It is a graph which shows the forward voltage-current characteristic which is the relationship between the anode voltage of the thyristor T for light emission, and an anode current. FIG. 2 is a part of a schematic equivalent circuit diagram showing the light emitting element array chip 1 of FIG. 1. FIG. 4 is a logic circuit diagram representing the equivalent circuit diagram shown in FIG. 3 with logic circuit diagram symbols. It is a graph which shows an example of the operation characteristic in the light emitting element array chip 1 of 1st Embodiment. It is an equivalent circuit diagram which shows the connection relation of the 1st switch part of each light emitting element array chip 1 which comprises a light emitting device. 7 is a timing chart showing the operation of the equivalent circuit diagram shown in FIG. 6. It is a partial top view which shows the basic composition of the light emitting element array chip 1 of 1st Embodiment. FIG. 9 is a partial cross-sectional view showing a basic configuration of the light-emitting element array chip 1 as seen from a section line IX-IX in FIG. 8. FIG. 9 is a partial cross-sectional view illustrating a basic configuration of the light-emitting element array chip 1 as viewed from a cutting plane line XX in FIG. 8. FIG. 9 is a partial cross-sectional view illustrating a basic configuration of the light-emitting element array chip 1 as viewed from a section line XI-XI in FIG. 8. FIG. 9 is a partial cross-sectional view showing a basic configuration of the light-emitting element array chip 1 as seen from a section line XII-XII in FIG. 8. FIG. 9 is a partial cross-sectional view illustrating a basic configuration of the light-emitting element array chip 1 as viewed from a section line XIII-XIII in FIG. 8. 1 is a block circuit diagram schematically showing a light emitting device 10 according to an embodiment of the present invention. 3 is a timing chart showing the operation of the light emitting device 10. 1 is a side view showing a basic configuration of an image forming apparatus using a light emitting element array chip 1. FIG. It is a schematic equivalent circuit diagram which shows the light emitting element array chip | tip 2 as 2nd Embodiment of the light emitting element array of this invention. It is a schematic equivalent circuit diagram which shows the light emitting element array chip | tip 3 as the 3rd Embodiment of this invention. It is a schematic equivalent circuit diagram which shows the light emitting element array chip | tip 4 as the 4th Embodiment of this invention. It is a schematic equivalent circuit diagram which shows the light emitting element array chip 5 as the 5th Embodiment of this invention.

FIG. 21 is a part of a schematic equivalent circuit diagram showing the light-emitting element array chip 5 shown in FIG. 20. 4 is a partial cross-sectional view showing a basic configuration of a light emitting element array chip 5. FIG. It is a block circuit diagram showing typically light emitting device 82 of an embodiment of the invention. It is a timing chart which shows operation | movement of the light-emitting device 82, A horizontal axis represents the elapsed time from reference | standard time, and a vertical axis | shaft represents a signal level with the magnitude | size of a voltage or an electric current. It is a block circuit diagram which shows typically other embodiment of a light-emitting device.

Explanation of symbols

1 to 5 Light emitting element array chip 10, 82, 83 Light emitting device T1 to Tk (T) Light emitting thyristor S1 to Sn (S) Switch thyristor B1 to Bm (B) Light emitting element block a1 to ak (a) Light emitting thyristor Anode b1 to bk (b) N gate electrode of light emitting thyristor c1 to cn (c) anode of switching thyristor d1 to dn (d) N gate electrode of switching thyristor e1 to en (e) of thyristor U for selection Anode f1 to fn (f) N gate electrode of selection thyristor U GH1 to GHn (GH) Horizontal gate wiring (control signal transmission line)
A1 to Am (A) Light emission signal input terminal G1 to Gn (G) Gate signal input terminal CSA Set signal input terminal CSG Trigger signal input terminal CSL Select signal transmission path U1 to Un (U) Selection thyristor CL Clock thyristor TR Trigger Thyristors D1 to Dn (D) Diode RQ First pull-up resistor RP1 to RPn Second pull-up resistor RI1 to RIn Current limiting resistor 21 Semiconductor substrate 22, 32, 42, 52, 152, 172 First semiconductor layer 23, 33 , 43, 53, 153, 173 Second semiconductor layer 24, 34, 44, 54, 154, 174 Third semiconductor layer 25, 35, 45, 155 Fourth semiconductor layer 26 Back electrode 130, 133a, 133b Light emitting signal drive IC
131,134 Gate signal driving IC
132,135 Select signal drive IC
87 Image forming apparatus

Claims (19)

(A) a first switch unit that outputs a first selection signal and an output trigger signal when both a clock signal and an input trigger signal are provided as input signals;
(B) a first selection signal transmission path that is connected to the first switch section and transmits the first selection signal;
(C) Connected to the first selection signal transmission line and outputs a control signal when both the second selection signal and the first selection signal from the first selection signal transmission line are given as input signals n (N is an integer of 2 or more) second switch units;
(D) n control signal transmission lines that are individually connected to the n second switch units and transmit the control signal;
(E) A plurality of light emitting elements that are connected to any one of the n control signal transmission paths and emit light when both the light emission signal and the control signal from the connected control signal transmission path are provided as input signals. Including elements,
At least one of the light emitting elements is connected to each control signal transmission path, the light emitting element array. The plurality of light-emitting elements constitute a plurality of light-emitting element blocks including n or less light-emitting elements,
A light emitting element block composed of a plurality of light emitting elements is characterized in that the plurality of light emitting elements are individually connected to different control signal transmission paths, and a common light emission signal is input to the plurality of light emitting elements. The light-emitting element array according to claim 1. The plurality of light emitting elements are arranged in a line,
The light emitting element block is composed of n-1 (n is an integer of 4 or more) light emitting elements,
In an odd-numbered light emitting element block from one side to the other in the arrangement direction of the light emitting elements, i ₁ (i ₁ is 1 or more and n in the light emitting element block from the one to the other in the arrangement direction). -1 or less integer) light-emitting element and j ₁ (j ₁ is an integer greater than or equal to 1 and less than or equal to n-1) control signal transmission line are connected so as to satisfy i ₁ = j ₁ And
In the even-numbered light emitting element block from the one side of the arrangement direction toward the other side, the i ₂ (i ₂ is 1 ₂₎ in the light emitting element block from the one side of the arrangement direction toward the other side. or more and a n-1 an integer) th light emitting elements, a _j 2 _{(j 2} is 2 or more and is the following integer) th said control signal transmission channel _n, to meet the _{i 2 + j 2 = n +} 1 The light emitting element array according to claim 2, wherein the light emitting element array is connected to the light emitting element array. The light-emitting element array according to claim 2 or 3 includes a substrate and a bonding pad provided on one surface of the substrate,
The light emitting elements are provided on the one surface of the substrate and arranged in a substantially straight line,
The n control signal transmission lines and the first selection signal transmission line are provided on the one surface of the substrate along the arrangement direction of the light emitting elements,
The bonding pads are arranged to be spaced apart from each other along the arrangement direction of the light emitting elements,
An input trigger signal bonding pad connected to the first switch unit for inputting the input trigger signal;
A clock signal bonding pad connected to the first switch unit for inputting the clock signal;
The output trigger signal bonding pad connected to the first switch unit for outputting the output trigger signal;
A second selection signal bonding pad that is individually connected to each of the second switch units and for inputting the second selection signal;
Connected to the light emitting elements included in each of the light emitting element blocks, provided individually to give the light emitting signal for each light emitting element block, and having a smaller number of light emitting signal bonding pads than the number of light emitting elements. And
The light emitting device array, wherein the first switch unit and the second switch unit are disposed between adjacent bonding pads. The input trigger signal bonding pad is provided at one end of the substrate along the arrangement direction of the light emitting elements,
5. The light emitting element array according to claim 4, wherein the output trigger signal bonding pad is provided at the other end portion of the substrate along the arrangement direction of the light emitting elements. The first switch unit includes a clock thyristor including a light emitting thyristor and a trigger thyristor including a light emitting thyristor, and each gate electrode of these thyristors is connected to the first selection signal transmission path,
Each of the second switch units includes a switch thyristor including a diode and a light emitting thyristor, and a gate electrode of each switch thyristor is individually connected to the control signal transmission line, and the first switch via the diode. Connected to the selection signal transmission line,
Each light emitting element is composed of a light emitting thyristor composed of a light emitting thyristor, and a gate electrode of each light emitting thyristor is connected to any one of the control signal transmission lines,
The clock thyristor, the trigger thyristor, the switch thyristor, and the light emitting thyristor have either one of an anode and a cathode grounded in common, and the clock thyristor, the switch thyristor, and the light emitting thyristor have an anode and a cathode The other electrode is supplied with the clock signal, the second selection signal, and the light emission signal, respectively.
The clock thyristor is configured to change the voltage between the gate electrode and the ground when the input trigger signal is input to the gate electrode and the threshold voltage is lowered and the clock signal is input and transitions to the on state. Output to the first selection signal transmission line as one selection signal;
The trigger thyristor outputs a voltage between an anode and a cathode as the output trigger signal when the clock thyristor is on.
The switch thyristor is turned on when the first selection signal is input to the gate electrode and the threshold voltage is lowered through the diode biased in the forward direction, and the second selection signal is input. 6. The light-emitting element array according to claim 1, wherein when the transition is made, a voltage between the gate electrode and the ground is output as a control signal to the control signal transmission path. The first switch unit further includes a first resistor, and one end of the first resistor is connected to the first selection signal transmission path, and the light emitting thyristor is connected to the other end of the first resistor. When the cathodes of the light emitting thyristors are commonly grounded, a positive constant voltage is applied. When the anodes of the light emitting thyristors are commonly grounded, a negative constant voltage is applied.
The second switch unit further includes a second resistor, and one end of the second resistor is connected to the gate electrode of the switch thyristor, and the diode is sequentially connected to the other end of the second resistor. The light emitting element array according to claim 6, wherein a constant voltage is applied so as to be biased in the direction. The first switch unit includes a clock thyristor composed of a light emitting thyristor and a trigger thyristor composed of a light emitting thyristor, and gate electrodes of these thyristors are connected to the first selection signal transmission path,
Each of the second switch sections includes a selection thyristor composed of a light emitting thyristor and a switch thyristor composed of a light emitting thyristor, and the anode of the selection thyristor is connected to the gate electrode of the switch thyristor, and the gate of each selection thyristor An electrode is connected to the first selection signal transmission line, and a gate electrode of each switch thyristor is individually connected to the control signal transmission line,
Each light emitting element is constituted by a light emitting thyristor composed of a light emitting thyristor, and a gate electrode of each light emitting thyristor is connected to any one of the control signal transmission lines,
The clock thyristor, the trigger thyristor, the selection thyristor, the switch thyristor, and the light emitting thyristor have either one of an anode and a cathode grounded in common, and the clock thyristor, the switch thyristor, and the light emitting thyristor The clock signal, the second selection signal, and the light emission signal are respectively input to the other electrode of the anode and the cathode, and the other electrode of the selection thyristor is in the forward direction in synchronization with the clock signal. Is applied as a set signal,
The clock thyristor is configured to change the voltage between the gate electrode and the ground when the input trigger signal is input to the gate electrode and the threshold voltage is lowered and the clock signal is input to make a transition to the on state. Output to the first selection signal transmission line as one selection signal;
The trigger thyristor outputs a voltage between an anode and a cathode as the output trigger signal when the clock thyristor is on.
The switch thyristor has the second selection signal in a state where the voltage between the anode and the cathode of the selection thyristor that has been turned on by the first selection signal is input to the gate electrode and the threshold voltage is lowered. The voltage between the gate electrode and the ground is output to the control signal transmission line as the control signal when the signal is input and transitioned to the on state. Light emitting element array. The first switch unit further includes a first resistor, and one end of the first resistor is connected to the first selection signal transmission path, and the light emitting thyristor is connected to the other end of the first resistor. When the cathodes of the light emitting thyristors are commonly grounded, a positive constant voltage is applied. When the anodes of the light emitting thyristors are commonly grounded, a negative constant voltage is applied.
The second switch unit further includes a second resistor, and one end of the second resistor is connected to a gate electrode of the switch thyristor, and the other end of the second resistor is connected to the selection thyristor. 9. The light-emitting element array according to claim 8, wherein the set signal is input so that the anode and the cathode are biased forward.   10. The second selection signal input to each switch thyristor is provided via a third resistor connected to the anode or cathode of each switch thyristor. The light emitting element array as described in one.   The light emitting element array according to any one of claims 6 to 10, wherein the first switch part, the second switch part, and the light emitting element are formed of light emitting thyristors having the same layer configuration.   The light-blocking means or the light-reducing means for light-blocking or reducing the light emitted from the light-emitting thyristors constituting the first switch section and the second switch section, respectively. The light emitting element array described in 1.   The first and second resistors are, from the side close to the substrate, a first semiconductor layer of one of P-type or N-type, a second semiconductor layer of the other conductivity type, and one of the conductivity types. 10. The light-emitting element array according to claim 7, wherein the light-emitting element array is configured using the third semiconductor layer among the semiconductor films stacked in the order of the third semiconductor layer.   14. A light shielding means or a light reducing means for covering the first and second resistors is provided in order to shield or reduce light incident on the first and second resistors. The light emitting element array of description. A light emitting device according to any one of claims 2 to 5 and claim 6 subordinate to any one of claims 2 to 5, and further to any one of claims 7 to 10 subordinate to claim 6. A light emitting element array group in which four or more arrays are arranged in a row;
A plurality of clock signal transmission lines connected to at least one light emitting element array to supply the clock signal;
An input trigger signal drive circuit connected to the first switch portion of the light emitting element array provided at one end in the arrangement direction of the light emitting element array group and supplying the input trigger signal to the first switch portion. When,
A clock signal drive circuit connected to the plurality of clock signal transmission paths and supplying the clock signal individually to each clock signal transmission path;
A second selection signal driving circuit that is individually connected to each second switch section in each light emitting element array and supplies the second selection signal common to each light emitting element array for each second switch section;
A light emission signal drive circuit that is individually connected to each light emitting element block in each light emitting element array and supplies the light emission signal common to each light emitting element array for each light emitting element block;
In the light emitting element array group, the input trigger of the light emitting element array in which the output trigger signal of the light emitting element array arranged on the one end side in the arrangement direction is arranged adjacent to the other end side in the arrangement direction. Input as a signal,
Each light emitting element array adjacent along the arrangement direction is individually connected to the plurality of clock signal transmission paths. Claim 8 subordinate to any one of claims 2 to 5, and further, four or more light emitting element arrays according to any one of claims 9 to 14 subordinate to claim 8 are arranged in a line. A light emitting element array group,
A plurality of clock signal transmission lines connected to at least one light emitting element array to supply the clock signal;
An input trigger signal drive circuit connected to the first switch portion of the light emitting element array provided at one end in the arrangement direction of the light emitting element array group and supplying the input trigger signal to the first switch portion. When,
A clock signal drive circuit connected to the plurality of clock signal transmission paths and supplying the clock signal individually to each clock signal transmission path;
A set signal drive circuit connected to the other electrode of the anode and cathode of the selection thyristor of each second switch portion of each light emitting element array and supplying the set signal common to the light emitting element arrays When,
A second selection signal driving circuit that is individually connected to each second switch section in each light emitting element array and supplies the second selection signal common to each light emitting element array for each second switch section;
A light emission signal drive circuit that is individually connected to each light emitting element block in each light emitting element array and supplies the light emission signal common to each light emitting element array for each light emitting element block;
The light emitting element array group includes the input trigger signal of the light emitting element array in which the output trigger signal of the light emitting element array arranged on the one end side in the arrangement direction is adjacent to the other side in the arrangement direction. Entered as
Each light emitting element array adjacent along the arrangement direction is individually connected to the plurality of clock signal transmission paths. The set signal driving circuit supplies a signal substantially equal to the potential of the common electrode when the clock signal driving circuit changes the clock signal transmission path to which the clock signal is supplied. Supply set signal,
The second selection signal drive circuit and the light emission signal drive circuit supply the second selection signal and the light emission signal after the set signal drive circuit starts supplying the set signal, respectively. The light-emitting device according to claim 16. The light emitting device according to claim 15,
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
Fixing means for fixing the developer transferred to the recording sheet,
The input trigger signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive circuit are configured to generate the input trigger signal, the clock signal, and the second selection based on image information. An image forming apparatus that supplies a signal and the light emission signal, respectively. A light emitting device according to claim 16 or 17,
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
Fixing means for fixing the developer transferred to the recording sheet,
The input trigger signal drive circuit, the set signal drive circuit, the clock signal drive circuit, the second selection signal drive circuit, and the light emission signal drive circuit are based on image information, The image forming apparatus, wherein the set signal, the clock signal, the second selection signal, and the light emission signal are respectively supplied.

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