JP5543124B2 - Light emitting thyristor, light emitting element array, light emitting device, and image forming apparatus - Google Patents

Description

  In the thyristor formed by sequentially laminating an N-type semiconductor layer and a P-type semiconductor layer, the present invention extracts light emitted from the inside of the semiconductor layer to the outside and changes the light emission state from the outside electrically. The present invention relates to a light emitting thyristor that can be controlled by irradiation and has improved light emission intensity and light receiving sensitivity. The present invention also relates to a light emitting element array using the light emitting thyristor. The present invention also relates to a self-scanning light-emitting device in which the light-emitting thyristor is integrated as a transfer switch element by light excitation, and further relates to an image forming apparatus using the light-emitting device.

  In a light-emitting thyristor including a plurality of semiconductor layers stacked in the thickness direction and formed by epitaxial growth, the semiconductor layer formed as NPN or PNP forms a phototransistor. Therefore, the current amplification factor β can be obtained.

  For the base and the emitter, the current amplification factor β can be obtained by calculation from the majority carrier concentration, the minority carrier diffusion coefficient, the minority carrier diffusion length, and the thickness of the base. There is a problem that the smaller the value of the current amplification factor β, the more easily the emission intensity depends on the current amplification factor β rather than the carrier concentration. Therefore, it is desirable that the value of the current amplification factor β is higher than a certain level.

  As a first conventional technique, a technique of forming a light-emitting thyristor with four layers of PNPN is known (for example, see Patent Document 1). When the current amplification factor β in the first conventional technique is obtained by calculation, it is a value of about 145, and the emission intensity is saturated as the N-type carrier concentration of the layer constituting the collector increases, so that sufficient emission intensity is obtained. There is a problem that cannot be obtained.

The current amplification factor β is also related to the threshold voltage V _BO that is required to be applied at a minimum to cause the light-emitting thyristor to emit light. This threshold voltage V _BO needs to be set larger than a certain level.

  As a second prior art, a first semiconductor layer of one of N-type and P-type conductivity, a second semiconductor layer of a conductivity type opposite to the first semiconductor layer, and the same conductivity as the first semiconductor layer There is known a light emitting thyristor in which a third semiconductor layer of a type and a fourth semiconductor layer of a conductivity type opposite to the first semiconductor are laminated in this manner (for example, see Patent Document 2).

  When the current amplification factor β in the second prior art is obtained by calculation, it exceeds 2000 and is a sufficiently large current amplification factor β.

JP 2001-308385 A JP 2007-180460 A

In order to sufficiently increase the threshold voltage V _BO that needs to be applied in order to emit light, among the layers for forming each transistor type layer, the carrier concentration of the central layer is increased, or It is necessary to set a large thickness dimension of the layer. When the current amplification factor β is large, there is a problem that a required value for the carrier concentration or thickness dimension of the central layer is further increased. Further, if the carrier concentration of the central layer is increased or the thickness dimension is set to be large, there is a problem that the value of the current amplification factor β is decreased.

  The object of the present invention is to suppress the influence of the current amplification factor β on the emission intensity without setting the carrier concentration and the thickness dimension of the center layer among the layers for forming the transistor type layer large. A light-emitting thyristor, a light-emitting element array including a light-emitting element formed thereby, a light-emitting device including the light-emitting element array, and an image forming apparatus including the light-emitting device are provided.

The light-emitting thyristor according to the present invention has the same conductivity as the first semiconductor layer on the substrate, the first semiconductor layer of one of N-type and P-type conductivity, the second semiconductor layer of the opposite conductivity type to the first semiconductor layer, and the first semiconductor layer. In the light emitting thyristor in which the third semiconductor layer of the type and the fourth semiconductor layer of the conductivity type opposite to the first semiconductor layer are stacked in this order,
The band gap of the third semiconductor layer is substantially the same as the band gap of the second semiconductor layer, and is narrower than the band gaps of the first and fourth semiconductor layers,
The third semiconductor layer includes a first region on the substrate side and a second region on the opposite side of the substrate, and the impurity concentration of the first region is lower than the impurity concentration of the second region. And less than 1 × 10 ¹⁶ (cm ⁻³ ),
The impurity concentration of the second semiconductor layer is substantially the same as or higher than the impurity concentration of the first region of the third semiconductor layer, and lower than the impurity concentration of the first semiconductor;
The impurity concentration of the fourth semiconductor layer, Ri substantially equal to or higher concentrations der and impurity concentration of the second region of the third semiconductor layer,
The value of the current amplification factor, characterized in der Rukoto 1000 or more.

According to the light-emitting thyristor of the present invention, the impurity concentration of the first region is 5 × 10 ¹⁵ (cm ⁻³ ) or more.

  According to the light-emitting thyristor of the present invention, a fifth semiconductor layer having the same conductivity type as the fourth semiconductor layer is stacked on the opposite side of the fourth semiconductor layer from the substrate in the first light-emitting thyristor. The band gap of the fifth semiconductor layer is substantially the same as or wider than the band gap of the fourth semiconductor layer, and the impurity concentration of the fifth semiconductor layer is substantially the same as or higher than the impurity concentration of the fourth semiconductor layer. It is characterized by high concentration.

Further, according to the light emitting element array of the present invention,
(A) A first control signal is output when a first signal is input to the first electrode, the second electrode, and the first electrode, and a second signal is input to the second electrode. N (n is an integer of 2 or more) switch elements including one control electrode;
(B) n signal transmission lines individually connected to the first control electrodes;
(C) a third electrode and a second control electrode connected to any one of the n signal transmission lines, wherein a third signal is input to the third electrode, and A light emitting element array including a plurality of light emitting elements that emit light when a control signal is input to the second control electrode,
Each signal transmission line is connected to at least one second control electrode of the light emitting element,
The first electrodes of the n switch elements are electrically connected to each other;
The switch element and the light-emitting element are configured to include the light-emitting thyristor having a cathode or an anode as a common electrode, and the switch element is further configured to include first and second resistors,
(A) When the cathode is a common electrode,
The N gate electrode of the light emitting thyristor constituting the switch element is connected to one end of each of the first and second resistors,
A positive voltage is applied to the other electrode of the first resistor with respect to the common electrode,
The first electrode is the other end of the second resistor;
The second electrode is an anode of a light-emitting thyristor constituting a switch element;
The third electrode is an anode of a light emitting thyristor constituting a light emitting element,
The first control electrode is an N gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode is an N gate electrode of a light emitting thyristor constituting a light emitting element,
(B) When the anode is a common electrode,
The P gate electrode of the light emitting thyristor constituting the switch element is connected to one end of each of the first and second resistors,
A negative voltage is applied to the other electrode of the first resistor with respect to the common electrode,
The first electrode is the other end of the second resistor;
The second electrode is a cathode of a light emitting thyristor constituting a switch element,
The third electrode is a cathode of a light emitting thyristor constituting a light emitting element,
The first control electrode is a P gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode is a P gate electrode of a light emitting thyristor constituting a light emitting element.

According to the light emitting device of the present invention,
(A) A first control signal is output when a first signal is input to the first electrode, the second electrode, and the first electrode, and a second signal is input to the second electrode. N (n is an integer of 2 or more) switch elements including one control electrode;
(B) n signal transmission lines individually connected to the first control electrodes;
(C) a third electrode and a second control electrode connected to any one of the n signal transmission lines, wherein a third signal is input to the third electrode, and A light emitting element array including a plurality of light emitting elements that emit light when a control signal is input to the second control electrode,
Each signal transmission line is connected to at least one second control electrode of the light emitting element,
The first electrodes of the n switch elements are electrically connected to each other;
The switch element and the light emitting element are configured to include the light emitting thyristor having a cathode or an anode as a common electrode, and the switch element is further configured to include a resistor,
(A) When the cathode is a common electrode,
The N gate electrode of the light emitting thyristor constituting the switch element is connected to one end of the resistor,
The first electrode is the other end of the resistor;
The second electrode is an anode of a light-emitting thyristor constituting a switch element;
The third electrode is an anode of a light emitting thyristor constituting a light emitting element,
The first control electrode is an N gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode is an N gate electrode of a light emitting thyristor constituting a light emitting element,
(B) When the anode is a common electrode,
The P gate electrode of the light emitting thyristor constituting the switch element is connected to one end of the resistor,
The first electrode is the other end of the resistor;
The second electrode is a cathode of a light emitting thyristor constituting a switch element,
The third electrode is a cathode of a light emitting thyristor constituting a light emitting element,
The first control electrode is a P gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode includes a light emitting element array unit including a plurality of light emitting element arrays which are P gate electrodes of light emitting thyristors constituting the light emitting element,
A first drive circuit electrically connected to the first electrode and supplying the first signal;
A second drive circuit electrically connected to the second electrode and supplying the second signal;
A third drive circuit electrically connected to the third signal and supplying the third signal;
The first drive circuit includes first signal level setting means for setting a potential of the high level or the low level of the first signal having a high level and a low level.

  According to the light emitting device of the present invention, the light emitting device includes a light shielding means or a light reducing means for shielding or reducing light emitted from the light emitting thyristor constituting the switch element.

According to the image forming apparatus of the present invention, the light emitting device;
Driving means for driving the light emitting device based on image information;
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
And fixing means for fixing the developer transferred to the recording sheet.

  According to the light emitting thyristor of the present invention, since the band gap of the fourth semiconductor layer (P-type) is larger than the band gap of the third semiconductor layer (N-type), a potential barrier is formed at the interface between the two semiconductor layers, The electrons injected from the first semiconductor layer can be confined, and the electron density in the third semiconductor layer (N-type) can be increased. Further, since the third semiconductor layer (N-type) is divided into two layers of the first region and the second region, the impurity concentration of the second region on the fourth semiconductor layer (P-type) side is increased, so that the second region The electron density in the thermal equilibrium state at 1 is increased. Further, the density of holes injected from the fourth semiconductor layer into the second region is increased by making the impurity concentration of the fourth semiconductor layer (P-type) substantially the same as or higher than the impurity concentration of the second region. be able to. With the above settings, holes and electrons can be efficiently recombined in the second region to emit light, and the internal quantum efficiency can be increased.

  In addition, the band gap of the fourth semiconductor layer (P-type), which is the light extraction direction, is wider than the band gap of the second region, which is the main light emitting layer, and thus does not serve as an absorption layer for the emitted light. Since the main light-emitting layer is the second region close to the light extraction direction, absorption by the main light-emitting layer itself is not a problem, and according to the present invention, a light-emitting thyristor excellent in light extraction efficiency is provided. be able to.

Further, by setting the impurity concentration in the first region to the above value, the value of the current amplification factor can be sufficiently increased, and among the layers forming the transistor type layers, the thickness dimension of the center layer and It is possible to achieve both a low carrier concentration and a sufficiently large threshold voltage V _BO required for light emission. Therefore, the influence of the current amplification factor on the emission intensity can be suppressed.

  Further, according to the light emitting thyristor of the present invention, the fifth semiconductor layer (P type) having a high impurity concentration is interposed between the ultrathin ohmic contact layer and the fourth semiconductor layer (P type), so that the anode electrode Good ohmic contact can be obtained between the two. The band gap of the fifth semiconductor layer (P type) is substantially the same as or wider than the band gap of the fourth semiconductor layer (P type), so that it does not become an absorption layer for light emitted inside, and the light extraction efficiency is reduced. I will not let you.

  According to the light emitting element array of the present invention, the light emitting element array includes n switch elements (n is an integer of 2 or more) that outputs a control signal when both the first signal and the second signal are input; Including n signal transmission paths through which the control signal is transmitted, and a plurality of (n or more) light emitting elements that emit light when the third signal is input together with the control signal from the signal transmission path. Composed. Since the first electrodes of the switch elements are electrically connected to each other between the switch elements, a common first signal can be given to all the switch elements included in the light emitting element array.

  When a common first signal is input to each switch element constituting the light emitting element array, a control signal is output to a signal transmission path connected to the switch element to which the second signal is input. Further, when the third signal is input to the light emitting element connected to the signal transmission path through which the control signal is output, the light emitting element emits light. Conversely, when the first signal common to the light emitting element array is not input, each switch element does not output a control signal even if the second signal is input. Even if it is input, the light emitting element to which the third signal is input does not emit light.

  Therefore, when a light-emitting device is configured using a plurality of light-emitting element arrays, it is possible to select which light-emitting element array to which the light-emitting elements belong to emit light according to the first signal (hereinafter, the first signal is input). It is said that the light emitting element array being selected is in a selected state). Therefore, a driving IC for giving a second signal and a third signal to each light emitting element array by sequentially giving a first signal to each light emitting element array constituting the light emitting device to make a selected state, and each light emitting element Time-division driving can be performed in which the wiring between the element and the driving IC is shared between the plurality of light emitting element arrays. As described above, when the light emitting device is configured by using the light emitting element array of the present invention, the driving IC and the wiring can be shared between the respective light emitting element arrays. A light emitting device can be realized.

  The switch element includes a light emitting thyristor and first and second resistors, and the light emitting element includes a light emitting thyristor. Here, the light-emitting thyristor constituting the switch element and the light-emitting element is used with a cathode or an anode as a common electrode (potential is Vg = 0 volts).

  When the cathode is the common electrode, the switch element is configured by connecting the N gate electrode of the light-emitting thyristor, one end of the first resistor, and one end of the second resistor. A positive voltage is applied to the other end of the first resistor with a cathode, which is a common electrode, as a reference potential. In this case, the other end of the second resistor corresponds to the first electrode for inputting the first signal, the anode of the light emitting thyristor corresponds to the second electrode for inputting the second signal, and the light emitting thyristor of the light emitting thyristor. The N gate electrode corresponds to a first control electrode for outputting a control signal. The light emitting element is composed of a light emitting thyristor. The third electrode for inputting a third signal corresponds to the anode of the light emitting thyristor, and the second control electrode for inputting a control signal is N of the light emitting thyristor. Corresponds to the gate electrode.

An example of the circuit operation by the above circuit configuration is shown.
As a first signal, a low level signal (with a potential of 0 volts) is applied to the other end of the second resistor, and a positive voltage applied to the other end of the first resistor is Vcc volts. To do. In the state where the first signal is not input, it is assumed that a high level voltage (Vcc volts) having the same potential as Vcc volts is applied to the other end of the second resistor. A voltage corresponding to each resistance value of the first and second resistors is applied to the N gate electrode of a light emitting thyristor (hereinafter referred to as a switch thyristor) constituting the switch element, so that the first signal is input. In a state in which the first signal is not applied, Vcc volts is applied. In a state in which the first signal is input, a partial pressure of Vcc volts (Vd volts) is applied.

  In addition, a high level signal is applied to the anode of the switch thyristor as the second signal, and a low level voltage (with a potential of 0 volts) is applied to the anode of the switch thyristor when the second signal is not input. Suppose that The high level of the second signal is selected as a value at which the switch thyristor transitions from the off state to the on state when the second signal is input while Vd volts is applied to the N gate of the switch thyristor. . Therefore, when the first signal is input and the high level of the second signal is input while Vd volts is applied to the N gate of the switch thyristor, the switch thyristor transitions to the ON state. When the switch thyristor transitions to the ON state, the N gate electrode of the switch thyristor corresponding to the first control electrode transitions from Vd to approximately 0 volts, and approximately 0 volts is output as a control signal. When the second signal is not input and a low level voltage is applied to the anode of the switch thyristor, the switch thyristor remains off regardless of whether the first signal is input. To do. That is, the switch thyristor functions as an AND circuit that shifts to an ON state only when the first and second signals are input and outputs a control signal.

  A light-emitting thyristor constituting the light-emitting element (hereinafter referred to as a light-emitting thyristor) is assumed to have a current-voltage characteristic such as a threshold voltage equal to that of a switch thyristor. In addition, a high level signal is applied to the anode of the light emitting thyristor as the third signal, and a low level voltage (with a potential of 0 volts) is applied to the anode of the light emitting thyristor when the third signal is not input. Suppose that The high level of the third signal is a state in which Vd or Vcc is applied to the N gate electrode of the light emitting thyristor, and even if the third signal is input, the light emitting thyristor remains off, and the light emitting thyristor When the third signal is input in a state where a control signal of approximately 0 volts is applied to the N gate electrode, the light emitting thyristor is selected as a value that shifts to the on state. Therefore, when the first signal is input and the control signal is input to the N gate electrode of the light emitting thyristor and the third signal is input, the light emitting thyristor is changed from the off state to the on state. Transition to emit light. In addition, when at least one of the first and second signals is not input and the control signal is not input, the light emitting thyristor is turned off regardless of whether the third signal is input or not. Maintain state. That is, the light emitting thyristor emits light only when all the first, second, and third signals are input.

  Therefore, according to the present invention, for example, a light emitting element can be selectively provided by providing the first to third signals with a simple circuit configuration using a light emitting thyristor without using a complicated semiconductor device such as a NAND gate or an inverter. Since a logic circuit that emits light can be configured, a light-emitting element array that is easy to design and that has a simple manufacturing process can be realized.

  When the anode of the light emitting thyristor is used as a common electrode, the polarity of the light emitting thyristor is reversed, the polarity of the voltage applied to the other end of the first resistor is reversed, and the conductivity of the gate electrode of the light emitting thyristor is reversed. If the types are reversed, the above-described logic circuit can be realized in the same manner.

  According to the light emitting device of the present invention, the light emitting element array includes n switch elements (n is an integer of 2 or more) that outputs a control signal when both the first signal and the second signal are input; A configuration including n signal transmission paths through which a control signal is transmitted, and a plurality of (n or more) light emitting elements that emit light when a third signal is input together with the control signal from the signal transmission path. Is done. Since the first electrodes of the switch elements are electrically connected to each other between the switch elements, a common first signal can be given to all the switch elements included in the light emitting element array.

  When a common first signal is input to each switch element constituting the light emitting element array, a control signal is output to a signal transmission path connected to the switch element to which the second signal is input. Further, when the third signal is input to the light emitting element connected to the signal transmission path through which the control signal is output, the light emitting element emits light. Conversely, when the first signal common to the light emitting element array is not input, each switch element does not output a control signal even if the second signal is input. Even if it is input, the light emitting element to which the third signal is input does not emit light.

  The light emitting device includes a plurality of the light emitting element arrays, a first drive circuit that supplies a first signal to each light emitting element array, a second drive circuit that supplies a second signal, and a third signal that supplies a third signal. 3 drive circuits. Therefore, in the light emitting device of the present invention configured by using a plurality of the light emitting element arrays, it is possible to select which light emitting element array to which the light emitting elements belong to emit light by the first signal (hereinafter, the first signal is The input light-emitting element array is said to be in a selected state), and some of the plurality of light-emitting element arrays are selected, and the light-emitting element array that is not in the selected state may receive the second signal and the third signal. It is possible to prevent light emission. A light emitting device array and a second and a third driving circuit for providing a second signal and a third signal by sequentially applying a first signal to each light emitting device array constituting the light emitting device to make the selected state. The light-emitting device can be stably operated by performing time-division driving in which the wiring between the plurality of light-emitting element arrays is shared. Therefore, the number of driving circuits and the number of layers of the board on which the driving circuit is mounted can be reduced, the area of the light emitting element array and the driving circuit mounting board can be reduced, and the apparatus can be operated in a small size and stably. A light emitting device can be realized.

  Since the signal level of the first signal is set by first signal level setting means provided outside the light emitting element array, the circuit of the light emitting element array can be simplified and the chip size of the light emitting element array can be reduced. can do. In addition, since only one first signal level setting unit is provided in the first driving circuit shared by the plurality of light emitting element arrays, the first signal level setting unit as a whole is compared with the case where the same function is provided in each light emitting element array. The structure can be simplified without reducing the function of the light emitting device.

  The switch element includes a light emitting thyristor and a resistor, and the light emitting element includes a light emitting thyristor. Here, the light-emitting thyristor constituting the switch element and the light-emitting element is used with a cathode or an anode as a common electrode (potential is Vg = 0 volts).

  When the cathode is the common electrode, the switch element is configured by connecting the N gate electrode of the light emitting thyristor and one end of the first resistor. In this case, the other end of the resistor corresponds to the first electrode for inputting the first signal, the anode of the light emitting thyristor corresponds to the second electrode for inputting the second signal, and the N gate electrode of the light emitting thyristor. Corresponds to a first control electrode for outputting a control signal. The light emitting element is composed of a light emitting thyristor. The third electrode for inputting a third signal corresponds to the anode of the light emitting thyristor, and the second control electrode for inputting a control signal is N of the light emitting thyristor. Corresponds to the gate electrode.

An example of the circuit operation by the above circuit configuration is shown.
As the first signal, a low level signal (with a potential of 2.5 volts) or a high level signal (with a potential of 5 volts) is applied to the other end of the resistor. An N gate electrode of a light emitting thyristor (hereinafter referred to as a switch thyristor) constituting the switch element has a low level and a high level suitable for switching the switch thyristor by the first signal level setting means of the first drive circuit. A first signal in which each potential of the level is set in advance is input. The first signal level setting means is composed of, for example, a plurality of resistors connected in series, and the high level of the first signal is determined according to the voltage output from the middle connection portion of the plurality of resistors connected in series. A level or low level potential is set. The potential is controlled by the voltage division ratio of a plurality of resistors.

  In addition, a high level signal is applied to the anode of the switch thyristor as the second signal, and a low level voltage (with a potential of 0 volts) is applied to the anode of the switch thyristor when the second signal is not input. Suppose that The high level of the second signal is selected as a value at which the switch thyristor transitions from the off state to the on state when the second signal is input while Vd volts is applied to the N gate of the switch thyristor. . Therefore, when the first signal is input and the high level of the second signal is input while Vd volts is applied to the N gate of the switch thyristor, the switch thyristor transitions to the ON state. When the switch thyristor transitions to the ON state, the N gate electrode of the switch thyristor corresponding to the first control electrode transitions from Vd to approximately 0 volts, and approximately 0 volts is output as a control signal. When the second signal is not input and a low level voltage is applied to the anode of the switch thyristor, the switch thyristor remains off regardless of whether the first signal is input. To do. That is, the switch thyristor functions as an AND circuit that shifts to an ON state only when the first and second signals are input and outputs a control signal.

  A light-emitting thyristor constituting the light-emitting element (hereinafter referred to as a light-emitting thyristor) is assumed to have a current-voltage characteristic such as a threshold voltage equal to that of a switch thyristor. In addition, a high level signal is applied to the anode of the light emitting thyristor as the third signal, and a low level voltage (with a potential of 0 volts) is applied to the anode of the light emitting thyristor when the third signal is not input. Suppose that The high level of the third signal is a state in which Vd or Vcc is applied to the N gate electrode of the light emitting thyristor, and even if the third signal is input, the light emitting thyristor remains off, and the light emitting thyristor When the third signal is input in a state where a control signal of approximately 0 volts is applied to the N gate electrode, the light emitting thyristor is selected as a value that shifts to the on state. Therefore, when the first signal is input and the control signal is input to the N gate electrode of the light emitting thyristor and the third signal is input, the light emitting thyristor is changed from the off state to the on state. Transition to emit light. In addition, when at least one of the first and second signals is not input and the control signal is not input, the light emitting thyristor is turned off regardless of whether the third signal is input or not. Maintain state. That is, the light emitting thyristor emits light only when all the first, second, and third signals are input.

  Therefore, according to the present invention, for example, a light emitting element can be selectively provided by providing the first to third signals with a simple circuit configuration using a light emitting thyristor without using a complicated semiconductor device such as a NAND gate or an inverter. Since a logic circuit that emits light can be configured, a light-emitting device that is easy to design and that has a simple manufacturing process can be realized.

  When the anode of the light-emitting thyristor is used as a common electrode, the above-described logic circuit can be realized in the same manner if the polarity of the light-emitting thyristor is reversed and the conductivity type of the gate electrode of the light-emitting thyristor is reversed.

  According to the light emitting device of the present invention, the light emitting device includes a light shielding means or a light reducing means for shielding or reducing the light emitted from the switch thyristor. Since the light shielding means or the light reducing means works so that the light emitted when the switching thyristor is switched does not enter the light emitting thyristor, the threshold voltage of the light emitting thyristor due to the light can be prevented from changing. Therefore, when the light emitting element and the switch element are constituted by light emitting thyristors, the light emitting element array can be stably operated.

  According to the image forming apparatus of the present invention, the light emitting device is driven by the driving unit based on the image information, and the light from the light emitting device is condensed on the charged photosensitive drum by the light collecting unit. The body drum is exposed to form an electrostatic latent image on its surface. When the developer is supplied to the photosensitive drum on which the electrostatic latent image is formed by the developer supplying means, the developer adheres to the photosensitive drum and an image is formed. An image formed with the developer on the photosensitive drum is transferred to the recording sheet by the transfer unit, and the developer transferred to the recording sheet is fixed by the fixing unit, whereby an image is formed on the recording sheet.

  The switch elements emit light in order along the scanning direction, but the switch elements and the light emitting elements are separated from each other, and the photosensitive drum is exposed by light emission of the light emitting elements, and the photosensitive drum is exposed by light emission of the switch elements. Therefore, a recorded image with excellent quality can be obtained.

  In addition, the light-emitting element for exposing the photosensitive drum and the switch element for signal transfer can be integrated so that the circuit board for mounting the light-emitting device can be downsized. It is possible to reduce the number of wire bonds to the circuit board and the number of drive ICs to be mounted on the circuit board. Therefore, the circuit board can be reduced in size and cost.

It is sectional drawing which shows the basic composition of the light emitting thyristor 115 of the 1st Embodiment of this invention, and is a figure which shows the impurity concentration and band gap of each layer. In the light emitting thyristor 115 according to the first embodiment of the present invention, it is a diagram showing the light emission intensity of the light emitting thyristor 115 when the impurity concentration of the second region 106 is changed. In the light emitting thyristor having the NPN layer structure, the relationship between the concentration of the N-type carrier and the light emission intensity of the semiconductor layer forming the collector is plotted with respect to a plurality of current amplification factors β. It is sectional drawing which shows the basic composition of the light emitting thyristor 116 of the 2nd Embodiment of this invention, and is a figure which shows the impurity concentration and band gap of each layer. It is a partial top view which shows the basic composition of the light emitting element array chip 1 of one Embodiment of this invention. FIG. 6 is a partial cross-sectional view illustrating a basic configuration of the light-emitting element array chip 1 as seen from a section line VI-VI in FIG. 5. FIG. 6 is a partial cross-sectional view showing a basic configuration of the light-emitting element array chip 1 as seen from a section line VII-VII in FIG. 5. FIG. 6 is a partial cross-sectional view illustrating a basic configuration of the light-emitting element array chip 1 as viewed from a section line VIII-VIII in FIG. 5. 1 is a block circuit diagram schematically showing a light emitting device 10 according to an embodiment of the present invention. 3 is a timing chart showing the operation of the light emitting device 10. It is a graph which shows the forward voltage-current characteristic which is the relationship between the anode voltage of the thyristor T for light emission, and an anode current. 2 is a side view showing a basic configuration of an image forming apparatus 87 having a light emitting device 10. FIG.

  Embodiments of a light-emitting thyristor of the present invention and a light-emitting device and an image forming apparatus of the present invention using the same will be described below with reference to the drawings.

  FIG. 1 shows a sectional view of the light-emitting thyristor 115 according to the first embodiment of the present invention, and the impurity concentration and band gap of each layer constituting the light-emitting thyristor 115. Note that the impurity concentration and band gap values in FIG. 1 show a desirable example, and the effects of the present invention are not limited to these values.

First, the structure of the light emitting thyristor 115 shown in FIG. 1 will be described.
A light-emitting thyristor 115 shown in FIG. 1 includes an N-type first semiconductor layer 102, a P-type second semiconductor layer 103, an N-type third semiconductor layer 104, and a P-type fourth semiconductor on an N-type semiconductor substrate 101. By laminating the layers 107 in this order, an NPNP thyristor structure is formed. Here, the third semiconductor layer 104 includes two layers of a first region 105 on the substrate side and a second region 106 on the opposite side of the substrate, and each of these layers is formed of an N-type semiconductor. Further, a P-type semiconductor ohmic contact layer 109 for making good ohmic contact with the surface electrode 110 is formed on the surface of the P-type fourth semiconductor layer 107 opposite to the substrate (the side away from the substrate). . The surface electrode 110 is formed on the surface of the ohmic contact layer 109 opposite to the substrate. The back electrode 111 is formed on the back surface of the substrate 101. In this case, the front electrode 110 is used as an anode electrode, and the back electrode 111 is used as a cathode electrode. A gate electrode 112 is provided on the surface of the third semiconductor layer 104 on the opposite side of the substrate of the second region 106.

  In this embodiment, the case where the substrate 101 is formed using an N-type semiconductor is illustrated. On the contrary, a P-type semiconductor substrate is used as the substrate 101, the first semiconductor layer 102 is P-type, the second semiconductor layer 103 is N-type, the third semiconductor layer 104 is P-type, and the fourth semiconductor is used as the semiconductor layer. It is also possible to form a PNPN thyristor structure with an N-type layer. In this case, an N-type semiconductor is used for the ohmic contact layer, and the back electrode 111 serves as an anode electrode and the front electrode 110 serves as a cathode electrode. However, it is preferable to form the substrate from an N-type semiconductor. This is because when the light emitting thyristors are integrated, the back electrode (cathode electrode) 111 on the back surface of the substrate can be connected to a common ground, and a positive power source can be connected to the front electrode (anode electrode) 110. Note that the effect of the present embodiment is not changed regardless of the order of conductivity types. In the case where the substrate is a P-type semiconductor substrate, the following explanation is valid as long as holes and electrons are exchanged.

  Further, an insulating substrate, a semi-insulating substrate, or the like can be used for the substrate 101. In this case, the second semiconductor layer 103, the third semiconductor layer 104, the fourth semiconductor layer 107, and the ohmic contact layer 109 are partially etched to expose the surface of the first semiconductor layer 102 (the side away from the substrate). Then, a cathode electrode corresponding to the back electrode 111 is formed on the exposed surface of the first semiconductor layer 102.

  Each of the semiconductor layers 102, 103, 104, and 107 and the ohmic contact layer 109 are formed by an epitaxial growth method such as a metal organic vapor phase epitaxy (MOVPE) or a molecular beam epitaxy (MBE). The reason why the epitaxial growth is necessary is that it cannot function as a phototransistor as a light emitting element and a light receiving element if it contains a large amount of lattice defects. Therefore, materials for the substrate 101, the semiconductor layers 102, 103, 104, and 107 and the ohmic contact layer 109 are selected from the viewpoint of lattice matching.

As the material of the substrate 101, thin films of III / V semiconductors and II / VI semiconductors can be epitaxially grown. For example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), silicon (Si ) And germanium (Ge). When an insulating substrate or a semi-insulating substrate is used as the substrate 101, for example, GaAs, gallium nitride (GaN), sapphire, or the like is used. Note that in order to improve the crystallinity of each of the semiconductor layers 102, 103, 104, and 107, a buffer layer having the same conductivity type as that of the first semiconductor layer 102 may be provided between the substrate 101 and the first semiconductor layer 102. is there.

  As the material of each semiconductor layer 102, 103, 104, 107, gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), aluminum gallium indium phosphide (AlGaInP), or the like is used. Note that the emission wavelength when a light-emitting thyristor is manufactured using these materials is 600 to 800 nm.

The ohmic contact layer 109 is made of a material that does not contain aluminum, such as GaAs or InGaP. This is because when aluminum is included, the surface is easily oxidized in the atmosphere, and it is difficult to make a good ohmic contact with the surface electrode 110. In addition, it is necessary for the ohmic contact layer 109 to have an impurity concentration of 1 × 10 ¹⁹ (cm ⁻³ ) or more in order to achieve good ohmic contact. The thickness of the ohmic contact layer 109 is preferably as thin as 0.01 to 0.02 μm. This is because the band gap value of GaAs and InGaP is smaller than that of a material containing aluminum, so that if the film thickness is large, it becomes a reabsorption layer for light generated inside.

  As the material of each of the electrodes 110, 111, and 112, a material suitable for maintaining good ohmic contact with the semiconductor layer or the substrate 101 that is in contact is used. For example, gold (Au), an alloy of gold and germanium (AuGe), an alloy of gold and zinc (AuZn), or the like is used for the surface electrode 110 in order to make good ohmic contact with the ohmic contact layer 109. . For example, Au, AuGe, nickel (Ni), or the like is used for the gate electrode 112 in order to make a good ohmic contact with the second region 106 of the third semiconductor layer 104. The back electrode 111 is made of, for example, Au, AuGe, or Ni from the viewpoint that a good ohmic contact can be obtained with the semiconductor substrate 101 or when the substrate 101 is made of a nonconductive material. Used.

  Next, optimization of the band gap and impurity concentration of each of the semiconductor layers 102, 103, 104, and 107 of the light-emitting thyristor 115, which is a feature of the present embodiment, will be described. The impurity concentration and the band gap in each semiconductor layer are determined so as to be optimal in light of the object of the present invention to improve the light emission intensity to the outside without reducing the light receiving sensitivity.

  As specific dopants, silicon, tellurium, or the like can be used for the N-type semiconductor in this embodiment, and zinc, carbon, magnesium, or the like can be used as the dopant for the P-type semiconductor. Silicon and zinc are used for the actual device fabrication.

The band gap value is controlled by controlling the type and composition of the semiconductor material constituting each of the semiconductor layers 102, 103, 104, and 107. Aluminum gallium arsenide (AlxGa1 _- xAs) can change the band gap according to the Al composition ratio x while maintaining the lattice matching condition. The case of using an aluminum gallium indium phosphide _{((AlyGa 1-y) 0.5} In 0.5 P), by varying the composition ratio y of Al, is possible to change the band gap in a state of lattice matched to GaAs it can.

  Moreover, the impurity concentration of the semiconductor layer being substantially the same means that the difference in impurity concentration is within 20% when the above-described materials are used. In addition, the band gaps being substantially the same means that the band gap difference is within 5% when the above-described materials are used. This is because, even if the design values are the same, when a light-emitting thyristor is actually manufactured, it may differ depending on the controllability of the device and the manufacturing conditions. In particular, for impurity doping, diffusion may occur in the film, and re-evaporation of the dopant may depend on the substrate temperature, and reproducibility is difficult to obtain. Therefore, when the above-described materials are used, if the impurity concentration is within 20% and the band gap is within 5%, there is no substantial difference.

  As shown in FIG. 1, the feature of the present embodiment is that the band gaps of the second semiconductor layer (P type) 103 and the third semiconductor layer (N type) 104 are substantially the same. In other words, the first semiconductor layer (N-type) 102 and the fourth semiconductor layer (P-type) 107 having a wider band gap than the first semiconductor layer are used. As for the impurity concentration in the thermal equilibrium state, the third semiconductor layer (N-type) 104 is placed on the substrate side (side in contact with the second semiconductor layer 103) and the first region 105 on the side opposite to the substrate (side in contact with the fourth semiconductor layer 107). The second region 106 is divided into two layers so that the impurity concentration of the second region 106 is higher than the impurity concentration of the first region 105. Further, the impurity concentration of the second semiconductor layer (P-type) 103 is substantially the same as or higher than the first impurity concentration, and the first semiconductor layer (N-type) 102 is the second semiconductor layer (P-type). The concentration is higher than 103. Further, the impurity concentration of the fourth semiconductor layer (P type) 107 is characterized by being set to be substantially the same as or higher than the impurity concentration of the second region 106 of the third semiconductor layer (N type) 104. .

  Table 1 shows the impurity concentration, band gap, and film thickness values of the semiconductor layers 102, 103, 104 (105, 106), 107 and the ohmic contact layer 109 in the present embodiment. Note that this value is an example of a preferable value, and the same effect as this embodiment can be obtained if the above-described relationship is satisfied with respect to the band gap and impurity concentration of each semiconductor layer.

  The first reason for setting the band gap and the impurity concentration of each of the semiconductor layers 102, 103, 104, and 107 is that the main light emitting layer is placed in the second region 106 in the third semiconductor layer (N-type) 104. This is because both the internal quantum efficiency and the light extraction efficiency can be improved.

  In order to increase the internal quantum efficiency, it is necessary to recombine the injected carriers effectively. Since an N-type semiconductor substrate is used as the substrate 101, holes are injected from the fourth semiconductor layer (P-type) 107 side through the junction J3 in the light-emitting thyristor 101. In this case, in order to effectively recombine the injected holes with the electrons, it is effective to increase the electron density in the second region 106 near the junction J3. Therefore, in the second region 106, settings were made to increase both the electron density in the thermal equilibrium state and the electron density increased by injection.

  In order to increase the electron density by injection from the junction, as shown in FIG. 1, the second semiconductor layer (P type) 103, the first region 105 in the third semiconductor layer (N type) 104, and the third semiconductor layer The band gaps of the respective layers of the second region 106 in the (N-type) 104 are made substantially the same, and the band gap of the fourth semiconductor layer 107 is made larger than those band gaps. Since the band gap of the fourth semiconductor layer (P-type) 107 is larger than the band gap of the second region (N-type) 106, the fourth gap is equal to the difference between the band gaps as compared with the case where the band gaps of both are equal. The lower end of the conduction band in the semiconductor layer (P-type) 107 rises and forms a potential barrier against electrons. Electrons injected from the first semiconductor layer (N-type) 102 through the junction J1 are bounced back by this potential barrier in the junction J3, so that the electron density in the second region (N-type) 106 in the vicinity of the junction J3. The effect which increases is obtained.

  In order to increase the electron density in the thermal equilibrium state, the third semiconductor layer (N-type) 104 is divided into two layers, and the impurity concentration of the first region 105 on the substrate side is set low, while the second region close to the junction J3. The impurity concentration of the two regions 106 was increased. Setting the impurity concentration of the first region 105 to be low is necessary to ensure a breakdown voltage between the gate electrode 112 and the back electrode (cathode electrode) 111. The impurity concentration of the first region 105 is the lowest in all layers.

  In order to confirm by experiments that increasing the carrier density in the thermal equilibrium state of the second region 106 is effective for increasing the emission intensity, several samples with different impurity concentrations in the second region 106 were prepared. The emission intensity was compared.

  FIG. 2 is a graph showing the light emission intensity of a plurality of light-emitting thyristors 115 produced by changing the impurity concentration of the second region 106. The light emission intensity was measured by setting the gate electrode 112 of the light emitting thyristor 115 to a low level and switching the light emitting thyristor 115 to the on state, and then setting the operating voltage to 5V. In FIG. 2, the vertical axis represents the measured emission intensity in arbitrary units, and the horizontal axis represents the impurity concentration in the second region 106. As is apparent from FIG. 2, the emission intensity is increased by about five times by increasing the impurity concentration (carrier density in the thermal equilibrium state) in the second region 106 by one digit. The effect has been demonstrated.

  In order to further increase the internal light emission efficiency, the impurity concentration of the fourth semiconductor layer (P-type) 107 may be set substantially the same as or higher than that of the second region. This is for increasing the density of holes injected into the second region 106 which is the main light emitting layer.

  On the other hand, in terms of light extraction efficiency, the band gap of each semiconductor layer in the light extraction direction may be increased so that emitted light is not reabsorbed. Normally, when the light-emitting thyristor is used as a light-emitting element, the light extraction direction is the ohmic contact layer 109 side (side away from the substrate) in FIG. Therefore, light emitted from the second region 106 passes through the fourth semiconductor layer (P-type) 107 and the ohmic contact layer 109 and is extracted to the outside, but the band of the fourth semiconductor layer (P-type) 107 is extracted. Since the gap is larger than the band gap of the second region 106 which is a main light emitting layer, the fourth semiconductor layer (P-type) 107 does not absorb light. Further, the thickness of the ohmic contact layer 109 is selected from 0.01 μm to 0.02 μm, and is so thin that the absorption of light emission in this layer is negligible.

  Further, in the present embodiment, by selecting the impurity concentration and the band gap of each of the semiconductor layers 102, 103, 104, and 107 as described above, the film thickness of the second region that is the main light emitting layer is 0.5 μm to 1 μm. It can be set relatively thick as 0.0 μm. In the present embodiment, holes injected through the junction J3 from the fourth semiconductor layer (P-type) 107 side mainly recombine with electrons in the second region 106 to emit light. Among the second regions 106, it is considered that the strongest light emission occurs in the vicinity of the junction J3 having the highest injected hole density. The emitted light is transmitted from the junction J3 side to the fourth semiconductor layer (P-type) 107 side. Since it is taken out through, absorption in the second region itself does not matter. Therefore, when the thickness of the main light emitting layer is made sufficient and the volume of the light emitting place is increased, the light emission intensity as a whole can be increased.

  As is clear from the above, setting the impurity concentration and the band gap so that the second region 106 on the opposite side of the substrate in the third semiconductor layer 104 becomes the main light emitting layer is also effective from the viewpoint of internal quantum efficiency. It is the best also from the point of taking out efficiency. Note that increasing the impurity concentration of the second region 106 has a secondary effect of reducing the contact resistance with the gate electrode 112.

  In order to increase the emitter injection efficiency, first, the heterojunction in which the band gap of the first semiconductor layer (N type) 102 corresponding to the emitter is larger than the band gap of the second semiconductor layer (P type) 103 corresponding to the base. I have to. Second, the impurity concentration of the first semiconductor layer (N-type) 102 corresponding to the emitter is set higher than the impurity concentration of the second semiconductor layer (P-type) 103 corresponding to the base. Third, the thickness of the second semiconductor layer (P-type) 103 corresponding to the base is reduced. The thickness of the second semiconductor layer (P-type) 103 is desirably about 0.01 μm to 0.5 μm. The settings of the impurity concentration and the band gap in the first semiconductor layer (N-type) 102 and the second semiconductor layer performed to increase the light receiving sensitivity are compatible with the settings performed in order to improve the light emission efficiency. ing.

Thus, when the transistor type layer structure is formed, the current amplification factor β can be obtained. FIG. 3 is a graph plotting the relationship between the concentration of N-type carriers in the semiconductor layer forming the collector and the emission intensity in a light-emitting thyristor having an NPN layer structure with respect to a plurality of values of the current amplification factor β. In FIG. 3, the horizontal axis represents the carrier concentration value on a logarithmic scale, and the unit is “cm ⁻³ ”. The vertical axis represents the emission intensity on a logarithmic scale, and the unit is “μW”. In FIG. 3, the solid line extending linearly to the right represents the carrier concentration dependence of the emission intensity expected when the influence of the current amplification factor β is eliminated by calculation. A solid line extending from the first branch point 117a to the right in parallel to the horizontal axis represents the carrier concentration dependency on the emission intensity, which is predicted by calculation, when the current amplification factor β = 90. A solid line extending in parallel to the horizontal axis to the right from the second branch point 117b represents the carrier concentration dependence on the emission intensity, which is predicted by calculation when the current amplification factor β = 601. A solid line extending to the right from the third branch point 117c in parallel to the horizontal axis represents the carrier concentration dependence on the emission intensity, which is predicted by calculation, when the current amplification factor β = 2028.

  In FIG. 3, the data plotted with squares represent the measured values of the carrier concentration dependence on the emission intensity when the current amplification factor β = 90, and the data plotted with circles is when the current amplification factor β = 601. Represents the measured value of the carrier concentration dependence on the emission intensity, and the data plotted with triangles represents the measured value of the carrier concentration dependence on the emission intensity when the current amplification factor β = 2028.

The current amplification factor β is also referred to as “grounded emitter DC current amplification factor (h _FE )”, and is expressed as a ratio of a collector current and a base current when a DC voltage is applied to a transistor with a common emitter. The value of the current amplification factor β is expressed as the following equation (1). The base and emitter majority carrier concentrations are “N _hB ” and “N _eE ”, respectively, and the base and emitter minority carrier diffusion coefficients are “D _eB ” and “D _hE ”, respectively. The base and emitter minority carrier diffusion lengths are “L _eB ” and “L _hE ”, respectively, and the base thickness dimension is “W _B ”.

As shown in FIG. 3, the value predicted based on the calculation of Expression (1) for the value of each current amplification factor β and the measured value are in good agreement. As the value of each character number, GaAs is taken as an example, N _hB = N _eE = 10 ¹⁸ (cm ⁻³ ), W _B = 0.01 (μm), D _eB = 0.4136 (cm ² / s), D _Using values of _hE = 0.0491 (cm ² / s), L _hE = 1.402 (μm), L _eB = 3.523 (μm), the value of current amplification factor β = h _FE = 1174.7 Is obtained.

Further, N _eE = 10 ¹⁸ (cm ⁻³ ), N _hB = 10 ¹⁷ (cm ⁻³ ), W _B = 0.2 (μm), D _eB = 10.45 (cm ² / s), D _hE = Using values of 1.946 (cm ² / s), L _hE = 0.9865 (μm), and L _eB = 13.164 (μm), a value of current amplification factor β = h _FE = 2028.3 is obtained. It is done.

  When the value of the current amplification factor β is small, the emission intensity is saturated with respect to the increase in the carrier concentration of the semiconductor layer forming the collector, specifically, the first region 105, and a sufficient emission intensity cannot be obtained. Therefore, the value of the current amplification factor β is preferably 1000 or more. By setting the current amplification factor β to 1000 or more, the influence of the current amplification factor on the emission intensity can be suppressed, and by setting the carrier concentration high, sufficient emission intensity can be obtained.

  As described above, according to the light-emitting thyristor of the embodiment of the present invention, it is possible to provide a light-emitting thyristor with excellent light emission efficiency.

  FIG. 4 shows a sectional view of the light-emitting thyristor 116 according to the second embodiment of the present invention, and the impurity concentration and band gap of each layer. Note that the values of the impurity concentration and the band gap in FIG. 4 show a desirable example, and the effects of the present invention are not limited to these values. The following description will be made on the case where the substrate is a general N-type semiconductor substrate. As described in the first embodiment, the effect is the same even if the conductivity types of the substrate 101, the semiconductor layers 102, 103, 104, 107, 108, and the ohmic contact layer 109 are reversed.

  The difference between the light emitting thyristor 116 of the present embodiment shown in FIG. 4 and the light emitting thyristor 115 of the first embodiment shown in FIG. 1 is that the fourth semiconductor layer (P type) 107 and the ohmic contact layer 109 are different. The fifth semiconductor layer (P type) 108 having the same conductivity type as the fourth semiconductor layer (P type) 107 is laminated therebetween. In FIG. 4, the part of the NPNP structure peculiar to the thyristor includes a first semiconductor layer (N type) 102, a second semiconductor layer (P type) 103, a third semiconductor layer (N type) 104, and a fourth semiconductor layer (P This part is common to the first embodiment. The band gap of the fifth semiconductor layer (P type) 108 is set to be substantially the same as or wider than the band gap of the fourth semiconductor layer (P type) 107, and the impurity concentration of the fifth semiconductor layer (P type) 108 is set. Is set to be substantially the same as or higher than the impurity concentration of the fourth semiconductor layer (P-type) 106. For each of the semiconductor layers 102, 103, 104, 107 and the ohmic contact layer 109 other than the fifth semiconductor layer (P-type) 108, the values of the band gap, impurity concentration, and film thickness of those layers are shown in FIG. It is set similarly to the first embodiment. In the following description, parts other than the fifth semiconductor layer (P-type) 108 shown in FIG. 4 are the same as those in the embodiment shown in FIG. The description is omitted to avoid duplication.

In the present embodiment, the specific value of the band gap of the fifth semiconductor layer (P-type) 108 is substantially the same as that of the fourth semiconductor layer (P-type) 107, and is about 1.75 eV to 1.88 eV. Was used. The value of the impurity concentration of the fifth semiconductor layer (P type) 108 was set to 1 × 10 ^{19 to} 3 × 10 ¹⁹ larger than that of the fourth semiconductor layer (P type). The thickness of the fifth semiconductor layer 108 is set to 0.1 to 0.5 μm. Since the material, formation method, and dopant material of the fifth semiconductor layer (P-type) 108 are the same as those of the other semiconductor layers 102, 103, 104, and 107 described in the first embodiment, description thereof is omitted.

  The feature of this embodiment is that an ohmic contact with the surface electrode (anode electrode) 110 can be easily made by providing the fifth semiconductor layer (P-type). As described in the first embodiment, the ohmic contact layer is usually formed by doping a high-concentration impurity using a material such as GaAs or InGaP that does not contain aluminum. Since GaAs and InGaP have a small band gap, it is necessary to form the ohmic contact layer as extremely thin as 0.01 μm to 0.02 μm so as not to be an absorption layer for emitted light. However, if the ohmic contact layer is thinned, good ohmic contact with the surface electrode (anode electrode) 110 may not be obtained, so that there is a problem between the fourth semiconductor layer (P-type) 107 and the ohmic contact layer 109. A fifth semiconductor layer (P-type) 108 having a relatively large film thickness is provided. The impurity concentration of the fifth semiconductor layer (P-type) 108 is substantially the same as or higher than the impurity concentration of the fourth semiconductor layer (P-type) 107 so that good ohmic contact can be obtained. At the same time, the band gap of the fifth semiconductor layer (P type) 108 is set to be substantially the same as or wider than the band gap of the fourth semiconductor layer (P type) 107, and the band of the third semiconductor layer (N type). By making it larger than the gap, it is prevented from becoming a reabsorption layer of light emitted inside. By doing so, a reliable ohmic contact can be obtained.

  Next, a light-emitting element array chip 1 according to an embodiment of the present invention configured using the light-emitting thyristor of the present invention will be described.

  FIG. 5 is a plan view showing a basic configuration of the light emitting element array chip 1. FIG. 6 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line VI-VI in FIG. FIG. 7 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as seen from the section line VII-VII in FIG. FIG. 5 shows a plane of the light emitting element array chip 1 arranged with the light emitting direction of each light emitting thyristor T as the front side perpendicular to the paper surface. The gate horizontal wirings GH1 to GH4, the power supply line 11, the select signal transmission path 14, the power supply bonding pad Vs, the select signal input terminal CS, the light emitting thyristor T, the switch thyristor S, the pull-up resistor RP, and the CS resistor RCS are shown by hatching for easy illustration. . Of the light emitting device 10, the light emitting thyristor 116 shown in the second embodiment is used as the light emitting thyristor used in the light emitting thyristor T and the switch thyristor S. The light emitting thyristor shown in the first embodiment is used. Even if 115 is used, the same light emitting device 10 can be configured.

  The plurality of light emitting thyristors T included in the light emitting element array chip 1 are arranged with an interval W1 therebetween. The light emitting thyristor T is a light emitting element for exposure. In the present embodiment, the light emitting thyristors T are arranged at equal intervals and in a straight line. Hereinafter, the arrangement direction X of the light emitting thyristors T may be simply referred to as the arrangement direction X. A direction along the light emission direction of each light emitting thyristor T is defined as a thickness direction Z, and a direction perpendicular to the arrangement direction X and the thickness direction Z is defined as a width direction Y. The light emitting thyristor T is formed so as to emit light having a wavelength of 600 nm to 800 nm.

  Since the light emitting thyristor T is formed by a light emitting thyristor having a PNPN structure, the light emitting thyristor T can be realized with a simple configuration in which P-type semiconductors and N-type semiconductors are alternately stacked, and the device can be easily manufactured. As described above, the light emitting thyristor T applies the control signal to the gate electrodes b1 to bk, so that the light emitting signal is applied to the anodes a1 to ak in a state where the threshold voltage is lower than the voltage of the light emitting signal. Emits light when

The light emitting thyristors T1 to Tk are divided into light emitting element blocks B1 to Bm, and the anodes a of the light emitting thyristors T belonging to the same light emitting element block B are connected to a bonding pad as a common light emitting signal input terminal A. A bonding pad as the light emission signal input terminal A may be simply referred to as a light emission signal bonding pad A. The light emitting signal bonding pad A in the present embodiment corresponds to the third bonding pad. Further, in the present embodiment, four light emitting thyristors T equal to the number of the gate horizontal wirings GH constitute one light emitting element block B. For example, from one to the other along the arrangement direction of the light emitting thyristors T, the light emitting thyristors T are numbered from No. 1 to k, and from the one along the arrangement direction to the other, If the number to the light emitting element block B subjected from No. 1 to No. m-th, the _{i 6 (1 ≦ i 6 ≦} m) th light emitting elements from the _4i 6 -3 th belonging to the block Bi ₆ first 4i ₆ th A connection portion 60 is provided between the anodes a of all the light emitting thyristors T4i ₆ -3 to T4i ₆ and the light emitting signal bonding pads Ai ₆ to be electrically connected. The anode a of the light emitting thyristor T, the light emitting signal bonding pad A, and the connection portion 60 are integrally formed at the same time. Further, in the present embodiment, as a preferred configuration, the light emitting signal bonding pad A is disposed along the arrangement direction X of the light emitting thyristor T on the opposite side of the light emitting thyristor T with the gate horizontal wiring GH interposed therebetween.

  The interval W1 between the light emitting thyristors T in the arrangement direction X and the length W2 in the arrangement direction X of the light emitting thyristors T depend on the resolution of an image to be formed in an image forming apparatus 87 described later on which the light emitting element array chip 1 is mounted. For example, when the resolution of the image is 600 dot per inch (dpi), the interval W1 is selected to be about 24 μm (micrometer), and the length W2 is selected to be about 18 μm.

  Each gate horizontal wiring GH extends in the arrangement direction X along the light emitting element array chip 1 from one end to the other end in the arrangement direction X of the light emitting element array chip 1. Each gate horizontal wiring GH is arranged at intervals in the width direction Y. In the present embodiment, the gate horizontal wiring GH4, the gate horizontal wiring GH3, the gate horizontal wiring GH2, and the gate horizontal wiring GH1 are arranged in order from the side close to the light emitting thyristor T. Further, in the present embodiment, the select signal transmission path 14 for supplying the select signal to the gate electrode d of the switch thyristor S is arranged in parallel with the gate lateral wiring GH1 on the side away from the light emitting thyristor T. . The select signal transmission path 14 is connected to a bonding pad as the select signal input terminal CS via the connection portion 75. A bonding pad as the select signal input terminal CS may be simply referred to as a select signal input terminal CS. The select signal bonding pad CS in the present embodiment corresponds to the first bonding pad. Further, the distance W3 between the gate horizontal lines GH and between the gate horizontal line GH1 and the select signal transmission path 14 is between the gate horizontal lines GH adjacent to each other and between the gate horizontal line GH1 and the select signal transmission path 14. The distance is selected so as not to cause a short circuit, for example, 5 μm.

In the present embodiment, the gate electrodes b1 to bk of the light emitting thyristor T are configured by a third semiconductor layer 24 described later, and are connected to any one of the gate lateral wirings GH1 to GH4. Is formed. Here, from one to the other along the arrangement direction of the light emitting thyristors T, the light emitting thyristors T are numbered from the first to the kth, and the light emitting elements from the one to the other in the arrangement direction. If the block B is numbered from the 1st to the m-th, the 4i ₆ −3rd belonging to the i ₆ (1 ≦ i ₆ ≦ m) th light emitting element block Bi ₆ along the arrangement direction. the 4i the _sixth light emitting thyristor T, the connecting portion 61 is formed between the first _4i 6 -3 -th light emitting thyristor _T4i 6 -3 horizontal gate lines GH1 and the gate electrode of the first from A connection 62 is formed between the gate electrode of the 4i ₆ -2nd light emitting thyristor T4i ₆ -2 and the second gate horizontal wiring GH2, and the 4i ₆ -1th light emitting thyristor T4i _6- 1 gate Connecting portion 63 is formed between the electrode and the third horizontal gate line GH3, connecting portion 64 between the first 4i ₆ th horizontal gate line and the gate electrode of the fourth light emitting thyristor T4i ₆ GH4 Is formed. Further, between the anodes a of all the light emitting thyristors T belonging to the i ₆ (1 ≦ i ₆ ≦ m) light emitting element block Bi ₆ and the i _6th light emitting signal input terminal Ai ₆ along the arrangement direction. The connection portion 60 is formed in the above. As described above, the light emitting thyristors T belonging to the same light emitting element block B are connected to the different gate horizontal wirings GH, so that the light emitting thyristors T can be dynamically driven as described above.

  The switch thyristor S is preferably arranged in a space formed between the light emitting signal bonding pads A. Since one light-emitting element block B composed of a plurality of light-emitting thyristors T is provided with one bonding pad for supplying a light-emitting signal, a space is generated between the light-emitting signal bonding pads A, and the space It is possible to arrange switch elements and the like by effectively utilizing the above. A bonding pad as a gate signal input terminal G for supplying a gate signal to the anode c of each switch thyristor S is also arranged utilizing the space generated between the bonding pads. A bonding pad as the gate signal input terminal G may be simply referred to as a gate signal bonding pad G. In the present embodiment, the gate signal bonding pad G corresponds to the second bonding pad. The anode c and the gate signal bonding pad G are integrally formed. With this arrangement, even if a switch thyristor S is provided, it is possible to avoid an increase in the size of the entire light emitting element array chip, and a small light emitting element array chip can be configured. . The number n of switch thyristors S is equal to the number of gate horizontal wirings GH, and n = 4 in the present embodiment. The CS resistor RCS is also disposed in the vicinity of the switch thyristor S by using a space generated between the bonding pads as the light emission signal input terminal A.

  The gate electrode d of the switch thyristor S in the present embodiment is constituted by a second region 24b of the third semiconductor layer 24 described later. A connection portion 65 is formed between the gate electrode d of the switch thyristor S and the CS resistor RCS, and a connection portion 66 is also formed between the gate electrode d and the corresponding gate lateral wiring GH. Connected. The connecting portion 65 that connects the gate electrode d and the CS resistor RCS and the connecting portion 66 that connects the gate electrode d and the gate lateral wiring GH are integrally formed. The CS resistor RCS is configured using a sheet resistance of a semiconductor film, and a connection portion 67 is formed between the CS resistor RCS and the select signal transmission path 14.

  In the present embodiment, the pull-up resistor RP is formed integrally with the switch thyristor S by using a part of the semiconductor layer constituting the switch thyristor S. The pull-up resistor RP uses the sheet resistance of the semiconductor film. A connection portion 68 is formed between a part of the pull-up resistor RP and the power supply line 11, and the power supply voltage Vcc is applied to the connection portion 68 side of the pull-up resistor.

  The power supply line 11 is wired in parallel with the gate horizontal wiring GH, and in this embodiment, is disposed on the side away from the gate horizontal wiring GH with the light emitting signal bonding pad A interposed therebetween. The power supply line 11 is electrically connected to the bonding pad to which the power supply voltage Vcc is applied by the connecting portion 69. A bonding pad to which the power supply voltage Vcc is applied may be simply referred to as a power supply bonding pad Vs.

  The anode a of the light emitting thyristor T, the anode c of the switch thyristor S, the gate horizontal wiring GH, the select signal transmission line 14, the power supply line 11, the connection portions 60 to 69, the light emitting signal bonding pad A, and the gate signal bonding pad G. The select signal bonding pad CS and the power supply bonding pad Vs are formed of a conductive material such as a metal material and an alloy material. Specifically, it is formed of gold (Au), an alloy of gold and germanium (AuGe), an alloy of gold and zinc (AuZn), nickel (Ni), aluminum (Al), or the like.

  Further, in the light emitting element array chip 1 shown in FIG. 5, as a preferable configuration, a light shielding film 12 is provided as a light shielding means on the surface of the switch thyristor S (the side opposite to the substrate). The switching thyristor S emits light at the time of switching in the same manner as the light emitting thyristor T. However, the light emission is not necessary, and light emitted from the light enters the light emitting thyristor T to change the threshold value of the light emitting thyristor T. In order to avoid this, the light shielding film 12 is used. As the light shielding film 12, the surface may be covered with a member made of a material opaque to the light emission. When an appropriate interlayer insulating film is provided, a gold (Au) thin film used for the gate lateral wiring GH is preferably used. It is also effective to dispose the switch thyristor S and the light-emitting thyristor T as far as possible. As shown in the plan view of FIG. 5, the light-emitting thyristor T and the other light-emitting thyristor T are arranged on one side across the gate horizontal wiring GH. A switch thyristor S may be arranged on the side.

  Although the above-described current limiting resistor RI may be added as a more preferable configuration, it is not used in the plan view of the light emitting element array chip 1 shown in FIG.

  Hereinafter, the configuration of the light-emitting element array chip 1 will be described in more detail with reference to FIGS. In the present embodiment, an N-type semiconductor substrate is used as the substrate 21. The light emitting thyristor T is composed of a light emitting thyristor 116, and a first semiconductor layer (N-type) 22, a second semiconductor layer (P-type) 23, and a third semiconductor layer (N-type) 24 on the surface of the substrate 31 in the Z direction. The first region 24a, the second region 24b, the fourth semiconductor layer (P type) 25, the fifth semiconductor layer (P type) 26, and the ohmic contact layer 27 are stacked in this order. The material, band gap, impurity concentration, and film thickness of each semiconductor layer 22, 23, 24a, 24b, 25, 26, 27 are the same as those of the light emitting thyristor 116 illustrated in the second embodiment. 4 and FIG. 6, reference numerals are different, but corresponding configurations are described with the same names. For example, the substrate 21 of FIG. 6 corresponds to the substrate 101 of FIG. 4 described above, and the first to fifth semiconductor layers 22, 23, 24, 25, and 26 of FIG. This corresponds to the fifth semiconductor layers 102, 103, 104, 107, and 108, respectively.

  In this embodiment, the switch thyristor S is formed at the same time as the light emitting thyristor T, and therefore the configuration of each layer is the same. Specifically, the switch thyristor S has a first semiconductor layer (N-type) 32 and a second semiconductor layer (P-type) on the same surface of the surface of the substrate 21 as the surface on which the light-emitting thyristor T is formed. ) 33, the first region 34a, the second region 34b, the fourth semiconductor layer (P-type) 35 and the fifth semiconductor layer (P-type) 36, and the ohmic contact layer 37 in the third semiconductor layer (N-type) 34. It is formed by laminating in this order. In the following description, the description of the light emitting thyristor T is the same for the switch thyristor S.

  In the present embodiment, a semiconductor substrate having the same conductivity type as that of the first semiconductor layer 22 is used for the substrate 21. On the surface opposite to the surface on which the semiconductor layers 22 to 26 are stacked in the thickness direction Z of the substrate 21, the back electrode 20 is formed over the entire surface. The back electrode 20 is formed of a conductive material such as a metal material and a composite material. Specifically, the back electrode 20 is formed of gold (Au), an alloy of gold and germanium (AuGe), an alloy of gold and zinc (AuZn), or the like. The back electrode 20 is used as a common electrode for each light emitting thyristor T.

  In the present embodiment, the conductivity type of the first semiconductor layer 22 and the third semiconductor layer 24 is N-type, and the conductivity type of the second semiconductor layer 23 and the fourth semiconductor layer 25 is P-type. Therefore, the cathodes of the light emitting thyristor T and the switch thyristor S are connected to the back electrode 20 as a common electrode, and an N gate electrode is used as the gate electrode. It is preferable that the back electrode 20 is grounded and the cathode potential is zero (0) volts (V) because a positive power source can be used as a power source for applying voltage or current to the anode a of each light emitting thyristor T.

  The insulating layer 28 is formed along the surfaces of the light-emitting thyristor T and the switch thyristor S, and is also formed between the light-emitting thyristor T and the switch thyristor S. The thyristors S are electrically insulated from each other by the insulating layer 28. The insulating layer 28 is formed of a resin material having electrical insulation, translucency, and flatness. For example, a resin material that transmits 95% or more of light having a wavelength emitted by the light emitting thyristor T, such as polyimide and benzocyclobutene (BCB), is used.

  A through hole 29 is formed in a part of the insulating layer 28 that covers the surface of the ohmic contact layer 27 (side away from the substrate). A part of the anode a is formed in the through hole 29 and is in contact with the ohmic contact layer 27. The through hole 29 is formed so that the center of the light emitting thyristor T in the arrangement direction X and the center of the light emitting thyristor T in the width direction Y are exposed from the insulating layer 28, and the current from the anode a is The light emitting thyristor T can emit light by being efficiently supplied to the central portion of the light emitting thyristor T. In the light emitting thyristor T, light is generated mainly in the third semiconductor layer 24.

  The length W3 in the arrangement direction X of the anodes a of the light emitting thyristors T is formed to be 1/3 or less of the length W2 in the arrangement direction X of the light emitting thyristors T. The anode a covers a part of the light emitting thyristor T in the light emission direction, but the light emitted from the light emitting thyristor T is prevented from being blocked as much as possible by selecting the length W3 as described above.

  The first semiconductor layer 22, the second semiconductor layer 23, the third semiconductor layer 24, the fourth semiconductor layer 25, the fourth semiconductor layer 26, and the ohmic contact layer 27 are formed by molecular beam epitaxial growth and chemical vapor deposition on one surface of the substrate 21. The layers can be sequentially stacked by using an epitaxial growth method such as a (CVD) method. Thereafter, the light emitting thyristors T and the switch thyristors S are formed by patterning and etching using photolithography. Therefore, since the light emitting thyristor T and the switch thyristor S are formed simultaneously in a series of manufacturing processes, the semiconductor layers constituting the switch thyristor S and the light emitting thyristor T have the same layer configuration. As a result, both the switch thyristor S and the light emitting thyristor T have both the light emitting function and the switch function, but the switch thyristor S uses only the switch function. In this way, the same structure and stable characteristics can be easily manufactured at a time, and the manufacturing cost can be reduced.

  The insulating layer 28 is formed by forming each semiconductor layer, spin-coating the above-described resin material such as polyimide, and then curing, and further forming each through hole 29 necessary for connection between the electrode and the light emitting thyristor T. In order to achieve this, patterning and etching by photolithography are performed.

  As shown in FIG. 7, the shape of the light emitting thyristor T in the width direction Y is the gate lateral wiring GH of the first semiconductor layer 22, the second semiconductor layer 23, and the third semiconductor layer 24 of the light emitting thyristor T. The end near the gate protrudes toward the gate horizontal wiring GH from the end near the gate horizontal wiring GH of the fourth semiconductor layer 25, the fifth semiconductor layer 26, and the ohmic contact layer 27, and the gate horizontal wiring GH The connected part 201 is configured. The length of the connected portion 201 in the arrangement direction X is equal to the length W2 described above. In the second region 24b of the third semiconductor layer 24, the portion constituting the connected portion 201 is smaller in thickness than the portion where the fourth semiconductor layer 25 is laminated. This is because, when the connected portion 201 is formed by exposing the surface of the second region 24b of the third semiconductor layer 24 by the etching process, the fourth semiconductor layer 25 is over-etched so as not to remain. .

  Similarly for the shape of the switch thyristor S in the width direction Y, the end portions of the switch thyristor S near the gate lateral wiring GH of the first semiconductor layer 32, the second semiconductor layer 33, and the third semiconductor layer 34 are as follows. The fourth semiconductor layer 35, the fifth semiconductor layer 36, and the ohmic contact layer 37 protrude toward the gate horizontal wiring GH from the end portions near the gate horizontal wiring GH and are connected to the gate horizontal wiring GH. 202 is configured. Further, in order to perform over-etching, the thickness of the portion constituting the connected portion 202 in the second region 34b of the third semiconductor layer 34 is formed smaller than the thickness of the portion where the fourth semiconductor layer 35 is laminated. Is done.

  The insulating layer 28 is formed along the surfaces of the light-emitting thyristor T and the switch thyristor S, and is also formed between the light-emitting thyristor T and the switch thyristor S, and the light-emitting thyristor T and the switch thyristor S. Are electrically insulated by the insulating layer 28. On the surface of the insulating layer 28 formed between the light emitting thyristor T and the switch thyristor S, the gate horizontal wiring GH and the select signal transmission path 14 are formed, and further, the insulating layer 203 is formed along these surfaces. Is done. Further, the power supply line 11 is formed on the surface of the insulating layer 28 on the side separated from the gate lateral wiring with the switch thyristor S interposed therebetween, and the insulating layer 203 is further formed along the surface.

  In the formed insulating layers 28 and 203, through holes 204 and 205 are formed in portions of the light emitting thyristor T that are stacked on the connected portion 201 and the surface of the gate horizontal wiring GH (on the opposite side of the substrate). . The connection portion 61 that electrically connects the second region 24b (corresponding to the gate electrode b) of the third semiconductor layer 24 of the light emitting thyristor T and the gate lateral wiring GH includes the through holes 204 and 205 and The insulating layers 28 and 203 sandwiched between the through holes 204 and 205 are stacked and provided. Further, through holes 205 and 206 are also formed in portions of the insulating layers 28 and 203 that are stacked on the connected portion 202 of the switch thyristor S and the surface of the gate lateral wiring GH (on the opposite side of the substrate). The connection portion 66 that electrically connects the second region 34b (corresponding to the gate electrode d) of the third semiconductor layer 34 of the switch thyristor S and the gate lateral wiring GH includes the through-holes 205 and 206 and the through-holes. The insulating layers 28 and 203 sandwiched between the holes 205 and 206 are stacked. As shown in FIG. 7, when the through-hole 205 provided in the insulating layer 203 of the part laminated | stacked on the gate horizontal wiring GH is common, the said connection parts 61 and 66 are formed integrally.

  Further, as described above, the through hole 29 is formed in a part of the insulating layer 28 laminated on the light emitting thyristor T on the surface of the ohmic contact layer 27 (on the opposite side of the substrate). A part of the anode a is formed in the through hole 29 and is in contact with the ohmic contact layer 27. The anode a is integrally formed with the connection portion 60 with the light emission signal input terminal A. The connection portion 60 covers a part of the fourth semiconductor layer 25, the fifth semiconductor layer 26, and the ohmic contact layer 27 of the light emitting thyristor T near the gate lateral wiring GH, and the second region 24 b of the third semiconductor layer 24. A part of the surface (on the opposite side of the substrate) of the insulating layer 28 laminated on the connected portion 201 provided on the substrate is also laminated. Similarly, a through-hole 207 is formed in a part of the insulating layer 28 laminated on the switch thyristor S on the surface of the ohmic contact layer 37 (on the opposite side of the substrate). A part of the anode c is formed in the through hole 207 and is in contact with the ohmic contact layer 37.

  The switch thyristor S is covered with a light shielding film 12. One end of the light shielding film 12 in the width direction Y covers the end of the fourth semiconductor layer 35, the fifth semiconductor layer 36, and the ohmic contact layer 37 of the switching thyristor S on the side opposite to the light emitting thyristor T to shield the light. The other end in the width direction Y of the film 12 covers the connected portion 202 of the second region 34b of the third semiconductor layer 34 of the switch thyristor S, and is near the center between the select signal transmission line 14 and the switch thyristor S. Extend to.

  FIG. 8 is a partial cross-sectional view showing the basic configuration of the light-emitting element array chip 1 as viewed from the section line VIII-VIII in FIG.

  As the CS resistor RCS and the pull-up resistor RP, a semiconductor layer composed of any one of the semiconductor layers 22 to 26 and 32 to 36 constituting the light emitting thyristor T and the switch thyristor S may be used as a thin film resistor. In the present embodiment, the pull-up resistor RP uses a semiconductor thin film composed of the first semiconductor layer 52, the second semiconductor layer 53, and the third semiconductor layer 54, and the CS resistor RCS is the first semiconductor layer. The layer 42, the second semiconductor layer 43, and the third semiconductor layer 44 are used. In this embodiment, the CS resistor RCS and the pull-up resistor RP are used when the semiconductor layers 22 to 26 and 32 to 36 and the ohmic contact layers 27 and 37 constituting the light emitting thyristor T and the switch thyristor S are formed. Since they are formed at the same time, no new manufacturing process is required.

  The surface of one end portion in the width direction Y of the third semiconductor layer 44 constituting the CS resistor RCS is connected to one end of a connection portion 65 that connects the gate electrode d of the switch thyristor S and the CS resistor RCS. This corresponds to one end of the resistor RCS. The other end portion in the width direction Y of the third semiconductor layer 44 constituting the CS resistor RCS is connected to one end of a connection portion 67 that connects the select signal transmission path 14 and the CS resistor RCS. It corresponds to the end.

  First semiconductor layer 42, second semiconductor layer 43, and third semiconductor layer 44 that form CS resistor RCS, and first semiconductor layer 52, second semiconductor layer 53, and third semiconductor layer that form pull-up resistor RP An etching process for determining the overall thickness of the connection portion 54 is performed simultaneously with the formation of the connected portions 201 and 202. Therefore, the thickness of the CS resistor RCS and the pull-up resistor RP is equal to the thickness of the connected parts 201 and 202.

  In FIG. 8, the insulating layer 28 is formed along the surfaces of the CS resistor RCS and the pull-up resistor RP, and is also formed between the CS resistor RCS and the pull-up resistor RP. The insulating layer 28 is electrically insulated from the RP. As described above, the gate horizontal wiring GH, the select signal transmission line 14, and the power supply line 11 are formed on the surface of the insulating layer 28, and the insulating layer 203 is formed along these surfaces.

  Of the formed insulating layers 28 and 103, the portion laminated on the surface (the substrate opposite side) of the other end portion in the width direction Y of the third semiconductor layer 44 constituting the select signal transmission path 14 and the CS resistor RCS The through holes 109 and 110 are formed, and a connection portion 67 for electrically connecting them is provided. A through-hole 111 is also formed in a portion of the insulating layer 28 that is stacked on the surface of one end portion in the width direction Y of the third semiconductor layer 44 that constitutes the CS resistor RCS (on the opposite side of the substrate). A connection portion 65 to the S gate electrode d is provided. Further, in the formed insulating layers 28 and 103, through-holes 112 and 113 are also formed in a portion laminated on the pull-up resistor RP and the power supply line 11, and a connection portion 68 for electrically connecting them is formed. The

  FIG. 9 is a block circuit diagram schematically showing the light emitting device 10 according to the embodiment of the present invention. The light emitting device 10 emits light as a plurality of light emitting element array chips L1, L2,..., Lp-1, Lp (the symbol p is a positive integer of 2 or more) and a drive circuit for the light emitting element array chips L1 to Lp. A light emission signal drive IC (Integrated Circuit) 130 that supplies a signal, a gate signal drive IC 131 that supplies a gate signal, and a select signal drive IC 132 that supplies a select signal are included. Each drive IC outputs image information based on a control means 96 described later. Each of the light emitting element array chips L1 to Lp is simply referred to as the light emitting element array chip L when collectively referring to each of the light emitting element array chips L1 to Lp. Further, the light emitting element array chip L may be simply referred to as an array chip L. In the present embodiment, the light-emitting element array chip 1 shown in FIG. The select signal drive IC 132 corresponds to the first drive circuit, the gate signal drive IC 131 corresponds to the second drive circuit, and the light emission signal drive IC 130 corresponds to the third drive circuit.

  In each array chip L, the light emitting elements T are arranged in a line along the arrangement direction X, and the light emitting directions from the respective light emitting elements T are aligned and mounted on the circuit board. However, the circuit board is not shown in FIG. The light emission signal driving IC 130, the gate signal driving IC 131, and the select signal driving IC 132 are mounted on the circuit board. Further, pattern wiring for connecting the output terminals of the driving ICs 130 to 132 and the bonding pads of the array chips L is formed on the circuit board, and the pattern wiring and the bonding pads are connected by bonding wires.

As described above, the light emitting element array chip 1 includes m light emitting signal bonding pads A, one select signal bonding pad CS, and four gate signal bonding pads G. Further, a power supply bonding pad Vs for connecting a positive power supply applied to the other end of the pull-up resistor RP (the side opposite to the connection of the gate electrode d of the switch thyristor S) is required. Is shown in FIG. In the case of the present embodiment in which p array chips shown in FIG. 9 are mounted, from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L, When each array chip is numbered from No. 1 to No. p, the select signal bonding pad CS of the i ₁₀ (1 ≦ i ₁₀ ≦ p) th array chip L is described as a select signal bonding pad CSi _10. To do. When referring to the select signal bonding pads CS1 to CSp of the unspecified array chip L, the select signal bonding pads CS may be simply described.

The light emission signal drive IC 130 has the same number (m) of light emission signal output terminals λ1 to λm as the light emission signal bonding pads A1 to Am of each array chip L. The light emission signal output terminals λ1 to λm may be simply referred to as the light emission signal output terminal λ when collectively referring to a plurality of light emission signal outputs terminals λ1 to λm. Each light emitting signal bonding pad A and the light emitting signal output terminal λ are connected by sharing wiring between different array chips. In the case of this embodiment in which p array chips are mounted, light emitting signal bonding pads A1 to Am from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L. Are numbered from 1 to m, and the light emission signal output terminals λ1 to λm are also numbered from 1 to m, respectively, i ₈ (1) of each of the p array chips. ≦ i ₈ ≦ m) The light emitting signal bonding pads Ai ₈ are electrically connected to each other and further electrically connected to the i _8th light emitting signal output terminal λi ₈ .

The gate signal driving IC 131 has the same number (four) of gate signal output terminals μ1 to μ4 as the gate signal bonding pads G1 to G4 of each array chip L. The gate signal output terminals μ1 to μ4 may be simply referred to as the gate signal output terminal μ when collectively referring to a plurality of gate signal output terminals μ1 to μ4 or when referring to an unspecified one. Each gate signal bonding pad G and the gate signal output terminal μ are connected by sharing wiring between different array chips. In the case of the present embodiment in which p array chips are mounted, the gate signal bonding pads G1 to G4 are directed from one to the other along the arrangement direction X of the light emitting elements T constituting each array chip L. Are numbered from No. 1 to No. 4 and gate signal output terminals μ1 to μ4 are also numbered from No. 1 to No. 4, respectively, and the i ₉ (1 ≦ 1) of each of the p array chips. i ₉ ≦ 4) The gate signal bonding pads Gi ₉ are electrically connected to each other, and further electrically connected to the i _9th gate signal output terminal μi ₉ .

The select signal driving IC 132 has the same number (p) of select signal output terminals ν1 to νp as the array chip L. The select signal output terminals ν1 to νp may be simply referred to as a select signal output terminal ν when collectively referring to a plurality of select signal output terminals ν1 to νp. Each select signal bonding pad CSi ₁₀ and the select signal output terminal ν are individually connected to each array chip. In the case of this embodiment in which p array chips are mounted, each array chip starts from the first along the array direction X of the light emitting elements T constituting each array chip L. When numbers are assigned to the p-th and the select signal output terminals ν1 to νp are also numbered from the first to the p-th, the select of the i ₁₀ (1 ≦ i ₁₀ ≦ p) -th array chip L The signal bonding pad CSi ₁₀ and the i-th _10th select signal output terminal νi ₁₀ are electrically connected.

As described above, since the select signal bonding pad CS of each array chip L and the select signal output terminal ν are individually connected, the select signal driving IC 132 is sequentially connected to the select signal bonding pad CS of each array chip L. The select signal can be output to the array chip L in order. On the other hand, since the wiring of each array chip L and the gate signal driving IC 131 is shared, for example, the gate signal output from the i ₉ (1 ≦ i ₉ ≦ 4) th gate signal output terminal μi ₉ is Input to the i ₉ (1 ≦ i ₉ ≦ 4) th gate signal bonding pad Gi ₉ of all the array chips L, and the anodes ci ₉ of the i _9th switch thyristors Si ₉ of all the array chips L Is input. However, for switching among the i ₉ th switch thyristor Si ₉ of each array chip L is only array chip L in the selected state by the selection signal is input. Further, among the light emitting thyristors T connected to the i _9th gate horizontal wiring GHi ₉ of the array chip L in the selected state, the light emission belonging to the light emitting element block B to which the light emission signal is input from the light emission signal driving IC 130. The thyristor T for use emits light.

  As described above, by switching the array chips L in the selected state in order, it is possible to stably operate time-division driving in which the gate signal driving IC 131 and the light emitting signal driving IC 130 are shared among the plurality of light emitting element arrays. Accordingly, the number of driving ICs and the number of layers of the board on which the driving ICs are mounted can be reduced, and the area of the light emitting element array and the driving IC mounting board can be reduced. As a result, it is small and stable. A light emitting device that operates in a short time can be realized.

  FIG. 10 is a timing chart showing the operation of the light emitting device 10, where the horizontal axis represents the elapsed time from the reference time, and the vertical axis represents the signal level in terms of voltage or current. In FIG. 10, signals output from the signal output terminals (light emission signal output terminal λ, gate signal output terminal μ, and select signal output terminal ν) of the light emission signal drive IC 130, the gate signal drive IC 131, and the select signal drive IC 132, respectively. Waveforms of (light emission signal, gate signal and select signal) are shown. Furthermore, the waveform of the power supply voltage Vcc applied to the other end of the pull-up resistor RP (the side opposite to the side where the gate electrode d of the switch thyristor S is connected) is also shown. In FIG. 10, reference numerals of bonding pads (signal input terminals) connected to the signal output terminals are used as reference numerals of the output waveform.

  In the present embodiment, the light emission signal driving IC 130 outputs a constant current of 5 mA when the level is high (H) and 0 mA when the level is low (L). The gate signal driving IC 131 outputs a constant current of 1 mA when the level is high (H) and 0 mA when the level is low (L). The select signal driving IC 132 outputs a constant voltage of 5V when the level is high (H) and 0V when the level is low (L). The power supply voltage Vcc applied to the other end of the pull-up resistor (the side opposite to the side where the gate electrode d of the switch thyristor S is connected) is 5V.

  The operation of the light emitting device 10 will be described in the order of time passage with reference to FIG. At time t0, since the select signal is at the high (H) level, no array chip is in the selected state. At time t1, the select signal input to the first array chip L1 is set to a low (L) level, so that the first array chip L1 enters the select state. At time t2, a high (H) level signal is input to the first gate signal input terminal G1 of each array chip L. Then, only in the selected first array chip L1, the first switch thyristor S1 switches to the ON state, and the gate horizontal wiring GH1 connected to the gate electrode d1 of the switch thyristor S1 is switched. The potential is almost low (0 V). Next, at time t3, light emission signals are input to the light emission signal input terminals A1 to Am of each array chip. Then, the light emitting thyristor T connected to the first gate horizontal wiring GH1 in the first array chip L1 in the selected state emits light. Since the light emission signal returns to the low (L) level at time t4, the light is turned off. Next, at time t5, the gate signal input to the first gate signal input terminal G1 returns to the low (L) level, and the gate signal input to the second gate signal input terminal G2 is high (H ) Become a level. Then, only in the selected first array chip L1, the second switch thyristor S2 is switched to be turned on. From time t6 to t7, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Then, the light emitting thyristor T connected to the second gate horizontal wiring GH2 in the first array chip L1 in the selected state emits light. Similarly, from time t8 to t11, since the gate signal input to the third gate signal input terminal G3 is at the high (H) level, the first array chip L1 in the selected state is the first one. The third switch thyristor S3 is switched to be turned on. In this state, at time t9 to t10, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Therefore, among the first array chips L1 in the selected state, the third one is selected. The light emitting thyristor T connected to the gate lateral wiring GH3 emits light. In addition, at time t11 to t14, the gate signal input to the fourth gate signal input terminal G4 is at the high (H) level, so the fourth array chip L1 in the selected state is the fourth one. The switching thyristor S4 switches to the ON state. In this state, at time t12 to t13, the light emission signal is input again to the light emission signal input terminals A1 to Am of each array chip. Therefore, among the first array chips L1 in the selected state, the fourth one. The light emitting thyristor T connected to the gate lateral wiring GH4 emits light. At time t15, the gate of the switching thyristor S of the first array chip L1 transitions to a high (H) level, the selection state of the first array chip L1 is completed, and the second array chip at time t15. The select signal input to the select signal input terminal CS2 of the array chip L2 transitions to the low (L) level, and the selection state of the second array chip L2 starts.

  As described above, by applying the select signals in order from the first array chip and sequentially selecting the array chips, the time-division driving for each array chip L becomes possible. Further, the gate signal is sequentially applied from the first switch thyristor, so that time-division driving in the array chip L is possible.

  FIG. 11 is a graph showing a forward voltage-current characteristic that is a relationship between the anode voltage and the anode current of the light emitting thyristor T. The anode voltage represents the anode potential when the cathode potential is 0 (zero) volts (V), and the anode current represents the current flowing into the anode.

In FIG. 11, the horizontal axis represents the anode voltage, and the vertical axis represents the anode current. FIG. 11 also shows a load line 70. In the thyristor T for light emission, the threshold voltage V _BO is lowered by giving a control signal to the gate electrode b, so that the operating point is off at which the characteristic curve 71 representing the forward voltage-current characteristic and the load line 70 intersect. Light is emitted by transition from the point q2 in the state to the point q1 in the on state where the characteristic curve 71 and the load line 70 intersect. A main current flows between the anode and the cathode at the point q1 in the on state.

  The operation of the light emitting thyristor T will be described specifically using numerical values. Here, when the cathode potential is 0 volt (V), when the light emission signal is at a high (H) level, a potential of 5 V is applied to the anode a, and when the light emission signal is at a low (L) level, 0 V is applied to the anode a. A potential shall be applied. When the control signal is high (H) level, a potential of 5V is applied to the gate electrode b, and when the control signal is low (L) level, a potential of 0V is applied to the gate electrode g.

  First, when the gate signal is at a high (H) level, the potential of the gate electrode b is 5 V. Therefore, in order to flow the anode current, the third semiconductor layer (N-type) and the potential of the gate electrode b are more than 5 V. It is necessary to apply a potential higher to the anode a by the forward drop voltage of the diode formed by the fourth semiconductor layer (P type). The forward drop voltage is about 1.5V when the light emitting thyristor is made of GaAs or AlGaAs. Therefore, even if the light emission signal is set to the high (H) level, the light emitting thyristor T is turned off at the point q2 and does not emit light. Next, when the gate signal is at a low (L) level, the potential of the gate electrode b is 0 V. Therefore, in order to flow the anode current, the third semiconductor layer (N-type) is more than the potential 0 V of the gate electrode g. Further, it is necessary to apply a potential higher to the anode a by the forward drop voltage of the diode formed by the fourth semiconductor layer (P type). Therefore, when the light emission signal is set to the high (H) level, the light emitting thyristor T is turned on at the point q1, and the anode current flows to emit light.

  The configuration and operation of the switch thyristor S can be described in the same manner as in the case of the light emitting thyristor T.

The threshold voltage V _BO is also related to the current amplification factor β described above, and it is preferable that the threshold voltage V _BO is set larger than a certain level. In the present embodiment, the breakdown that occurs when the applied voltage exceeds the threshold voltage V _BO is breakdown due to punch-through. The higher the voltage applied to the collector junction, the wider the base region and the smaller the base width. As a result, the current amplification factor β increases, and the collector current is not controlled by the base current. In this embodiment, the threshold voltage V _BO is designed on the premise of breakdown due to punch-through.

Therefore, the threshold voltage V _BO is such that the carrier charge amount is “q” (Coulomb, “C”), the base carrier concentration is “N _P ”, the base thickness dimension is “W _P ”, and the first region 64a The carrier concentration is “N _N1 ”, the thickness dimension of the first region 64 a is “W _N1 ”, the carrier concentration of the second region is “N _N2 ”, the dielectric constant is “εε ₀ ”, and the diffusion potential is “V _D ”. When,

It can be expressed as. Further, the diffusion potential V _d is expressed by assuming that the Boltzmann constant is “k”, the temperature is “T”, and the intrinsic carrier concentration is “n _i ”.

It can be expressed as. “Ln” represents a natural logarithm with the base “e” as the number of Napiers. This calculation formula assumes that the depletion layer is formed in at least a part of the base, that is, the range including the second semiconductor layer 23, the first region 24a, and the second region 24b, and further, the breakdown is punched. Since it is caused by the through, it is calculated by adding a condition that the thickness dimension of the depletion layer matches the film thickness of the base second semiconductor layer 23.

From equation (2), if the threshold voltage V _BO is set sufficiently large, at least one of the carrier concentration “N _P ” and the film thickness “W _P ” of the second semiconductor layer 23 serving as the base is increased. It turns out that it is necessary to do. Since the film thickness “Wp” of the base layer is the thickness dimension “W _B ”, if this is set large, the value of the current amplification factor β becomes small.

In the present embodiment, the value of the current amplification factor β is made sufficiently large by setting the value of the carrier concentration of the first region 24 a to 5 × 10 ¹⁵ (cm ⁻³ ) or more and 1 × 10 ¹⁶ (cm ⁻³ ). The voltage V _BO can be sufficiently increased without setting the thickness dimension and the carrier concentration of the base layer among the layers forming the transistor-type layers. As described above, the adjustment of the carrier concentration in the first region 24a requires setting the current amplification factor β sufficiently large, keeping the thickness dimension of the base layer and the carrier concentration low, and light emission. It is possible to achieve both a sufficiently large threshold voltage _VBO . Therefore, the influence of the current amplification factor β on the emission intensity can be suppressed.

  Next, an image forming apparatus 87 according to an embodiment of the present invention configured using the light emitting device of the present invention will be described.

  FIG. 12 is a side view showing a basic configuration of an image forming apparatus 87 having the light emitting device 10 shown in FIG. The image forming apparatus 87 is an electrophotographic image forming apparatus, and the light emitting device 10 is used as an exposure device for the photosensitive drum 90. In the present embodiment, a plurality of light emitting devices 10 and driving means 73 are mounted on a circuit board. The plurality of light emitting devices 10 mounted on the circuit board are simply referred to as the light emitting devices 10.

  The image forming apparatus 87 is an apparatus that employs a tandem system that forms four color images of Y (yellow), M (magenta), C (cyan), and K (black), and is roughly divided into four light emitting elements. Devices 10Y, 10M, 10C, 10K, lens arrays 88Y, 88M, 88C, 88k as condensing means, circuit board 31 on which the light emitting device 10 and driving means 73 are mounted, and a first holder 89Y for holding the lens array 88. 89M, 89C, 89K, four photosensitive drums 90Y, 90M, 90C, 90K, four developer supply means 91Y, 91M, 91C, 91K, a transfer belt 92 as transfer means, and four cleaners 93Y, 93M, 93C. , 93K, four chargers 94Y, 94M, 94C, 94K, a fixing means 95 and a control means 96.

  Each light emitting device 10 is driven by the driving means 73 based on the color image information of each color. The length W11 in the X direction of the four light emitting devices 10 is selected from 200 mm to 400 mm, for example.

  Light from the light emitting element L of each light emitting device 10 is condensed and irradiated onto each of the photosensitive drums 90C, 90M, 90Y, and 90K via the lens array 88. The lens array 88 includes, for example, a plurality of lenses respectively disposed on the optical axis of the light emitting element L, and is configured by integrally forming these lenses.

  The circuit board on which the light emitting device 10 is mounted and the lens array 88 are held by the first holder 89. By the holder 89, the light irradiation direction of the light emitting element L and the optical axis direction of the lens of the lens array 88 are aligned so as to be substantially aligned.

  Each of the photoconductive drums 90Y, 90M, 90C, and 90K is formed, for example, by adhering a photoconductive layer on the surface of a cylindrical substrate, and the outer peripheral surface receives light from the light emitting devices 10Y, 10M, 10C, and 10K. Then, an electrostatic latent image forming position where the electrostatic latent image is formed is set.

  The exposed photosensitive drums 90Y, 90M, 90C, and 90K are sequentially exposed at the periphery of the photosensitive drums 90Y, 90M, 90C, and 90K toward the downstream side in the rotational direction with respect to the electrostatic latent image forming positions. Developer supply means 91Y, 91M, 91C, 91K for supplying developer to the transfer belt 92, cleaners 93C, 93M, 93Y, 93K, and chargers 94Y, 94M, 94C, 94K are arranged, respectively. A transfer belt 92 that transfers an image formed on the photosensitive drum 90 with a developer onto a recording sheet is provided in common to the four photosensitive drums 90Y, 90M, 90C, and 90K.

  The photosensitive drums 90Y, 90M, 90C, and 90K are held by a second holder, and the second holder and the first holder 89 are relatively fixed. The photoconductor drums 90Y, 90M, 90C, and 90K are aligned so that the rotation axis directions of the respective photoconductor drums 90Y and the X direction of the respective light emitter chip assemblies 86 substantially coincide with each other.

  The recording sheet is conveyed by the transfer belt 92, and the recording sheet on which an image is formed by the developer is conveyed to the fixing unit 95. The fixing unit 95 fixes the developer transferred to the recording sheet. The photosensitive drums 90Y, 90M, 90C, and 90K are rotated by a rotation driving unit.

  The control unit 96 supplies a clock signal and image information to the driving unit 73 described above, and also rotates and drives the photosensitive drums 90Y, 90M, 90C, and 90K, developer supply units 91Y, 91M, 91C, and 91K, Each part of the transfer means 92, the charging means 94Y, 94M, 94C, 94K and the fixing means 95 is controlled.

  In the image forming apparatus 87 having such a configuration, bias light and leakage light are not generated from the light emitting device 10 used as the exposure apparatus, so that a high quality image can be formed. In addition, since the light emitting device 10 in which the switch element T and the light emitting element L by the light emitting thyristor are integrated is used for the exposure apparatus, such an exposure apparatus can be manufactured at low cost, thereby manufacturing the image forming apparatus 87. Cost can be reduced. Even if the light emitting device 10 of the image forming apparatus 87 of the present embodiment is replaced with the light emitting device 120, the same effect can be achieved.

  In addition, this invention is not limited to the above-mentioned form, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

115, 116 Light-emitting thyristor 10 Light-emitting device 101 Substrate (N-type)
102 First semiconductor layer (N-type)
103 Second semiconductor layer (P type)
104 Third semiconductor layer (N-type)
105 1st area | region 106 2nd area | region 107 4th semiconductor layer (P type)
108 Fifth semiconductor layer (P type)
110 Surface electrode (anode electrode)
111 Back electrode (cathode electrode)
112 Gate electrode

Claims (7)

On the substrate, a first semiconductor layer of one of N-type and P-type conductivity, a second semiconductor layer having a conductivity type opposite to the first semiconductor layer, a third semiconductor layer having the same conductivity type as the first semiconductor layer, And a light emitting thyristor in which a fourth semiconductor layer having a conductivity type opposite to that of the first semiconductor layer is stacked in this order
The band gap of the third semiconductor layer is substantially the same as the band gap of the second semiconductor layer, and is narrower than the band gaps of the first and fourth semiconductor layers,
The third semiconductor layer includes a first region on the substrate side and a second region on the opposite side of the substrate, and the impurity concentration of the first region is lower than the impurity concentration of the second region. And less than 1 × 10 ¹⁶ (cm ⁻³ ),
The impurity concentration of the second semiconductor layer is substantially the same as or higher than the impurity concentration of the first region of the third semiconductor layer, and is lower than the impurity concentration of the first semiconductor layer,
The impurity concentration of the fourth semiconductor layer, Ri substantially equal to or higher concentrations der and impurity concentration of the second region of the third semiconductor layer,
Emitting thyristor value of the current amplification factor, characterized in der Rukoto 1000 or more. 2. The light-emitting thyristor according to claim 1, wherein the impurity concentration of the first region is 5 × 10 ¹⁵ (cm ⁻³ ) or more.   A fifth semiconductor layer having the same conductivity type as the fourth semiconductor layer is stacked on the opposite side of the fourth semiconductor layer from the substrate, and the band gap of the fifth semiconductor layer is equal to the band gap of the fourth semiconductor layer. 3. The light emitting device according to claim 1, wherein the fifth semiconductor layer has substantially the same or wider width, and the impurity concentration of the fifth semiconductor layer is substantially the same as or higher than the impurity concentration of the fourth semiconductor layer. Thyristor. (A) A first control signal is output when a first signal is input to the first electrode, the second electrode, and the first electrode, and a second signal is input to the second electrode. N (n is an integer of 2 or more) switch elements including one control electrode;
(B) n signal transmission lines individually connected to the first control electrodes;
(C) a third electrode and a second control electrode connected to any one of the n signal transmission lines, wherein a third signal is input to the third electrode, and A light emitting element array including a plurality of light emitting elements that emit light when a control signal is input to the second control electrode,
Each signal transmission line is connected to at least one second control electrode of the light emitting element,
The first electrodes of the n switch elements are electrically connected to each other;
The said switch element and the said light emitting element are comprised including the light emitting thyristor as described in any one of Claims 1-3 which makes a cathode or an anode a common electrode, and the said switch element is further 1st and 2nd. Consisting of a resistor
(A) When the cathode is a common electrode,
The N gate electrode of the light emitting thyristor constituting the switch element is connected to one end of each of the first and second resistors,
A positive voltage is applied to the other electrode of the first resistor with respect to the common electrode,
The first electrode is the other end of the second resistor;
The second electrode is an anode of a light-emitting thyristor constituting a switch element;
The third electrode is an anode of a light emitting thyristor constituting a light emitting element,
The first control electrode is an N gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode is an N gate electrode of a light emitting thyristor constituting a light emitting element,
(B) When the anode is a common electrode,
The P gate electrode of the light emitting thyristor constituting the switch element is connected to one end of each of the first and second resistors,
A negative voltage is applied to the other electrode of the first resistor with respect to the common electrode,
The first electrode is the other end of the second resistor;
The second electrode is a cathode of a light emitting thyristor constituting a switch element,
The third electrode is a cathode of a light emitting thyristor constituting a light emitting element,
The first control electrode is a P gate electrode of a light emitting thyristor constituting a switch element,
The light emitting element array, wherein the second control electrode is a P gate electrode of a light emitting thyristor constituting the light emitting element. (A) A first control signal is output when a first signal is input to the first electrode, the second electrode, and the first electrode, and a second signal is input to the second electrode. N (n is an integer of 2 or more) switch elements including one control electrode;
(B) n signal transmission lines individually connected to the first control electrodes;
(C) a third electrode and a second control electrode connected to any one of the n signal transmission lines, wherein a third signal is input to the third electrode, and A light emitting element array including a plurality of light emitting elements that emit light when a control signal is input to the second control electrode,
Each signal transmission line is connected to at least one second control electrode of the light emitting element,
The first electrodes of the n switch elements are electrically connected to each other;
The said switch element and the said light emitting element are comprised including the light emitting thyristor as described in any one of Claims 1-3 which makes a cathode or an anode a common electrode, and the said switch element is further comprised including a resistor. And
(A) When the cathode is a common electrode,
The N gate electrode of the light emitting thyristor constituting the switch element is connected to one end of the resistor,
The first electrode is the other end of the resistor;
The second electrode is an anode of a light-emitting thyristor constituting a switch element;
The third electrode is an anode of a light emitting thyristor constituting a light emitting element,
The first control electrode is an N gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode is an N gate electrode of a light emitting thyristor constituting a light emitting element,
(B) When the anode is a common electrode,
The P gate electrode of the light emitting thyristor constituting the switch element is connected to one end of the resistor,
The first electrode is the other end of the resistor;
The second electrode is a cathode of a light emitting thyristor constituting a switch element,
The third electrode is a cathode of a light emitting thyristor constituting a light emitting element,
The first control electrode is a P gate electrode of a light emitting thyristor constituting a switch element,
The second control electrode includes a light emitting element array unit including a plurality of light emitting element arrays which are P gate electrodes of light emitting thyristors constituting the light emitting element,
A first drive circuit electrically connected to the first electrode and supplying the first signal;
A second drive circuit electrically connected to the second electrode and supplying the second signal;
A third drive circuit electrically connected to the third signal and supplying the third signal;
The light emitting device according to claim 1, wherein the first driving circuit includes first signal level setting means for setting a potential of the high level or the low level of the first signal having a high level and a low level.   6. The light emitting device according to claim 5, further comprising a light shielding means or a light reducing means for shielding or reducing light emitted from the light emitting thyristor constituting the switch element. A light emitting device according to claim 5 or 6,
Driving means for driving the light emitting device based on image information;
Condensing means for condensing light from the light emitting element of the light emitting device on the photosensitive drum;
Developer supplying means for supplying the developer to the exposed photosensitive drum by which light from the light emitting device is condensed on the photosensitive drum by the condensing means;
Transfer means for transferring an image formed by a developer on the photosensitive drum to a recording sheet;
An image forming apparatus comprising: fixing means for fixing the developer transferred to the recording sheet.

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