JP2012020498A - Light-emitting device, print head, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting device which can suppress the number of wiring lines.SOLUTION: Light-emitting chips Ca1-Ca20 belonging to a light-emitting chip group #a, light-emitting chips Cb1-Cb20 belonging to a light-emitting chip group #b, and a signal generating circuit 110 are mounted on a circuit board 62 of the light-emitting device 65. The signal generating circuit 110 includes an enabling signal generating part 130 which transmits enable signals φE to the light-emitting chip groups #a and #b, and a write signal generating part 150 which transmits write signals φW1-φW20 for each set formed by the light-emitting chip Ca of the light-emitting chip group #a and the light-emitting chip Cb of the light-emitting chip group #b.

Description

  The present invention relates to a light emitting device, a print head, and an image forming apparatus.

  In an image forming apparatus such as a printer, copier, or facsimile that employs an electrophotographic system, an electrostatic latent image is obtained by irradiating image information onto a charged photosensitive member by an optical recording means, and then the static image is obtained. An image is formed by adding toner to the electrostatic latent image to make it visible, and transferring and fixing it on a recording sheet. In addition to the optical scanning method in which a laser is used as the optical recording means and the exposure is performed by scanning the laser beam in the main scanning direction, in recent years, a light emitting diode (LED: Light) as a light emitting element in response to a request for downsizing of the apparatus. A recording apparatus using an LED print head (LPH: LED Print Head) in which a plurality of Emitting Diodes (Arrays) are arranged in the main scanning direction is employed.

  In Patent Document 1, a terminal for controlling whether or not to emit light when a lighting signal is input to the light emitting element chip is provided, and by using a general-purpose shift register IC, a plurality of chips can emit light on one data line. A self-scanning light emitting element array in which data for multiplexing is multiplexed is described.

JP 2001-219596 A

  By the way, in the LPH recording apparatus using a plurality of self-scanning light emitting device array (SLED: Self-scanning Light Emitting Device) chips, the wiring for transmitting the lighting signal to the SLED chip supplies the current for lighting. A low resistance is required. Therefore, in order to light a plurality of SLED chips in parallel, if a wiring for lighting is provided in each of the plurality of SLED chips, a wide, low-resistance lighting signal is provided on a circuit board on which the plurality of SLED chips are mounted. As a result, a large number of wirings for transmitting the circuit board are provided, which increases the width of the circuit board and hinders miniaturization. In addition, if the wiring is formed in multiple layers in order to reduce the width of the circuit board, it becomes an obstacle to cost reduction.

  An object of this invention is to provide the light-emitting device etc. which can suppress the number of wiring.

The invention described in claim 1 includes a first light emitting chip group including a plurality of first light emitting chips, each of which includes a plurality of light emitting elements, and lighting is permitted at a first potential level. A second light emitting chip group including a plurality of second light emitting chips, which includes a plurality of light emitting elements and which is permitted to be lit at a second potential level, and the plurality of second light emitting chips belonging to the first light emitting chip group. A permission signal having a period of the first potential level and a period of the second potential level is commonly applied to the plurality of second light emitting chips belonging to one light emitting chip and the second light emitting chip group. A plurality of sets, each including permission signal supply means for transmitting, a first light emitting chip each belonging to the first light emitting chip group, and a second light emitting chip belonging to the second light emitting chip group In contrast, the first During the potential level period, the light emitting elements of the first light emitting chip belonging to the first light emitting chip group are set to be lit or not lit, and during the second potential level period, the second light emitting chip group. The light emitting device includes a writing signal supply unit that transmits a writing signal for setting the light emitting element of the second light emitting chip belonging to 1 to be turned on or off in common for each set.
According to a second aspect of the present invention, each of the plurality of first light emitting chips belonging to the first light emitting chip group is sequentially turned on or off with respect to each light emitting element of the plurality of first light emitting chips. A first transfer signal supply means for commonly transmitting a first transfer signal to be specified and a plurality of second light emitting chips belonging to the second light emitting chip group belonging to the second light emitting chip group. The second transfer signal supply means for commonly transmitting a second transfer signal for sequentially designating each of the light emitting elements as a target to be lit or not lit, further comprising: A light emitting device.
According to a third aspect of the present invention, the second transfer signal supply means shifts the timing on the time axis with respect to the first transfer signal transmitted by the first transfer signal supply means, The light emitting device according to claim 2, wherein the second transfer signal is transmitted.
According to a fourth aspect of the present invention, a first lighting signal that supplies power for lighting to the plurality of first light emitting chips belonging to the first light emitting chip group is commonly transmitted. A second lighting signal supply for commonly transmitting a lighting signal supply means and a second lighting signal for supplying power for lighting to the plurality of second light emitting chips belonging to the second light emitting chip group. The light-emitting device according to claim 1, further comprising: means.
According to a fifth aspect of the present invention, the second lighting signal supply means shifts the timing on the time axis with respect to the first lighting signal transmitted by the first lighting signal supply means, The light emitting device according to claim 4, wherein the second lighting signal is transmitted.

According to a sixth aspect of the present invention, the first light emitting chip is provided on the substrate and the substrate, and each of the plurality of first light emitting chips has a first gate terminal, a first anode terminal, and a first cathode terminal. A transfer thyristor, a plurality of first electrical means provided on the substrate, and connected to the first gate terminals of the transfer thyristors of the plurality of transfer thyristors, respectively, and provided on the substrate; , Each having a second gate terminal, a second anode terminal, and a second cathode terminal, the first gate terminal of each transfer thyristor of the plurality of transfer thyristors, and the second gate terminal Are provided on the substrate, each of which has a third gate terminal, a third anode terminal, and a third cathode. A plurality of light-emitting elements each having a child, wherein the second gate terminal of each write thyristor of the plurality of write thyristors is connected to the third gate terminal via a third electrical means, respectively. A thyristor and one end of a write signal line provided on the substrate and connecting either the second anode terminal or the second cathode terminal of each of the write thyristors of the plurality of write thyristors; A write resistor provided between the write signal terminal to which the write signal is transmitted, an end of the write signal line provided on the substrate, and an enable signal terminal to which the enable signal is transmitted A first permission resistor and a second permission resistor provided in series with each other, and a fourth gate terminal, a fourth anode terminal, and a fourth cathode terminal provided on the substrate. And the fourth anode Either the child or the fourth cathode terminal includes a first permission thyristor connected to a connection point between the first permission resistor and the second permission resistor. 6. The light emitting device according to any one of 1 to 5.
According to a seventh aspect of the present invention, the second light emitting chip is provided on a substrate and the substrate, and each of the plurality of second light emitting chips has a first gate terminal, a first anode terminal, and a first cathode terminal. A transfer thyristor, a plurality of first electrical means provided on the substrate, and connected to the first gate terminals of the transfer thyristors of the plurality of transfer thyristors, respectively, and provided on the substrate; , Each having a second gate terminal, a second anode terminal, and a second cathode terminal, the first gate terminal of each transfer thyristor of the plurality of transfer thyristors, and the second gate terminal Are provided on the substrate, each of which has a third gate terminal, a third anode terminal, and a third cathode. A plurality of light-emitting elements each having a child, wherein the second gate terminal of each write thyristor of the plurality of write thyristors is connected to the third gate terminal via a third electrical means, respectively. A thyristor and one end of a write signal line provided on the substrate and connecting either the second anode terminal or the second cathode terminal of each of the write thyristors of the plurality of write thyristors; A write resistor provided between the write signal terminal to which the write signal is transmitted, an end of the write signal line provided on the substrate, and an enable signal terminal to which the enable signal is transmitted A third permission resistor and a permission diode provided in series between each other, and a fifth gate terminal, a fifth anode terminal, and a fifth cathode terminal provided on the substrate, 5th gate end The second permission thyristor connected to the connection point between the third permission resistor and the permission diode via the fourth permission resistor, the fifth gate terminal, and the permission to transmit the permission signal. The light-emitting device according to claim 1, further comprising a fifth permission resistor provided between the signal terminal and the signal terminal.

  The invention according to claim 8 includes a first light emitting chip group including a plurality of first light emitting chips, each of which includes a plurality of light emitting elements, and lighting is permitted at a first potential level. A second light-emitting chip group including a plurality of second light-emitting chips that includes a plurality of light-emitting elements and that is permitted to be lit at a second potential level, and the plurality of second light-emitting chips belonging to the first light-emitting chip group. A permission signal having a period of the first potential level and a period of the second potential level is commonly applied to the plurality of second light emitting chips belonging to one light emitting chip and the second light emitting chip group. A plurality of sets including permission signal supply means for transmitting, a first light emitting chip each belonging to the first light emitting chip group, and a second light emitting chip belonging to the second light emitting chip group In contrast, the first During the potential level period, the light emitting elements of the first light emitting chip belonging to the first light emitting chip group are set to be lit or not lit, and during the second potential level period, the second light emitting chip group. And a writing signal supply means for transmitting a writing signal for setting the light emitting element of the second light emitting chip belonging to the group to be turned on or off in common to each set, and exposing the image carrier to static A print head comprising: an exposure unit that forms an electrostatic latent image; and an optical unit that forms an image of light emitted from the exposure unit on the image carrier.

  According to a ninth aspect of the present invention, there is provided charging means for charging the image holding member, and a plurality of first light emitting chips each including a plurality of light emitting elements and lighting permitted at a first potential level. A first light-emitting chip group, a second light-emitting chip group including a plurality of second light-emitting chips, each of which includes a plurality of light-emitting elements and is allowed to be lit at a second potential level; The plurality of first light emitting chips belonging to the light emitting chip group and the plurality of second light emitting chips belonging to the second light emitting chip group have a period of the first potential level and the second potential level. A permission signal supply means for commonly transmitting a permission signal having a period, a first light emitting chip each belonging to the first light emitting chip group, and a second light emitting chip belonging to the second light emitting chip group And consists of The light-emitting elements of the first light-emitting chips belonging to the first light-emitting chip group are set to be lit or not lit for the plurality of sets in the period of the first potential level, and the second potential Write signal supply means for commonly transmitting a write signal for each set of light emitting elements of the second light emitting chip belonging to the second light emitting chip group to be turned on or off during the level period An exposure unit that exposes the image carrier to form an electrostatic latent image, an optical unit that forms an image of light emitted from the exposure unit on the image carrier, and the image carrier. An image forming apparatus comprising: a developing unit that develops the formed electrostatic latent image; and a transfer unit that transfers an image developed on the image holding member to a transfer target.

According to the first aspect of the present invention, the number of wirings can be suppressed as compared with a case where a plurality of light emitting chips are driven without being divided into groups and groups.
According to the second aspect of the present invention, it is possible to control lighting or non-lighting for each group of light emitting chips as compared with the case where the present configuration is not provided.
According to the invention of claim 3, the margin for setting a signal for driving can be widened as compared with the case where the present configuration is not provided.
According to invention of Claim 4, compared with the case where it does not have this structure, the number of the wiring which supplies the electric current for lighting can be suppressed.
According to the invention of claim 5, the lighting period can be set for each group of light emitting chips as compared with the case where this configuration is not provided.
According to the sixth and seventh aspects of the present invention, the light emitting chip can be configured more easily than when the present configuration is not provided.
According to invention of Claim 8, compared with the case where it does not have this structure, a print head can be made smaller.
According to the ninth aspect of the present invention, the image forming apparatus can be made smaller as compared with the case where the present configuration is not provided.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. It is sectional drawing which showed the structure of the print head. It is a top view of a light-emitting device. It is the figure which showed the arrangement of the light emitting element in a light emitting chip, the structure of a bonding pad, the structure of the signal generation circuit in a light emitting device, and the wiring structure on a circuit board. It is the figure which showed and arranged the light emitting chip which belongs to light emitting chip group #a of the light emitting device, and the light emitting chip which belongs to light emitting chip group #b as each element of a matrix. It is an equivalent circuit diagram for demonstrating the circuit structure of light emitting chip Ca which is a self-scanning light emitting element array (SLED). It is the plane layout figure and sectional drawing of light emitting chip Ca. It is an equivalent circuit diagram for demonstrating the circuit structure of the light emitting chip Cb which is a self-scanning light emitting element array (SLED). It is the plane layout figure and sectional drawing of the light emitting chip Cb. In the light emitting chip Ca, it is a diagram for explaining the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line (φWL (Ca)). In the light-emitting chip Cb, the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line (φWL (Cb)) is described. 6 is a timing chart showing the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line (φWL (Ca) and φWL (Cb)) for the light emitting chips Ca and Cb. . 3 is a timing chart for explaining the operation of the light emitting device according to the first embodiment. 6 is a timing chart for explaining the operation of the light emitting device according to the second embodiment.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
[First Embodiment]
(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at predetermined intervals. The image forming unit 11 includes four image forming units 11Y, 11M, 11C, and 11K. The image forming units 11Y, 11M, 11C, and 11K have predetermined surfaces of the photosensitive drum 12 and the photosensitive drum 12 as an example of an image holding body that forms an electrostatic latent image and holds a toner image, respectively. An example of a charging unit 13 as an example of a charging unit that charges at a potential, a print head 14 that exposes a photosensitive drum 12 charged by the charging unit 13, and an example of a developing unit that develops an electrostatic latent image obtained by the print head 14 The developing device 15 is provided. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, the sheet conveying belt 21 that conveys the recording sheet 25, the driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25 are exemplified. A transfer roll 23 and a fixing device 24 for fixing the toner image on the recording paper 25 are provided.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the print head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. Electrostatic transfer is sequentially performed by the transfer electric field, and a composite toner image in which toner of each color is superimposed on the recording paper 25 is formed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing processing by heat and pressure by the fixing device 24, and is discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing the configuration of the print head 14. The print head 14 includes a light emitting device 65 as an example of an exposure unit including a housing 61 and a light emitting unit 63 including a plurality of light emitting elements that expose the photoconductive drum 12, and light emitted from the light emitting unit 63. A rod lens array 64 is provided as an example of optical means for forming an image on 12 surfaces.
The light emitting device 65 includes a circuit board 62 on which a light emitting unit 63 and a signal generation circuit M that generates a signal for driving the light emitting unit 63 are mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that an image of the light emitting point in the light emitting element of the light emitting unit 63 is formed on the focal plane of the rod lens array 64. ing. Further, the rod lens array 64 is arranged along the axial direction (main scanning direction) of the photosensitive drum 12.

(Light emitting device 65)
FIG. 3 is a top view of the light emitting device 65.
As shown in FIG. 3, in the light emitting device 65 according to the present embodiment, the light emitting unit 63 includes 20 light emitting chips Ca1 to Ca20 (light emitting chip group as an example of the first light emitting chip group) on a circuit board 62. #A) and 20 light emitting chips Cb1 to Cb20 (light emitting chip group #b as an example of the second light emitting chip group) are arranged in a staggered pattern in two rows in the main scanning direction. Yes. That is, in this embodiment, two light emitting chip groups (light emitting chip group #a and light emitting chip group #b) are provided. Here, the light emitting chip group may be abbreviated as a group. The details of facing the light emitting chip group #a and the light emitting chip group #b will be described later.
In the present specification, “to” indicates a plurality of components each distinguished by a number, and includes those described before and after “to”, and includes the number between them. . For example, the light emitting chips Ca1 to Ca20 include the light emitting chips Ca20 in numerical order from the light emitting chip Ca1.

As described above, the light emitting device 65 includes the signal generation circuit 110 that drives the light emitting unit 63.
The light emitting chips Ca1 to Ca20 have the same configuration, and the light emitting chips Cb1 to Cb20 have the same configuration. However, as will be described later, the configurations of the light emitting chips Ca1 to Ca20 and the configurations of the light emitting chips Cb1 to Cb20 are different. Accordingly, when the light emitting chips Ca1 to Ca20 are not distinguished from each other, the light emitting chip Ca as an example of the first light emitting chip, and when the light emitting chips Cb1 to Cb20 are not distinguished from each other, the light emitting chip Cb as an example of the second light emitting chip. write.
In the present embodiment, 20 light emitting chips Ca and Cb are used, respectively, but the present invention is not limited to this.

(Light-Emitting Chip Ca / Cb and Circuit Board 62)
FIG. 4 is a diagram showing the arrangement of the light emitting elements in the light emitting chips Ca and Cb, the configuration of the bonding pads, the configuration of the signal generation circuit 110 in the light emitting device 65, and the wiring configuration on the circuit board 62. FIG. 4A is a view showing light emitting chips Ca and Cb (referred to as light emitting chips Ca / Cb in FIG. 4A). FIG. 4B is a diagram illustrating the configuration of the signal generation circuit 110 and the wiring configuration on the circuit board 62 in the light emitting device 65. In the light emitting chips Ca and Cb, the arrangement of the light emitting elements and the configuration of the bonding pads are the same.

First, the arrangement of the light emitting elements and the configuration of the bonding pads in the light emitting chips Ca and Cb shown in FIG. 4A will be described.
The light emitting chips Ca and Cb are a plurality of light emitting elements (in the present embodiment, light emitting thyristors L1, L2, L3,...) Provided in a row along one long side of the substrate 80 on the rectangular substrate 80. The light emitting element row | line | column 102 comprised from these is provided. Note that the light-emitting thyristors L1, L2, L3,.
Further, the light emitting chips Ca and Cb are terminals (φE terminal, φ1 terminal, Vga terminal, φ2 terminal, φW, which are a plurality of bonding pads for receiving various control signals and the like at both ends in the long side direction of the substrate 80. Terminal, φI terminal). These terminals are provided in order of the φE terminal, φ1 terminal, and Vga terminal from one end of the substrate 80, and are provided in the order of the φI terminal, φW terminal, and φ2 terminal from the other end of the substrate 80. The light emitting element array 102 is provided between the Vga terminal and the φ2 terminal.
The light emitting chips Ca and Cb are each provided with a Vsub terminal (not shown) for setting a potential reference on the back surface of the substrate 80.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the wiring configuration on the circuit board 62 will be described with reference to FIG.
As described above, the circuit board 62 of the light emitting device 65 is mounted with the signal generating circuit 110, the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a, and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. Wiring for connecting the generation circuit 110 to the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 is provided.

First, the configuration of the signal generation circuit 110 will be described.
Although not shown, the image generation unit 110 and the image processing unit 40 (see FIG. 1) transmit image processed image data and various control signals to the signal generation circuit 110. Based on these image data and various control signals, the signal generation circuit 110 rearranges the image data and corrects the light amount.
Then, the signal generation circuit 110 sends the first transfer signal φ1a and the second transfer signal as an example of the first transfer signal to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a based on various control signals. The transfer signal generator 120a as an example of the first transfer signal supply means for transmitting φ2a and the first as an example of the second transfer signal for the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. A transfer signal generator 120b as an example of a second transfer signal supply means for transmitting the transfer signal φ1b and the second transfer signal φ2b is provided.
Here, the first transfer signal φ1a and the second transfer signal φ2a generated by the transfer signal generating unit 120a are combined, and the first transfer signal φ1b and the second transfer generated by the transfer signal generating unit 120b are combined. The signal φ2b is collectively referred to as a second transfer signal.

  Further, the signal generation circuit 110 outputs the permission signal φE in common to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b based on various control signals. A permission signal generator 130 is provided as an example of a permission signal supply means for transmitting.

Furthermore, the signal generation circuit 110 transmits a lighting signal φIa as an example of a first lighting signal to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a based on various control signals. Second lighting for transmitting a lighting signal φIb as an example of the second lighting signal to the lighting signal generator 140a as an example of the lighting signal supply means and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. A lighting signal generator 140b as an example of a signal supply means is provided.
Then, the signal generation circuit 110 converts one light emitting chip Ca belonging to the light emitting chip group #a and one light emitting chip Cb belonging to the light emitting chip group #b to one light emitting chip group (light emitting chip) based on various control signals. As a chip set), there is provided a write signal generator 150 as an example of a write signal supply means for transmitting write signals φW1 to φW20 for each light emitting chip set. Here, the light emitting chip set may be referred to as a set.
For example, the write signal generation unit 150 transmits the write signal φW1 to the light emitting chip set # 1 formed by the light emitting chip Ca1 belonging to the light emitting chip group #a and the light emitting chip Cb1 belonging to the light emitting chip group #b. To do. The write signal φW2 is transmitted to the light emitting chip set # 2 formed by the light emitting chip Ca2 belonging to the light emitting chip group #a and the light emitting chip Cb2 belonging to the light emitting chip group #b. Similarly, the write signal φW20 is transmitted to the light emitting chip set # 20 formed by the light emitting chip Ca20 belonging to the light emitting chip group #a and the light emitting chip Cb20 belonging to the light emitting chip group #b.

In FIG. 4, the transfer signal generation unit 120 a and the transfer signal generation unit 120 b are illustrated separately, but these are collectively referred to as the transfer signal generation unit 120.
Similarly, although the lighting signal generator 140a and the lighting signal generator 140b are shown separately, they are collectively referred to as the lighting signal generator 140.
Further, similarly, when the first transfer signal φ1a and the first transfer signal φ1b are not distinguished from each other, the first transfer signal φ1a is represented as the first transfer signal φ1, and when the second transfer signal φ2a and the second transfer signal φ2b are not distinguished from each other, 2 written as transfer signal φ2. Similarly, when the lighting signal φIa and the lighting signal φIb are not distinguished, the lighting signal φI and the write signals φW1 to φW20 are collectively referred to as a write signal φW.

Next, the arrangement of the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 will be described.
The light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a are arranged in a row on the circuit board 62 in the long side direction of the substrate 80, respectively. Similarly, the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b are also arranged in a line in the long side direction of the substrate 80, respectively. The light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b face each other, and the light emitting elements are arranged at a predetermined interval in the X direction which is the main scanning direction. So that they are arranged in a staggered pattern.

The wiring that connects the signal generation circuit 110 to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b will be described.
The circuit board 62 is connected to a Vsub terminal (see FIGS. 7 and 9 described later) provided on the back surface of each of the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20, and supplies a reference potential Vsub. A line 200a is provided. A power supply line 200b is provided which is connected to Vga terminals provided in the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 and supplies a power supply potential Vga for supplying power.

Further, on the circuit board 62, a first transfer signal line for transmitting the first transfer signal φ1a from the transfer signal generating unit 120a of the signal generating circuit 110 to the φ1 terminals of the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a. The second transfer signal line 202a for transmitting the second transfer signal φ2a is provided at the φ2 terminal of the light emitting chips Ca1 to Ca20 belonging to 201a and the light emitting chip group #a. The first transfer signal φ1a and the second transfer signal φ2a are transmitted in common (in parallel) to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a.
Similarly, a first transfer signal line 201b for transmitting the first transfer signal φ1b from the transfer signal generation unit 120b of the signal generation circuit 110 to the φ1 terminals of the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b, and The second transfer signal line 202b for transmitting the second transfer signal φ2b is provided at the φ2 terminal of the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. The first transfer signal φ1b and the second transfer signal φ2b are transmitted in common (in parallel) to the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b.

  The circuit board 62 is connected to the φE terminals of the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b from the permission signal generating unit 130 of the signal generating circuit 110. A permission signal line 203 for transmitting the permission signal φE is provided. The permission signal φE is transmitted in common (in parallel) to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b.

Further, the circuit board 62 has a lighting signal line 204a for transmitting the lighting signal φIa from the lighting signal generator 140a of the signal generation circuit 110 to the φI terminals of the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a. Is provided. The lighting signal φIa is transmitted in common (in parallel) to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a via the current limiting resistors RI provided for the light emitting chips Ca1 to Ca20.
Similarly, a lighting signal line 204b for transmitting the lighting signal φIb is provided from the lighting signal generator 140b of the signal generation circuit 110 to the φI terminals of the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. The lighting signal φIb is transmitted in common (in parallel) to the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b via the current limiting resistors RI provided for the light emitting chips Cb1 to Cb20.

Furthermore, the circuit board 62 includes one light emitting chip Ca belonging to the light emitting chip group #a and one light emitting chip Cb belonging to the light emitting chip group #b from the write signal generating unit 150 of the signal generating circuit 110. Write signal lines 205 to 224 for transmitting write signals φW1 to φW20 are provided for each light emitting chip group.
For example, the write signal line 205 is connected to the φW terminal of the light emitting chip Ca1 belonging to the light emitting chip group #a and the φW terminal of the light emitting chip Cb1 belonging to the light emitting chip group #b, and the light emitting chip Ca1 and the light emitting chip Cb1 are connected. A write signal φW1 is transmitted to the light emitting chip set # 1 to be configured. The write signal line 206 is connected to the φW terminal of the light emitting chip Ca2 belonging to the light emitting chip group #a and the φW terminal of the light emitting chip Cb2 belonging to the light emitting chip group #b, and is configured by the light emitting chip Ca2 and the light emitting chip Cb2. Write signal φW2 is transmitted to light emitting chip set # 2. Similarly, the write signal line 224 is connected to the φW terminal of the light emitting chip Ca20 belonging to the light emitting chip group #a and the φW terminal of the light emitting chip Cb20 belonging to the light emitting chip group #b, and the light emitting chip Ca20 and the light emitting chip are connected. A write signal φW20 is transmitted to the light emitting chip set # 20 composed of Cb20.

As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips Ca1 to Ca20 and Cb1 to Cb20 on the circuit board 62.
The permission signal φE is also transmitted in common to all the light emitting chips Ca1 to Ca20 and Cb1 to Cb20 on the circuit board 62 regardless of the light emitting chip groups #a and #b.
The first transfer signal φ1a, the second transfer signal φ2a, and the lighting signal φIa are transmitted in common to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a. The first transfer signal φ1b, the second transfer signal φ2b, and the lighting signal φIb are transmitted in common to Cb1 to Cb20 belonging to the light emitting chip group #b.
On the other hand, the write signals φW1 to φW20 are transmitted to each of the light emitting chip groups # 1 to # 20 formed by one light emitting chip C belonging to the light emitting chip group #a and one light emitting chip C belonging to the light emitting chip group #b. It is transmitted in common.

FIG. 5 shows the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b of the light emitting device 65 according to the first embodiment as elements of the matrix. It is a figure.
In FIG. 5, the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b are arranged as respective elements of a matrix of 2 rows × 20 columns, and from the signal generation circuit 110. Signals transmitted to the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 (first transfer signals φ1a, φ1b, second transfer signals φ2a, φ2b, lighting signals φIa, φIb, permission signals φE, write signals φW1 to φW20) The wiring (line) is shown.
As described above, the first transfer signal φ1a, the second transfer signal φ2a, and the lighting signal φIa are transmitted in common to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a. It can be easily understood that the first transfer signal φ1b, the second transfer signal φ2b, and the lighting signal φIb are transmitted in common to the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b.
On the other hand, the write signals φW1 to φW20 are respectively transmitted to the light emitting chip groups # 1 to # 20 formed by one light emitting chip Ca belonging to the light emitting chip group #a and one light emitting chip Cb belonging to the light emitting chip group #b. It can be easily understood that the data is transmitted in common.
In contrast, it can be easily understood that the permission signal φE is transmitted in common to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b.

Here, the number of wirings (lines) on the circuit board 62 will be described.
In this embodiment, as shown in FIGS. 4 and 5, since two light emitting chip groups are used, two lighting signal lines 204a and 204b are used. Further, in addition to the first transfer signal lines 201a and 201b, the second transfer signal lines 202a and 202b, and the power supply lines 200a and 200b, the permission signal line 203 and the write signal lines 205 to 224 are used. Therefore, the number of wirings is 29.
Note that the lighting signal lines 204a and 204b need to have a small resistance in order to transmit a lighting current to the light emitting thyristor L. For this reason, wide wiring is required for the lighting signal lines 204a and 204b. In the case where this embodiment is applied, since there are two lighting signal lines 204a and 204b, an increase in the area of the circuit board 62 of the light emitting device 65 is suppressed.
The write signals φW1 to φW20 are for changing the potential of gate terminals Gm1, Gm2, Gm3,... (See FIGS. 6 and 8 described later) of write thyristors M1, M2, M3,. Thus, the value of the flowing current is smaller than that of the lighting signal lines 204a and 204b. Therefore, a wide wiring is not required for the write signal lines 205 to 224. That is, an increase in the area of the circuit board 62 of the light emitting device 65 is suppressed.

When the present embodiment is not applied, that is, when the light emitting chips Ca1 to Ca20 and Cb1 to Cb20 of the light emitting device 65 are not divided into groups and groups, the lighting signal φI is generated for each of the light emitting chips Ca1 to Ca20 and Cb1 to Cb20. Sent. If the number of the light emitting chips Ca1 to Ca20 and Cb1 to Cb20 is 40, 40 lighting signal lines 204 (corresponding to the lighting signal lines 204a and 204b in FIG. 4) are required. In addition, one first transfer signal line 201 (corresponding to the first transfer signal lines 201a and 201b in FIG. 4) and one second transfer signal line 202 (corresponding to the second transfer signal lines 202a and 202b in FIG. 4) One power supply line 200a, 200b is required in addition to this. Therefore, the number of wirings provided in the light emitting device 65 is 44.
Note that when this embodiment is not applied, the group and the set are not provided, so that the permission signal line 203 and the write signal lines 205 to 224 are not required.
However, as described above, the lighting signal line 204 that transmits a current for lighting to the light emitting thyristor L needs to have a small resistance. Therefore, a wide wiring is necessary for the lighting signal line 204. For this reason, when this embodiment is not applied, 40 wide wirings are provided on the circuit board 62 of the light-emitting device 65, and the area of the circuit board 62 is increased.

  As described above, when the present embodiment is applied, the number of wirings is reduced to 3/4 and an increase in the area of the circuit board 62 can be suppressed as compared with the case where the present embodiment is not applied. .

(Light emitting chip Ca)
FIG. 6 is an equivalent circuit diagram for explaining a circuit configuration of a light emitting chip Ca that is a self-scanning light emitting element array (SLED). In FIG. 6, except for terminals (Vga terminal, φ1 terminal, φ2 terminal, φE terminal, φW terminal, φI terminal), each element described below is a light emitting chip as described in FIG. Arranged based on the layout on Ca.
Here, the light emitting chip Ca will be described by taking the light emitting chip Ca1 as an example. Therefore, in FIG. 6, the light emitting chip Ca is expressed as the light emitting chip Ca1 (Ca). The configuration of the other light emitting chips Ca2 to Ca20 is the same as that of the light emitting chip Ca1.
Note that the positions of the terminals (Vga terminal, φ1 terminal, φ2 terminal, φE terminal, φW terminal, φI terminal) are different from those in FIG. A Vsub terminal is provided on the back surface of the substrate 80.

As described above, the light-emitting chip Ca1 (Ca) is a light-emitting thyristor that includes light-emitting thyristors L1, L2, L3,... A row (light emitting element row 102 (see FIG. 4)) is provided.
Further, the light-emitting chip Ca1 (Ca) includes a transfer thyristor array composed of transfer thyristors T1, T2, T3,. A write thyristor array composed of M1, M2, M3,.
Here, when the transfer thyristors T1, T2, T3,... Are not distinguished from each other, the transfer thyristor T and the write thyristors M1, M2, M3,.

Further, the light emitting chip Ca1 (Ca) includes two pairs of transfer thyristors T1, T2, T3,... In the order of numbers, and coupling diodes Dx1, Dx2, Dx3 as an example of the first electrical means between each pair. , ... Further, connection diodes Dy1, Dy2, Dy3,... As an example of second electrical means are provided between the transfer thyristors T1, T2, T3,... And the write thyristors M1, M2, M3,. Further, connecting diodes Dz1, Dz2, Dz3,... As an example of third electrical means are provided between the write thyristors M1, M2, M3,... And the light emitting thyristors L1, L2, L3,.
Furthermore, the light emitting chip Ca1 (Ca) includes power supply line resistances Rgx1, Rgx2, Rgx3,..., Power supply line resistances Rgy1, Rgy2, Rgy3,.

  Here, similarly to the light-emitting thyristor L and the like, the coupling diodes Dx1, Dx2, Dx3,..., The connection diodes Dy1, Dy2, Dy3,..., The connection diodes Dz1, Dz2, Dz3, ..., the power supply line resistances Rgx1, Rgx2, Rgx3,. .., Power line resistances Rgy1, Rgy2, Rgy3,..., Power line resistances Rgz1, Rgz2, Rgz3,... Are not distinguished from each other when coupled diode Dx, connection diode Dy, connection diode Dz, power line resistance Rgx, power line They are expressed as a resistance Rgy and a power supply line resistance Rgz.

6, the light emitting thyristors L1, L2, L3,... Of the light emitting thyristor array, the transfer thyristors T1, T2, T3,... Of the transfer thyristor array, and the write thyristors M1, M2, M3,. Are arranged in numerical order from the left side. Furthermore, coupling diodes Dx1, Dx2, Dx3,..., Connection diodes Dy1, Dy2, Dy3,..., Connection diodes Dy1, Dy2, Dy3,. Similarly, Rgy3,..., Power line resistances Rgz1, Rgz2, Rgz3,... Are also arranged in numerical order from the left side in the figure.
The light emitting thyristor array, the transfer thyristor array, and the write thyristor array are arranged in the order of the transfer thyristor array, the write thyristor array, and the light emitting thyristor array from the top in FIG.

In FIG. 6, the light emitting thyristors L1 to L6 are mainly shown in the light emitting thyristor array. However, the number of light emitting thyristors L in the light emitting thyristor array may be a predetermined number. In this embodiment, if the number of light emitting thyristors L is, for example, 128, the number of transfer thyristors T and write thyristors M is also 128. Similarly, the number of connection diodes Dy, connection diodes Dz, power supply line resistances Rgx, power supply line resistances Rgy, and power supply line resistances Rgz is also 128. However, the number of coupling diodes Dx is 127, which is one less than the number of transfer thyristors T.
The number of transfer thyristors T and write thyristors M may be larger than the number of light-emitting thyristors L.

The light emitting chip Ca1 (Ca) includes one start diode Dx0. Further, a current limiting resistor R1 for preventing an excessive current from flowing through a first transfer signal line 72 that transmits a first transfer signal φ1 and a second transfer signal line 73 that transmits a second transfer signal φ2, which will be described later. And a current limiting resistor R2.
Furthermore, a permission thyristor Sa as an example of a first permission thyristor, a power supply line resistance Rga, a permission resistor Ra as an example of a first permission resistor, a permission resistor Rb as an example of a second permission resistor, and a write resistance RW is provided.

The thyristor (light-emitting thyristor L, transfer thyristor T, write thyristor M, permission thyristor Sa) is a semiconductor element having three terminals: an anode terminal, a cathode terminal, and a gate terminal.
Here, the anode terminal of the transfer thyristor T may be referred to as a first anode terminal, the cathode terminal as a first cathode terminal, and the gate terminal as a first gate terminal. Similarly, the anode terminal of the write thyristor M may be referred to as a second anode terminal, the cathode terminal as a second cathode terminal, and the gate terminal as a second gate terminal. Further, the anode terminal of the light emitting thyristor L may be referred to as a third anode terminal, the cathode terminal as a third cathode terminal, and the gate terminal as a third gate terminal. The anode terminal of the permission thyristor Sa may be referred to as a fourth anode terminal, the cathode terminal as a fourth cathode terminal, and the gate terminal as a fourth gate terminal.

Next, electrical connection of each element in the light emitting chip Ca1 (Ca) will be described.
The anode terminal of the transfer thyristor T, the anode terminal of the write thyristor M, the anode terminal of the light emitting thyristor L, and the anode terminal of the permission thyristor Sa are connected to the substrate 80 of the light emitting chip Ca1 (Ca) (anode common).
These anode terminals are connected to the power supply line 200a (see FIG. 4) via the Vsub terminal which is a back electrode 85 (see FIG. 7 described later) provided on the back surface of the substrate 80. A reference potential Vsub is supplied to the power supply line 200a.

  Along with the arrangement of the transfer thyristors T, the cathode terminals of odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1 on the transfer thyristor T1 side. A first transfer signal line 201a (see FIG. 4) is connected to the φ1 terminal, and the first transfer signal φ1a is transmitted.

  On the other hand, the cathode terminals of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 along the arrangement of the transfer thyristors T. The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2 on the transfer thyristor T2 side. The second transfer signal line 202a (see FIG. 4) is connected to the φ2 terminal, and the second transfer signal φ2a is transmitted.

The cathode terminal of the write thyristor M is connected to the write signal line 74. The write signal line 74 is connected to the φW terminal as an example of the write signal terminal via the write resistor RW on the write thyristor M1 side. In the light emitting chip Ca1, the write signal line 205 (see FIG. 4) is connected to the φW terminal, and the write signal φW1 is transmitted.
As shown in FIG. 4, write signal lines 206 to 224 are connected to the φW terminals of the other light emitting chips Ca2 to Ca20, and write signals φW2 to φW20 are transmitted.

  The write signal line 74 branches between the write thyristor M1 and the write resistor RW, and is connected to the φE terminal as an example of the enable signal terminal through the enable resistors Rb and Ra connected in series in this order. ing. The enable signal line 203 (see FIG. 4) is connected to the φE terminal, and the enable signal φE is transmitted.

The cathode terminal of the light emitting thyristor L is connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal on the light emitting thyristor L1 side. A lighting signal line 204a (see FIG. 4) is connected to the φI terminal, and a lighting signal φIa is transmitted.
As shown in FIG. 4, a current limiting resistor RI is provided between the lighting signal generator 140a and the φI terminal, but the description is omitted in FIG.

  The gate terminals Gt1, Gt2, Gt3,... Of the transfer thyristor T are connected to the gate terminals Gm1, Gm2, Gm3,... Of the write thyristors M1, M2, M3,. It is connected via Dy2, Dy3,. Is connected to the gate terminals Gt1, Gt2, Gt3,... Of the transfer thyristors T1, T2, T3,..., And the cathodes of the connection diodes Dy1, Dy2, Dy3,. The terminals are connected to the gate terminals Gm1, Gm2, Gm3,... Of the write thyristors M1, M2, M3,.

  On the other hand, the gate terminals Gm1, Gm2, Gm3,... Of the write thyristors M1, M2, M3,... Are paired with the gate terminals Gl1, Gl2, Gl3,. 1 are connected via connecting diodes Dz1, Dz2, Dz3,. That is, the anode terminals of the connection diodes Dz1, Dz2, Dz3,... Are connected to the gate terminals Gm1, Gm2, Gm3,. The cathode terminal is connected to the gate terminals Gl1, Gl2, Gl3,... Of the light emitting thyristors L1, L2, L3,.

Also here, when the gate terminals Gt1, Gt2, Gt3,..., The gate terminals Gm1, Gm2, Gm3,..., The gate terminals Gl1, Gl2, Gl3,. Indicated as Gl.
The connection diode Dy is connected in a direction in which a current flows from the gate terminal Gt of the transfer thyristor T to the gate terminal Gm of the write thyristor M. Similarly, the connection diode Dz is connected in a direction in which a current flows from the gate terminal Gm of the write thyristor M to the gate terminal Gl of the light emitting thyristor L.

Coupling diodes Dx1, Dx2, Dx3,... Are connected between gate terminals Gt, each of which is a pair of gate terminals Gt1, Gt2, Gt3,. Yes. That is, the coupling diodes Dx1, Dx2, Dx3,... Are connected in series so as to be sandwiched between the gate terminals Gt1, Gt2, Gt3,. The direction of the coupling diode Dx1 is connected in a direction in which a current flows from the gate terminal Gt1 toward the gate terminal Gt2. The same applies to the other coupling diodes Dx2, Dx3, Dx4,.
The gate terminal Gt of the transfer thyristor T is connected to the power supply line 71 via a power supply line resistance Rgx provided corresponding to each transfer thyristor T. The power line 71 is connected to the Vga terminal. The Vga terminal is connected to the power supply line 200b (see FIG. 4) and supplied with the power supply potential Vga.
The gate terminal Gm of the write thyristor M is connected to the power supply line 71 via the power supply line resistance Rgy provided corresponding to each of the write thyristors M.
The gate terminal Gl of the light emitting thyristor L is connected to the power supply line 71 via a power supply line resistance Rgz provided corresponding to each of the light emitting thyristors L.

  The gate terminal Gt1 of the transfer thyristor T1 on one end side of the transfer thyristor array is connected to the cathode terminal of the start diode Dx0. On the other hand, the anode terminal of the start diode Dx 0 is connected to the second transfer signal line 73.

  Furthermore, the gate terminal Gsa of the permission thyristor Sa is connected to the power supply line 71 via the power supply line resistance Rga. Further, the cathode terminal Ksa of the permission thyristor Sa is connected between the permission resistors Ra and Rb connected in series.

FIG. 7 is a plan layout view and a cross-sectional view of the light emitting chip Ca. Unlike FIG. 6, FIG. 7 does not show the connection relationship with the signal generation circuit 110, and thus it is not necessary to take the light emitting chip Ca1 as an example. Therefore, in FIG. 7, it represents with the light emitting chip Ca. FIG. 7A is a plan layout view of the light emitting chip Ca, and shows a portion centering on the light emitting thyristors L1 to L4, the writing thyristors M1 to M4, and the transfer thyristors T1 to T4. FIG. 7B is a cross-sectional view taken along the line VIIB-VIIB shown in FIG. Accordingly, in the cross-sectional view of FIG. 7B, the light-emitting thyristor L1, the connection diode Dz1, the power supply line resistance Rgz1, the power supply line resistance Rgy1, the connection diode Dy1, the transfer thyristor T1, and the coupling diode Dx1 are shown from the bottom in the figure. Has been. 7A and 7B, major elements and terminals are represented by names.
In FIG. 7A, wirings connecting the elements are indicated by solid lines except for the power supply line 71. Further, in FIG. 7B, description of wirings connecting the elements is omitted.

  As shown in FIG. 7B, the light emitting chip Ca is made of a compound semiconductor such as GaAs or GaAlAs. That is, the light emitting chip Ca is provided on the p-type substrate 80 in contact with the substrate 80, and on the p-type first semiconductor layer 81 in contact with the first semiconductor layer 81. N-type second semiconductor layer 82, p-type third semiconductor layer 83 provided on and in contact with second semiconductor layer 82 on n-type second semiconductor layer 82, on p-type third semiconductor layer 83 A plurality of islands (islands) (first islands 301-1) formed by separating the n-type fourth semiconductor layer 84 provided in contact with the third semiconductor layer 83 from each other in a portion excluding the substrate 80. 11th island 311). Some islands do not include the uppermost n-type fourth semiconductor layer 84.

As shown in FIG. 7A, the first island 301 is provided with a light emitting thyristor L1. The second island 302 is provided with a write thyristor M1 and a connection diode Dz1.
As shown in FIG. 7A, the third island 303 is composed of a trunk portion extending left and right in the drawing and a plurality of branch portions separated from the trunk portion. A power line 71 is provided at the trunk, and power line resistances Rgx, Rgy, Rgz, and Rga are provided at the branches.
The fourth island 304 is provided with a transfer thyristor T1, a coupling diode Dx1, and a connection diode Dy1. The fifth island 305 is provided with a start diode Dx0. The sixth island 306 has a current limiting resistor R1, the seventh island 307 has a current limiting resistor R2, the eighth island 308 has a permission resistor Rb, the ninth island 309 has a permission thyristor Sa, and the tenth island 310 has a permission resistance. Ra is provided. The eleventh island 311 is provided with a write resistor RW.
In the light emitting chip Ca, islands similar to the first island 301, the second island 302, and the fourth island 304 are formed in parallel. These islands include light emitting thyristors L2, L3, L4,..., Write thyristors M2, M3, M4,..., Transfer thyristors T2, T3, T4,. Similar to the four islands 304. Description of these will be omitted.
Further, as shown in FIG. 7B, a back surface electrode 85 serving as a Vsub terminal is provided on the back surface of the substrate 80.

Further, the first island 301 to the eleventh island 311 will be described in detail with reference to FIGS. 7A and 7B.
The light emitting thyristor L1 provided on the first island 301 includes a substrate 80 as an anode terminal, an n-type ohmic electrode 121 formed on the region 111 of the n-type fourth semiconductor layer 84 as a cathode terminal, and an n-type fourth semiconductor. The p-type ohmic electrode 131 formed on the p-type third semiconductor layer 83 exposed by removing the layer 84 is used as a gate terminal Gl1. Then, light is emitted from the surface of the region 111 of the n-type fourth semiconductor layer 84 excluding the portion of the n-type ohmic electrode 121.

The write thyristor M1 provided on the second island 302 includes the substrate 80 as an anode terminal, the n-type ohmic electrode 123 formed on the n-type fourth semiconductor layer 84 as a cathode terminal, and the n-type fourth semiconductor layer 84. The p-type ohmic electrode 132 on the p-type third semiconductor layer 83 exposed by removing is used as the gate terminal Gm1.
Similarly, the connection diode Dz1 provided on the second island 302 forms the n-type ohmic electrode 122 provided on the region 112 of the n-type fourth semiconductor layer 84 on the cathode terminal and the p-type third semiconductor layer 83. The formed p-type ohmic electrode 132 (gate terminal Gm1) is formed as an anode terminal.

  The power line resistances Rgx, Rgy, Rgz, Rga provided on the third island 303 are formed between two p-type ohmic electrodes formed on the p-type third semiconductor layer 83. A p-type third semiconductor layer 83 between the two p-type ohmic electrodes is used as a resistor. For example, the power supply line resistance Rgz1 is formed by using the p-type third semiconductor layer 83 between the p-type ohmic electrodes 133 and 134 provided on the p-type third semiconductor layer 83 as a resistance. The power supply line resistance Rgx1 is formed using the p-type third semiconductor layer 83 between the p-type ohmic electrodes 134 and 135 provided on the p-type third semiconductor layer 83 as a resistance. The power supply line resistance Rgy1 is formed using the p-type third semiconductor layer 83 between the p-type ohmic electrodes 134 and 136 provided on the p-type third semiconductor layer 83 as a resistance. The power supply line resistance Rga is formed with the p-type third semiconductor layer 83 between the p-type ohmic electrodes 134 and 161 provided on the p-type third semiconductor layer 83 as a resistance.

The transfer thyristor T1 provided on the fourth island 304 includes the substrate 80 as an anode terminal, the n-type ohmic electrode 125 formed on the region 114 of the n-type fourth semiconductor layer 84 as a cathode terminal, and the n-type fourth semiconductor. The p-type ohmic electrode 137 formed on the p-type third semiconductor layer 83 exposed by removing the layer 84 is used as a gate terminal Gt1.
Similarly, the connection diode Dy1 provided on the fourth island 304 forms the n-type ohmic electrode 124 provided on the region 113 of the n-type fourth semiconductor layer 84 on the cathode terminal and the p-type third semiconductor layer 83. The formed p-type ohmic electrode 137 (gate terminal Gt1) is formed as an anode terminal.
Further, the coupling diode Dx1 similarly provided on the fourth island 304 includes the n-type ohmic electrode 126 provided on the region 115 of the n-type fourth semiconductor layer 84 as the cathode terminal and the p-type third semiconductor layer 83. The p-type ohmic electrode 137 (gate terminal Gt1) formed in the above is formed as an anode terminal.

The start diode Dx0 provided on the fifth island 305 exposes the n-type ohmic electrode 127 provided on the n-type fourth semiconductor layer 84 by removing the cathode terminal and the n-type fourth semiconductor layer 84. The p-type ohmic electrode 138 formed on the p-type third semiconductor layer 83 is formed as an anode terminal.
A current limiting resistor R1 provided on the sixth island 306, a current limiting resistor R2 provided on the seventh island 307, an enabling resistor Rb provided on the eighth island 308, an enabling resistor Ra provided on the tenth island 310, The write resistance RW provided on the eleventh island 311 is a set of p-type ohmic electrodes (reference numerals) formed on the p-type third semiconductor layer 83, similarly to the power line resistances Rgx1, Rgy1, Rgz1, and Rga. The n-type third semiconductor layer 83 is used as a resistor.

  The permission thyristor Sa provided on the ninth island 309 exposes the n-type ohmic electrode 128 provided on the n-type fourth semiconductor layer 84 by removing the cathode terminal and the n-type fourth semiconductor layer 84. A p-type ohmic electrode 139 provided on the p-type third semiconductor layer 83 is formed as a gate terminal Gsa.

In FIG. 7A, the connection relationship between each element in the light emitting chip Ca will be described.
The n-type ohmic electrode 121 that is the cathode terminal of the light-emitting thyristor L 1 of the first island 301 is connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. The p-type ohmic electrode 131 which is the gate terminal Gl1 of the light emitting thyristor L1 is connected to the n-type ohmic electrode 122 which is the cathode terminal of the connection diode Dz1 of the second island 302. Although the description is omitted, the same applies to the light emitting thyristors L2, L3, L4,.

The n-type ohmic electrode 123 that is the cathode terminal of the write thyristor M 1 of the second island 302 is connected to the write signal line 74. The write signal line 74 is connected to one terminal of a write resistor RW provided on the eleventh island 311. The other terminal of the write resistor RW is connected to the φW terminal.
One terminal of the write resistor RW is connected to one terminal of the permission resistor Rb provided on the eighth island 308. The other terminal of the permission resistor Rb is connected to the n-type ohmic electrode 128 that is the cathode terminal of the permission thyristor Sa provided on the ninth island 309. The n-type ohmic electrode 128 that is the cathode terminal of the permission thyristor Sa is connected to one terminal of the permission resistor Ra provided on the tenth island 310. The other terminal of the permission resistor Ra is connected to the φE terminal.

The n-type ohmic electrode 122 which is the cathode terminal of the connection diode Dz1 of the second island 302 is connected to the p-type ohmic electrode 133 of the power supply line resistance Rgz1 provided on the third island 303.
The p-type ohmic electrode 132 which is the gate terminal Gm1 of the write thyristor M1 of the second island 302 is connected to the p-type ohmic electrode 136 of the power supply line resistance Rgy1 provided on the third island 303. The p-type ohmic electrode 136 of the power supply line resistance Rgy1 is connected to the n-type ohmic electrode 124 that is the cathode terminal of the connection diode Dy1 provided on the fourth island 304.

The p-type ohmic electrode 135 of the power supply line resistance Rgx1 provided on the third island 303 is connected to the p-type ohmic electrode 137 that is the gate terminal Gt1 of the transfer thyristor T1 provided on the fourth island 304.
Further, the p-type ohmic electrode 134 provided on the third island 303 is connected to the Vga terminal.

The n-type ohmic electrode 125 that is the cathode terminal of the transfer thyristor T 1 provided on the fourth island 304 is connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R 1 provided on the sixth island 306.
Then, the n-type ohmic electrode 126 that is the cathode terminal of the coupling diode Dx1 provided on the fourth island 304 is connected to the p-type ohmic electrode (not indicated) that is the gate terminal Gt2 of the adjacent transfer thyristor T2. Has been.
On the other hand, the p-type ohmic electrode 137 that is the gate terminal Gt1 of the transfer thyristor T1 provided on the fourth island 304 is the n-type fourth semiconductor layer 84 that is the cathode terminal of the start diode Dx0 provided on the fifth island 305. It is connected to the n-type ohmic electrode 127 formed thereon.

The p-type ohmic electrode 138 formed on the p-type third semiconductor layer 83 that is the anode terminal of the start diode Dx0 provided on the fifth island 305 is the n-type that is the cathode terminal of the even-numbered transfer thyristor T. The n-type ohmic electrode (not indicated) formed on the fourth semiconductor layer 84 is connected to the φ2 terminal via a current limiting resistor R2 provided on the seventh island 307.
The p-type ohmic electrode 139 formed on the p-type third semiconductor layer 83 of the ninth island 309 is connected to the p-type ohmic electrode 161 formed on the p-type third semiconductor layer 83 of the third island 303. Has been.
Although not described here, the same applies to the other light emitting thyristors L, transfer thyristors T, write thyristors M, coupling diodes Dx, and connecting diodes Dy and Dz.
In this way, the circuit configuration of the light emitting chip Ca1 (Ca) shown in FIG. 6 is formed.

(Light emitting chip Cb)
FIG. 8 is an equivalent circuit diagram for explaining a circuit configuration of a light emitting chip Cb which is a self-scanning light emitting element array (SLED). In FIG. 8, except for terminals (Vga terminal, φ1 terminal, φ2 terminal, φE terminal, φW terminal, φI terminal), each element described below is a light emitting chip as described in FIG. 9 described later. Arranged based on the layout on Cb.
Here, the light emitting chip Cb will be described by taking the light emitting chip Cb1 as an example. Therefore, in FIG. 8, the light-emitting chip Cb is expressed as a light-emitting chip Cb1 (Cb). The configuration of the other light emitting chips Cb2 to Cb20 is the same as that of the light emitting chip Cb1.
Note that the positions of the terminals (Vga terminal, φ1 terminal, φ2 terminal, φE terminal, φW terminal, φI terminal) are different from those in FIG. A Vsub terminal is provided on the back surface of the substrate 80.

The light-emitting chip Cb1 (Cb) is a light-emitting chip Ca1 (Ca) described in FIG. 6, instead of the permission resistors Ra and Rb and the permission thyristor Sa (including the power supply line resistance Rga) connected to the φE terminal. The permission thyristor Sb (including the power supply line resistance Rgb) as an example of the second permission thyristor, the permission diode Ds, the permission resistor Rc as an example of the third permission resistor, and the permission resistor Rd as an example of the fourth permission resistor , A permission resistor Re as an example of a fifth permission resistor is provided.
Other configurations of the light emitting chip Cb1 (Cb) are the same as those of the light emitting chip Ca1 (Ca) shown in FIG. Therefore, in the following, in the light-emitting chip Cb1 (Cb), the parts different from the light-emitting chip Ca1 (Ca) will be described, and the same parts are denoted by the same reference numerals and detailed description thereof will be omitted.

An electrical connection of the permission thyristor Sb, the permission diode Ds, and the permission resistors Rc, Rd, and Re in the light emitting chip Cb1 (Cb) will be described.
The anode terminal of the transfer thyristor T, the anode terminal of the write thyristor M, the anode terminal of the light emitting thyristor L, and the anode terminal of the permission thyristor Sb are connected to the substrate 80 of the light emitting chip Cb1 (Cb) (anode common).
The write signal line 74 connected to the cathode terminal of the write thyristor M is connected to the φW terminal as an example of the write signal terminal via the write resistor RW on the write thyristor M1 side. In the light emitting chip Cb1, the write signal line 205 (see FIG. 4) is connected to the φW terminal, and the write signal φW1 is transmitted.
As shown in FIG. 4, write signal lines 206 to 224 are connected to φW terminals of the other light emitting chips Cb2 to Cb20, and write signals φW2 to φW20 are transmitted.

The write signal line 74 branches between the write thyristor M1 and the write resistor RW, and is connected to the anode terminal As of the permission diode Ds via the permission resistor Rc. The cathode terminal of the permission diode Ds is connected to the φE terminal as an example of the permission signal terminal. The enable signal line 203 (see FIG. 4) is connected to the φE terminal, and the enable signal φE is transmitted.
The anode terminal As of the permission diode Ds is connected to the gate terminal Gsb of the permission thyristor Sb via the permission resistor Rd. The cathode terminal of the permission diode Ds is connected to the gate terminal Gsb of the permission thyristor Sb via the permission resistor Re.
Furthermore, the cathode terminal Ksb of the permission thyristor Sb is connected to the power supply line 71 via the power supply line resistance Rgb.

The first transfer signal line 201b (see FIG. 4) is connected to the φ1 terminal of the light emitting chip Cb1 (Cb), and the first transfer signal φ1b is transmitted. The second transfer signal line 202b (see FIG. 4) is connected to the φ2 terminal, and the second transfer signal φ2b is transmitted.
Further, the lighting signal line 204b (see FIG. 4) is connected to the φI terminal of the light emitting chip Cb1 (Cb), and the lighting signal φIb is transmitted.
As shown in FIG. 4, a current limiting resistor RI is provided between the lighting signal generator 140b and the φI terminal, but the description thereof is omitted in FIG.
An anode terminal of the permission thyristor Sb may be referred to as a fifth anode terminal, a cathode terminal as a fifth cathode terminal, and a gate terminal as a fifth gate terminal.

FIG. 9 is a plan layout view and a cross-sectional view of the light emitting chip Cb. Unlike FIG. 8, FIG. 9 does not show the connection relationship with the signal generation circuit 110, and thus it is not necessary to use the light emitting chip Cb1 as an example. Therefore, in FIG. 9, the light emitting chip Cb is described. FIG. 9A is a plan layout diagram of the light emitting chip Cb, and shows a portion centering on the light emitting thyristors L1 to L4, the writing thyristors M1 to M4, and the transfer thyristors T1 to T4. FIG. 9B is a cross-sectional view taken along line IXB-IXB shown in FIG. As will be described later, the IXB-IXB line portion of FIG. 9A is the same as the VIIB-VIIB line portion of FIG. 7A. Therefore, the cross-sectional view of the light-emitting chip Cb illustrated in FIG. 9B is the same as the cross-sectional view of the light-emitting chip Ca illustrated in FIG.
9A and 9B, main elements and terminals are indicated by names. In FIG. 9A, wirings connecting the elements are indicated by solid lines except for the power supply line 71. Further, in FIG. 9B, description of wirings connecting the elements is omitted.

  As described with reference to FIG. 8, the light emitting chip Cb shown in FIG. 9 includes permission resistors Ra and Rb and a permission thyristor Sa (power supply line resistance Rga) connected to the φE terminal in the light emitting chip Ca shown in FIG. ), A permission thyristor Sb (including a power supply line resistance Rgb), a permission diode Ds, and permission resistances Rc, Rd, and Re. Therefore, the permission thyristor Sb, the permission diode Ds, and the permission resistors Rc, Rd, Re will be described below, and the same components are denoted by the same reference numerals and description thereof is omitted.

Since the light-emitting chip Cb does not include the permission resistors Ra and Rb and the permission thyristor Sa in the light-emitting chip Ca, the light-emitting chip Cb includes the eighth island 308, the ninth island 309, and the tenth island 310 in the light-emitting chip Ca illustrated in FIG. Not. Instead, the light emitting chip Cb includes a twelfth island 312, a thirteenth island 313, a fourteenth island 314, and a fifteenth island 315, as shown in FIG.
The twelfth island 312 is provided with a permission thyristor Sb. The thirteenth island 313 is provided with a permission diode Ds and a permission resistor Rc. The fourteenth island 314 is provided with a permission resistor Rd, and the fifteenth island 315 is provided with a permission resistor Re.
Therefore, the first island 301, the second island 302, the third island 303, the fourth island 304, the fifth island 305, the sixth island 306, and the seventh island 307 in the light emitting chip Cb shown in FIG. The same as the first island 301, the second island 302, the third island 303, the fourth island 304, the fifth island 305, the sixth island 306, and the seventh island 307 in the light emitting chip Ca shown. Therefore, the cross-sectional view taken along line IXB-IXB shown in FIG. 9B is the same as the cross-sectional view taken along line VIIB-VIIB shown in FIG.

The permission thyristor Sb provided on the twelfth island 312 has a p-type exposed by removing the n-type fourth semiconductor layer 84 using the n-type ohmic electrode 151 on the n-type fourth semiconductor layer 84 as a cathode terminal. The p-type ohmic electrode 162 formed on the third semiconductor layer 83 is configured as a gate terminal Gsb.
The permission diode Ds provided on the thirteenth island 313 has the n-type ohmic electrode 152 on the n-type fourth semiconductor layer 84 as a cathode terminal and the p-type exposed by removing the n-type fourth semiconductor layer 84. The p-type ohmic electrode 163 formed on the third semiconductor layer 83 is configured as an anode terminal As. The permission resistor Rc is between the p-type ohmic electrode 163 and the p-type ohmic electrode 164 formed on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84. The p-type third semiconductor layer 83 is used as a resistor.
The permission resistor Rd provided on the fourteenth island 314 and the permission resistor Re provided on the fifteenth island 315 are the p-type third semiconductor layer 83 as in the case of the current limiting resistors R1, R2 or the write resistor RW. A p-type third semiconductor layer 83 between a pair of p-type ohmic electrodes provided above is configured as a resistor.
Note that the power supply line resistance Rga in the light emitting chip Ca shown in FIG. 7 is the power supply line resistance Rgb in the light emitting chip Cb in FIG.

Next, in FIG. 9A, the connection relationship between the permission thyristor Sb, the permission diode Ds, and the permission resistors Rc, Rd, and Re will be described.
Also in the light emitting chip Cb, similarly to the light emitting chip Ca, the n-type ohmic electrode 123 on the n-type fourth semiconductor layer 84 which is the cathode terminal of the write thyristor M1 is connected to the write signal line 74. The write signal line 74 is connected to a p-type ohmic electrode (no symbol) that is one terminal of the write resistor RW provided on the eleventh island 311. A p-type ohmic electrode (no symbol) which is the other terminal of the write resistor RW is connected to the φW terminal.
The write signal line 74 is connected to the p-type ohmic electrode 164 which is one terminal of the permission resistor Rc provided on the thirteenth island 313. The p-type ohmic electrode 163 that is the other terminal of the permission resistor Rc is connected to the p-type ohmic electrode (not shown) that is one terminal of the permission resistor Rd provided on the fourteenth island 314. The p-type ohmic electrode (not shown) which is the other terminal of the permission resistor Rd is connected to the p-type ohmic electrode 162 which is the gate terminal Gsb of the permission thyristor Sb provided on the twelfth island 312. Further, the p-type ohmic electrode 162 that is the gate terminal Gsb of the permission thyristor Sb is connected to the p-type ohmic electrode (not indicated) that is one terminal of the permission resistor Re provided on the fifteenth island 315. A p-type ohmic electrode (unsigned) which is the other terminal of the enabling resistor Re is connected to the φE terminal. In addition, the p-type ohmic electrode (not labeled) that is the other terminal of the permission resistor Re is connected to the n-type ohmic electrode 152 that is the cathode terminal of the permission diode Ds provided on the thirteenth island 313. The p-type ohmic electrode 163 that is the anode terminal of the permission diode Ds also serves as the other terminal of the permission resistor Rc.
The n-type ohmic electrode 151 that is the cathode terminal Ksb of the permission thyristor Sb provided on the twelfth island 312 is the p-type ohmic electrode 161 that is one terminal of the power supply line resistance Rgb provided on the branch of the third island 303. It is connected to the.
The p-type ohmic electrode 134 which is the other terminal of the power supply line resistance Rgb constitutes the power supply line 71 and is connected to the Vga terminal.
As described above, the circuit configuration of the light emitting chip Cb1 (Cb) shown in FIG. 8 is formed.

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
The light emitting device 65 includes light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a and light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b (see FIGS. 3, 4, and 5).
As shown in FIG. 4, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 on the circuit board 62.
Further, the permission signal φE is transmitted in common to all the light emitting chips Ca1 to Ca20 and the light emitting chips Cb1 to Cb20 on the circuit board 62.

The first transfer signal φ1a, the second transfer signal φ2a, and the lighting signal φIa are transmitted in common to the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a. Therefore, the light emitting chips Ca1 to Ca20 belonging to the light emitting chip group #a are driven in parallel.
Similarly, the first transfer signal φ1b, the second transfer signal φ2b, and the lighting signal φIb are transmitted in common to the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b. Therefore, the light emitting chips Cb1 to Cb20 belonging to the light emitting chip group #b are driven in parallel.

  On the other hand, the write signals φW1 to φW20 (φW) are light emitting chip groups # 1 to # 20 formed by one light emitting chip Ca belonging to the light emitting chip group #a and one light emitting chip Cb belonging to the light emitting chip group #b. Are transmitted in common to each of these. For example, the write signal φW1 is transmitted in common with the light emitting chip Ca1 belonging to the light emitting chip group #a and the light emitting chip Cb1 belonging to the light emitting chip group #b as the light emitting chip set # 1. Also, the 20 write signals φW1 to φW20 are transmitted at the same timing. Therefore, the light emitting chip sets # 1 to # 20 are driven in parallel.

As described above, the light emitting chips Ca2 to Ca20 belonging to the light emitting chip group #a are driven in parallel with the light emitting chip Ca1, and the light emitting chips Cb2 to Cb20 of the light emitting chip group #b are driven in parallel to the light emitting chip Cb1. Therefore, it is sufficient to describe the operations of the light emitting chips Ca1 and Cb1 belonging to the light emitting chip set # 1. The light emitting chips Ca1 and Cb1 constitute the light emitting chip set # 1, and the light emitting chip sets # 2 to # 20 are driven in parallel with the light emitting chip set # 1, and thus constitute the light emitting chip set # 1. It is sufficient to describe the light emitting chips Ca1 and Cb1.
In the above description, the write signals φW1 to φW20 are transmitted at the same timing. However, as will be described later, the write signals φW1 to φW20 may be transmitted at different timings.

<Thyristor operation>
Before describing the operations of the light emitting chips Ca1 and Cb1, the basic operations of the thyristors (transfer thyristor T, writing thyristor M, light emitting thyristor L, permission thyristors Sa, Sb) will be described. As described above, the thyristor is a semiconductor element having three terminals: an anode terminal, a cathode terminal, and a gate terminal.
Hereinafter, as an example, the reference potential Vsub supplied to the Vsub terminal which is the anode terminal of the thyristor is set to 0 V (high level potential “H”) as shown in FIGS. 6, 7, 8, and 9. And the power supply potential Vga supplied to the Vga terminal is −3.3 V (a low-level potential and expressed as “L”). As shown in FIGS. 7 and 9, the thyristor is formed by stacking a p-type semiconductor layer and an n-type semiconductor layer made of a compound semiconductor such as GaAs or GaAlAs. Directional potential) Vd is set to 1.5V.

An off-state thyristor with a small current flowing between the anode terminal and the cathode terminal is turned on (turned on) when a potential lower than the threshold voltage (a negative potential having a large absolute value) is supplied to the cathode terminal. . When the thyristor is turned on, the current flowing between the anode terminal and the cathode terminal is larger than that in the off state (on state). Here, the threshold voltage of the thyristor is the gate terminal (gate terminal Gt in the transfer thyristor T, gate terminal Gm in the write thyristor M, gate terminal Gl in the light emitting thyristor L, gate terminal Gsa in the enable thyristor Sa, and in the enable thyristor Sb. This is a value obtained by subtracting the diffusion potential Vd from the potential of the gate terminal Gsb). For example, if the potential of the gate terminal of the thyristor is −1.5V, the threshold voltage is −3V. That is, when a voltage lower than −3V, for example, −3.3V that is “L” is transmitted to the cathode terminal, the thyristor is turned on.
In the thyristor in the on state, the gate terminal has a potential close to the potential of the anode terminal of the thyristor. In the following description, since the anode terminal is set to 0V (“H”), the potential of the gate terminal of the on-state thyristor is assumed to be 0V (“H”). Further, the cathode terminal of the thyristor in the on state has a value close to the pn junction diffusion potential Vd. Here, description is made assuming that the potential of the cathode terminal is −1.7 V.

The thyristor in the on state continues to maintain the on state if the potential of the cathode terminal is a potential necessary to maintain the on state. On the other hand, when the potential becomes higher (a negative potential having a small absolute value or a positive potential) than the potential necessary for maintaining the on state, the state is turned off (turned off).
That is, since the potential of the cathode terminal of the on-state thyristor is −1.7 V as described above, the on-state thyristor is continuously applied with a potential lower than −1.7 V to the cathode terminal. When a current that can be maintained is supplied, the ON state is maintained.
On the other hand, the on-state thyristor is turned off when a potential higher than −1.7 V is applied to the cathode terminal.
In the following description, the potential of the cathode terminal of the thyristor in the on state may be set to “H” (0 V) to turn off the thyristor. “H” (0 V) is the potential of the cathode terminal of the thyristor in the on state. While the potential is higher than a certain −1.7 V, the thyristor is turned off when the cathode terminal becomes the same potential as the anode terminal.

  From the above, the thyristor maintains a state where current flows when it is turned on, and does not shift to the off state even when the potential of the gate terminal is changed. That is, the thyristor has a function of maintaining (storing and holding) the on state.

As described above, -1.7V, which is a potential that is continuously applied to the cathode terminal in order to maintain the thyristor in the on state, is the threshold voltage of the thyristor when the potential of the gate terminal is -1.5V. The potential is higher than 3V.
The light-emitting thyristor L is turned on (emits light) when turned on, and turned off (not lit) when turned off. The light emission output (light quantity) of the light emitting thyristor L in the on state is determined by the current flowing between the cathode terminal and the anode terminal.

<Potential of write signal line 74>
Next, regarding the light emitting chips Ca and Cb, the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line 74 (φWL (Ca)) will be described.
First, the light emitting chip Ca will be described.
FIG. 10 is a diagram for explaining the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line 74 (φWL (Ca)) in the light emitting chip Ca. FIG. 10A shows an equivalent circuit of the light emitting chip Ca1 (Ca) shown in FIG. This is an equivalent circuit in which Rga and write resistance RW are extracted. FIG. 10B is a diagram showing the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line 74 (φWL (Ca)).
The relationship between the potential (φE) and the potential (φW) of the φE terminal and the potential (φWL (Ca)) of the write signal line 74 shown in FIG. The resistance value is 1 kΩ, the resistance value of the write resistor RW is 2 kΩ, and the resistance value of the power supply line resistance Rga is 20 kΩ. In FIG. 10B, φWL (Ca) is shown by rounding off two decimal places.

Here, a case is considered where all of the write thyristors M (see FIG. 6) whose cathode terminals are connected to the write signal line 74 are in the OFF state. That is, the potential of the write signal line 74 is determined by the potentials of φE and φW without being affected by the write thyristor M.
The permission signal φE transmitted to the φE terminal is described as “H” (0 V), a first potential level (hereinafter referred to as “E1”), and a second potential level (hereinafter referred to as “E2”). ) And three potential levels. As an example, “E1” is set to −L, which is “L”, and “E2” is set to −5.3V.
On the other hand, the write signal φW is a signal having two potential levels of “H” (0 V) and “L” (−3.3 V).

  As shown in FIG. 10A, the gate terminal Gsa of the permission thyristor Sa is connected to the power supply line 71 via the power supply line resistance Rga and supplied with the power supply potential Vga (-3.3V of “L”). Yes. Therefore, the threshold voltage of the permission thyristor Sa is −4.8 V obtained by subtracting the diffusion potential Vd (−1.5 V) of the pn junction from the potential of the gate terminal Gsa. That is, the permission thyristor Sa in the off state is turned on when a potential lower than −4.8V (≦ −4.8V) is applied to the cathode terminal Ksa. On the other hand, the permission thyristor Sa in the off state does not turn on even when a potential higher than −4.8V (> −4.8V) is applied to the cathode terminal Ksa, and maintains the off state.

In FIG. 10B, when φW is “H” (0 V) and φE is “H” (0 V), the threshold voltage is −4.8 V because the cathode terminal Ksa of the permission thyristor Sa is also 0 V. The permission thyristor Sa cannot be turned on and is in an off state. Therefore, φWL (Ca) is also “H” (0 V).
Next, when φW is “H” (0 V) and φE is “E1” (−3.3 V), the cathode terminal Ksa of the permission thyristor Sa is changed from “H” (0 V) to “E1” (− At the timing of shifting to 3.3V), it becomes −3.3V. However, the permission thyristor Sa having the threshold voltage of −4.8V cannot be turned on and is in the off state. Therefore, φWL (Ca) is obtained by dividing the potential difference between φW of “H” (0V) and φE of “E1” (−3.3V) by the enable resistors Ra and Rb and the write resistor RW, and −1. .7V.
Further, when φW is “H” (0 V) and φE is “E2” (−5.3 V), the cathode terminal Ksa of the permission thyristor Sa has φE changed from “H” (0 V) to “E2” (−5). .−3V) at the timing of transition to .3V). Then, the permission thyristor Sa having a threshold voltage of −4.8 V is turned on and turned on. As a result, the potential of the cathode terminal Ksa of the permission thyristor Sa becomes −1.7V. Therefore, φWL (Ca) is a potential obtained by dividing the potential difference between φW of “H” (0 V) and the cathode terminal Ksa of −1.7 V by the permission resistor Rb and the write resistor RW−0. 6V.

On the other hand, in FIG. 10B, when φW is “L” (−3.3 V) and φE is “H” (0 V), the permission thyristor Sa with the threshold voltage of −4.8 V cannot be turned on. In the off state. Therefore, φWL (Ca) is a potential obtained by dividing the potential difference between φW of “L” (−3.3 V) and φE of “H” (0 V) by the enable resistors Ra and Rb and the write resistor RW. It will be -1.7V.
Next, when φW is “L” (−3.3V) and φE is “E1” (−3.3V), as described above, the permission thyristor Sa having the threshold voltage of −4.8V is turned on. Cannot be in the off state. φWL (Ca) is −3.3V because φW and φE are both −3.3V.
Further, when φW is “L” (−3.3 V) and φE is “E2” (−5.3 V), the permission thyristor Sa is turned on and turned on as described above. As a result, the potential of the cathode terminal Ksa of the permission thyristor Sa becomes −1.7V. Therefore, φWL (Ca) is a potential obtained by dividing the potential difference between φW of “L” (−3.3 V) and the cathode terminal Ksa of −1.7 V by the permission resistor Rb and the write resistor RW. -2.2V.

As described above, in the light emitting chip Ca, when φE is “E1” (−3.3 V) and φW is “L” (−3.3 V), φWL (Ca) is “L” (−3. 3V). That is, as will be described later, the light emitting chip Ca is permitted to be turned on when φE becomes “E1” (−3.3 V), and turned on (light emission) when φW becomes “L” (−3.3 V). To do.
In addition, when φW is “L” (−3.3 V) and φE is “H” (0 V), it does not appear in the operation of the light emitting device 65 described later.

Now, the light emitting chip Cb will be described.
FIG. 11 is a diagram for explaining the relationship between the potential (φE) and the potential (φW) of the φE terminal and the potential (φWL (Cb)) of the write signal line 74 in the light emitting chip Cb. FIG. 11A shows an equivalent circuit of the light emitting chip Cb1 (Cb) shown in FIG. , Re, and write resistance RW are equivalent circuits shown. FIG. 11B is a diagram showing the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line 74 (φWL (Cb)).
Note that the relationship between the potential (φE) of the φE terminal and the potential (φW) of the φW terminal and the potential (φWL (Cb)) of the write signal line 74 shown in FIG. The resistance value of the resistor RW is 2 kΩ, the resistance value of the permission resistor Rd is 4 kΩ, the resistance value of the permission resistor Re is 20 kΩ, and the resistance value of the power line resistance Rgb is 2 kΩ. In FIG. 11B, φWL (Cb) is shown by rounding off two decimal places.

As can be seen from FIG. 11A, the gate terminal Gsb of the permission thyristor Sb is connected to the cathode terminal of the permission diode Ds via the permission resistor Re and to the φE terminal. The gate terminal Gsb of the permission thyristor Sb is connected to the anode terminal As of the permission diode Ds via the permission resistor Rd, and is further connected to the write signal line 74 via the permission resistor Rc. The write signal line 74 is connected to the φW terminal via the write resistor RW.
The cathode terminal Ksb of the permission thyristor Sb is connected to the power supply line 71 via the power supply line resistance Rgb, and is supplied with the power supply potential Vga (“L” of −3.3 V). The permission thyristor Sb has a threshold voltage higher than −3.3V (≧ −3.3V) when the potential of the gate terminal Gsb becomes higher than −1.8V (≧ −1.8V). Turn on.
As will be described later, in the initial state in which the light emitting device 65 is in the operating state, the Vga terminal is set to “L” (−3.3 V), and the φE terminal (φE) and the φW terminal (φW) are “H”. Set to (0V). When φE and φW become “H” (0 V), the potential of the gate terminal Gsb also becomes “H” (0 V), so that the threshold voltage of the permission thyristor Sb becomes −1.5 V, which is higher than −3.3 V. As a result, the permission thyristor Sb is turned on. The permission thyristor Sb continues to maintain the ON state because the power supply potential Vga (−3.3 V) is supplied to the cathode terminal Ksb. As a result, the potential of the gate terminal Gsb of the permission thyristor Sb becomes “H” (0 V).

In FIG. 11B, first, when φW is “H” (0 V) and φE is “H” (0 V), the potentials of φE and φW and the gate terminal Gsb are “H” (0 V). (Cb) also becomes “H” (0 V).
Next, when φW is “H” (0V) and φE is “E1” (−3.3V), the cathode terminal of the permission diode Ds is −3.3V, and the anode terminal As is close to 0V. Therefore, the pn junction is biased in the forward direction (forward bias). As a result, the permission diode Ds generates a potential difference of −1.5 V that is the diffusion potential Vd of the pn junction. The potential of the anode terminal As is −1.4 V when determined in consideration of the resistance of the on-state permission thyristor Sb and the forward bias permission diode Ds. Therefore, φWL (Cb) becomes −0.6 V by dividing the potential difference between φH of “H” (0 V) and the anode terminal As of −1.4 V by the enable resistor Rc and the write resistor RW.
Further, when φW is “H” (0 V) and φE is “E2” (−5.3 V), the enabling diode Ds is forward biased, and the potential of the anode terminal As of the enabling diode Ds is in the ON state. It is -3.3 V when it is determined in consideration of the resistance of the permission thyristor Sb and the forward bias permission diode Ds. Therefore, φWL (Cb) is −1.5 V, because the potential difference between φW of “H” (0 V) and the anode terminal As of −3.3 V is divided by the permission resistor Rc and the write resistor RW. .

On the other hand, in FIG. 11B, when φW is “L” (−3.3 V) and φE is “H” (0 V), the potential of the cathode terminal of the permission diode Ds is 0 V and the potential of the anode terminal As. Is a potential close to 0V, so that the pn junction is biased in the reverse direction (reverse bias). Therefore, φWL (Cb) is −1.7V obtained by dividing the potential difference between φW of “L” (−3.3V) and the gate terminal Gsb of 0V by the permission resistors Rd and Rc and the write resistor RW. Become.
Next, when φW is “L” (−3.3 V) and φE is “E1” (−3.3 V), as described above, the permission diode Ds has a cathode terminal of −3.3 V and an anode terminal As. Becomes a forward bias of -1.4V. Therefore, φWL (Cb) is −2.5 V, because the potential difference between φW of “L” (−3.3 V) and the anode terminal As of −1.4 V is divided by the permission resistor Rc and the write resistor RW. It becomes.
Further, when φW is “L” (−3.3 V) and φE is “E2” (−5.3 V), as described above, the permission diode Ds is forward biased, and the potential of the anode terminal As is -3.3V. Therefore, since φW and the anode terminal As are both −3.3V, φWL (Cb) is −3.3V.

As described above, in the light-emitting chip Cb, when φE is “E2” (−5.3 V) and φW is “L” (−3.3 V), φWL (Cb) is “L” (−3. 3V). That is, as will be described later, the light-emitting chip Cb is allowed to light when φE becomes “E2” (−5.3 V), and lighted (light emission) when φW becomes “L” (−3.3 V). To do.
Note that a state where φW is “L” (−3.3 V) and φE is “H” (0 V) does not appear in the operation described later.

FIG. 12 shows the relationship between the potential of the φE terminal (φE) and the potential of the φW terminal (φW) and the potential of the write signal line 74 (φWL (Ca) and φWL (Cb)) for the light emitting chips Ca and Cb. It is a timing chart which shows.
In FIG. 12, it is assumed that time elapses from time t1 to time t9 in numerical order.
ΦE is “H” (0 V) from time t1 to time t2, and shifts from “H” (0 V) to “E1” (−3.3 V) at time t2. Then, at time t5, the process shifts from “E1” (−3.3V) to “E2” (−5.3V). Then, at time t8, “E2” (−5.3V) shifts to “H” (0V), and “H” (0V) is maintained until time t9.
On the other hand, φW is “H” (0 V) from time t1 to time t3, and shifts from “H” (0 V) to “L” (−3.3 V) at time t3. At time t4, “L” (−3.3V) is shifted to “H” (0V), and at time t6, “H” (0V) is shifted to “L” (−3.3V). At time t7, the shift is made from “L” (−3.3 V) to “H” (0 V). Then, “H” (0 V) is maintained until time t9.

First, the potential (φWL (Ca)) of the write signal line 74 of the light emitting chip Ca will be described with reference to FIG.
From time t1 to time t2, since φE and φW are both “H” (0 V), φWL (Ca) is “H” (0 V). From time t2 to time t3, since φE is “E1” (−3.3V) and φW is “H” (0V), φWL (Ca) is −1.7V. From time t3 to time t4, since φE is “E1” (−3.3V) and φW is “L” (−3.3V), φWL (Ca) is −3.3V. From time t4 to time t5, since φE is “E1” (−3.3V) and φW is “H” (0V), φWL (Ca) returns to −1.7V.
On the other hand, from time t5 to time t6, since φE is “E2” (−5.3V) and φW is “H” (0V), φWL (Ca) is −0.6V. As described above, at time t5, the permission thyristor Sa is turned on and turned on. From time t6 to time t7, since φE is “E2” (−5.3V) and φW is “L” (−3.3V), φWL (Ca) is −2.2V. Also at this time, the permission thyristor Sa maintains the on state. From time t7 to time t8, since φE is “E2” (−5.3V) and φW is “L” (−3.3V), φWL (Ca) returns to −0.6V. Also at this time, the permission thyristor Sa maintains the on state.
From time t8 to time t9, both φE and φW are “H” (0 V), so φWL (Ca) returns to “H” (0 V). At time t8, the permission thyristor Sa is turned off because the potential of the cathode terminal Ksa becomes the same “H” (0 V) as the potential of the anode terminal.

Next, the potential (φWL (Cb)) of the write signal line 74 of the light emitting chip Cb will be described with reference to FIG.
It is assumed that the power supply potential Vga (“L” (−3.3 V)) is supplied at time t1. Since both φE and φW are “H” (0 V), the permission thyristor Sb is turned on, and the potential of the gate terminal Gsb is set to “H” (0 V). The permission thyristor Sb is kept on while the power supply potential Vga (“L” (−3.3 V)) is supplied.
From time t1 to time t2, since φE and φW are both “H” (0 V), φWL (Cb) is “H” (0 V). From time t2 to time t3, since φE is “E1” (−3.3V) and φW is “H” (0V), φWL (Cb) is −0.6V. From time t3 to time t4, since φE is “E1” (−3.3V) and φW is “L” (−3.3V), φWL (Cb) is −2.5V. From time t4 to time t5, since φE is “E1” (−3.3V) and φW is “H” (0V), φWL (Cb) returns to −0.6V.
On the other hand, from time t5 to time t6, φE is “E2” (−5.3 V) and φW is “H” (0 V), so φWL (Cb) is −1.5 V. From time t6 to time t7, since φE is “E2” (−5.3 V) and φW is “L” (−3.3 V), φWL (Cb) is −3.3 V. From time t7 to time t8, since φE is “E2” (−5.3V) and φW is “L” (−3.3V), φWL (Cb) returns to −1.5V.
From time t8 to time t9, both φE and φW are “H” (0 V), so φWL (Cb) returns to “H” (0 V).
The permission thyristor Sb is turned on at time t1 and is kept on at time t9.

As described above, it can be seen that the combinations of φE and φW that φWL (Ca) or φWL (Cb) becomes “L” (−3.3 V), that is, the timings are different.
When φWL (Ca) is φE is “E1” (−3.3V) and φW is “L” (−3.3V), φWL (Cb) is φE is “E2” (−5.3V) ), When φW is “L” (−3.3 V), it becomes “L” (−3.3 V). That is, the potential (φE) of the φE terminal at the timing when the potential of the φW terminal changes from “H” (0 V) to “L” (−3.3 V) is “E1” (−3.3 V) or “E2” (− The light emitting chip Ca or Cb can be selected and allowed to be lit, as will be described later, depending on whether the voltage is at 5.3V).
The potentials of “H”, “L”, “E1”, “E2” and the resistance values of the permission resistors Ra, Rb, Rc, Rd, Re, and the power supply line resistors Rga, Rgb are only examples. Other values may be used.

FIG. 13 is a timing chart for explaining the operation of the light-emitting device 65 in the first embodiment. FIG. 13 shows a timing chart for explaining the operation of the light emitting chip set # 2 (light emitting chips Ca2 and Cb2) in addition to the light emitting chip set # 1 (light emitting chips Ca1 and Cb1). FIG. 13 shows a timing chart of a portion for controlling lighting or non-lighting of the four light emitting thyristors L1 to L4 in each of the light emitting chips Ca1, Cb1, Ca2, and Cb2.
In the following, controlling lighting or non-lighting of the light emitting thyristor L is referred to as lighting control.

In the light emitting chip set # 1 (light emitting chips Ca1 and Cb1), all the light emitting thyristors L1 to L4 are turned on. In the light emitting chip set # 2 (light emitting chips Ca2 and Cb2), the light emitting thyristors L2, L3, and L4 of the light emitting chip Ca2 are turned on, and the light emitting thyristors L1, L3, and L4 of the light emitting chip Cb2 are turned on. The light emitting thyristor L1 of the light emitting chip Ca2 and the light emitting thyristor L2 of the light emitting chip Cb2 were not lit.
However, below, it demonstrates focusing on operation | movement of light emitting chip | tip Ca1 and Cb1.

In FIG. 13, it is assumed that time elapses in alphabetical order from time a to time y. The light-emitting thyristor L1 of the light-emitting chip Ca1 belonging to the light-emitting chip group #a is controlled to be turned on during a period Ta (1) from time c to time o. The light-emitting thyristor L2 of the light-emitting chip Ca1 is controlled to be turned on during a period Ta (2) from time o to time u. The light-emitting thyristor L3 of the light-emitting chip Ca1 is controlled to be turned on during a period Ta (3) from time u to time w. The light-emitting thyristor L4 of the light-emitting chip Ca1 is controlled to be turned on during a period Ta (4) from time w to time y. Thereafter, the light-emitting thyristor L having a number of 5 or more is similarly controlled to be turned on.
On the other hand, the light-emitting thyristor L1 of the light-emitting chip Cb1 of the light-emitting chip group #b is controlled to be lit during a period Tb (1) from time h to time r. The light-emitting thyristor L2 of the light-emitting chip Cb1 is controlled to be turned on during a period Tb (2) from time r to time v. The light-emitting thyristor L3 of the light-emitting chip Cb1 is controlled to be turned on during a period Tb (3) from time v to time x. Thereafter, the light emitting thyristor L having a number of 4 or more is similarly controlled to be turned on.

In this embodiment, the periods Ta (1), Ta (2), Ta (3),... And the periods Tb (1), Tb (2), Tb (3),. When not distinguished from each other, it is expressed as a period T.
Then, the periods Ta (1), Ta (2), Ta (3),... For controlling the light emitting chips Ca (light emitting chips Ca1 to Ca20) belonging to the light emitting chip group #a, and the light emitting chips belonging to the light emitting chip group #b. The period Tb (1), Tb (2), Tb (3),... For controlling Cb (light emitting chips Cb1 to Cb20) is shifted by half the length of the period T (180 ° in terms of phase). To do. That is, the period Tb (1) starts when a period ½ of the period T elapses after the period Ta (1) starts.
Therefore, hereinafter, the periods Ta (1), Ta (2), Ta (3),... For controlling the light emitting chip Ca1 belonging to the light emitting chip group #a will be described.
Note that the length of the period T may be variable as long as the mutual relationship of signals described below is maintained.

The signal waveforms in the periods Ta (1), Ta (2), Ta (3),... Are the same waveforms except for the write signal φW (φW1 to φW20) that changes depending on the image data.
Note that the period from time a to time c is a period in which the light emitting chip Ca1 (C) starts operating. The signal in this period will be described in the description of the operation.

The signal waveforms of the first transfer signal φ1a and the second transfer signal φ2a in the period Ta (1) and the period Ta (2) will be described. The first transfer signal φ1a and the second transfer signal φ2a are transmitted in common to the light emitting chips Ca belonging to the light emitting chip group #a.
The first transfer signal φ1a is “L” (−3.3V) at the start time c of the period Ta (1), and shifts from “L” (−3.3V) to “H” at the time m. “H” is maintained at the end time o of the period Ta (1) (start time o of the period Ta (2)). Then, the time shifts from “H” to “L” at time s, and “L” is maintained at the end time u of the period Ta (2).
The second transfer signal φ2a is “H” (0V) at the start time c of the period Ta (1), and transitions from “H” to “L” (−3.3V) at the time l. “L” is maintained at the end time o of 1) (start time o of the period Ta (2)). Then, it shifts from “L” to “H” (0 V) at time t, and maintains “H” at the end time u of the period Ta (2).

Here, when the first transfer signal φ1a and the second transfer signal φ2a are compared, the waveform of the first transfer signal φ1a in the period Ta (1) becomes the waveform of the second transfer signal φ2a in the period Ta (2). Yes. The waveform of the second transfer signal φ2a in the period Ta (1) is the waveform of the first transfer signal φ1a in the period Ta (2).
That is, the first transfer signal φ1a and the second transfer signal φ2a are signal waveforms that repeat in units of a period (2T) that is twice the period T. Then, like the period from time l to time m, both “H” (0 V) and “L” (−3.3 V) are alternately sandwiched between periods “L” (−3.3 V). Is repeated. Except for the period from time a to time b, the first transfer signal φ1 and the second transfer signal φ2 do not have a period of “H” (0 V) at the same time.
The transfer thyristor T of the light-emitting chip Ca1 shown in FIG. 6 is sequentially turned on and turned on or off by a set of transfer signals of the first transfer signal φ1a and the second transfer signal φ2a, as will be described later. A light-emitting thyristor L that is a lighting control target (lighting control) is designated.
Note that the first transfer signal φ1b and the second transfer signal φ2b transmitted in common to the light-emitting chips Cb belonging to the light-emitting chip group #b are divided into the first transfer signal φ1a and the second transfer signal φ2a, respectively, as described above. It is shifted backward on the time axis for a period of 1/2 of T. Since the period of the first transfer signal φ1a and the second transfer signal φ2a, the first transfer signal φ1b and the second transfer signal φ2b is 2T, the first transfer signal φ1a, the second transfer signal φ2a, the first transfer signal φ1b, The phase of the second transfer signal φ2b is shifted by 90 °.

In the period Ta (1), the lighting signal φIa will be described. The lighting signal φIa is transmitted in common to the light emitting chips Ca belonging to the light emitting chip group #a.
The lighting signal φIa shifts from “H” (0 V) to “L” (−3.3 V) at the start time c of the period Ta (1), and shifts from “L” to “H” at time n. . Then, “H” is maintained at the end time o of the period Ta (1). The lighting signal φIa repeats the signal waveform in the period Ta (1) in the periods Ta (2), Ta (3), Ta (4),.
The lighting signal φIa is a signal for supplying a current for lighting (light emission) to the light emitting thyristor L as described later.
Note that the lighting signal φIb transmitted in common to the light-emitting chips Cb belonging to the light-emitting chip group #b is shifted backward on the time axis for the period of ½ of the period T, as described above. . That is, since the lighting signals φIa and φIb have a period of T, the phases are shifted by 180 °.

In the period Ta (1), the permission signal φE will be described. The permission signal φE is transmitted in common to all the light emitting chips Ca (light emitting chips Ca1 to Ca20) and the light emitting chips Cb (light emitting chips Cb1 to Cb20) regardless of the light emitting chip groups #a and #b.
The permission signal φE is “H” (0V) at the start time c of the period Ta (1), and transitions from “H” (0V) to “E1” (−3.3V) at time d, and at time i. Then, shift to “E2” (−5.3V). Then, at the end time o of the period Ta (1) (start time o of the period Ta (2)), the shift is made from “E2” (−5.3 V) to “H” (0 V).
The permission signal φE in the period Ta (1) corresponds to the waveform from time t1 to time t8 shown in FIG. And the permission signal φE repeats the signal waveform in the period Ta (1) in the periods Ta (2), Ta (3), Ta (4),.
The permission signal φE is a signal that permits (enables) the light-emitting chip Ca and the light-emitting chip Cb to light up, as will be described in detail later.

Next, the write signal φW1 will be described in the period Ta (1). Write signal φW1 is transmitted in common to light emitting chips Ca1 and Cb1 constituting light emitting chip set # 1.
The write signal φW1 is “H” (0 V) at the start time c of the period Ta (1), transitions from “H” to “L” (−3.3 V) at time e, and “ Transition from “L” to “H”. Furthermore, the transition is from “H” to “L” at time j, and from “L” to “H” at time k. Then, “H” is maintained at the end time o of the period Ta (1).
That is, the write signal φW1 has two periods of “L” in the period Ta (1).
Looking at the relationship between the write signal φW1 and the permission signal φE, in the period Ta (1), during the period (time e to time f) when the write signal φW1 first becomes “L”, the permission signal φE is It is included in the period from time d to time i, which is “E1” (−3.3 V). In the period Ta (1), the period (from time j to time k) when the write signal φW1 becomes “L” later is from time i to time o when the permission signal φE is “E2” (−5.3 V). Included in the period.
In the period Ta (1), the period (time e to time f) in which the write signal φW1 first becomes “L” is included in the period Ta (1) from time c to time o. A period (time j to time k) in which φW1 becomes “L” later is included in a period Tb (1) from time h to time r.

  As will be described later, in a period (time e to time f) when the write signal φW1 is initially “L”, a signal for lighting (light-emitting) the light-emitting thyristor L1 of the light-emitting chip Ca1 belonging to the light-emitting chip group #a. It is. The period (time j to time k) when the write signal φW1 is later “L” is a signal for turning on (emitting) the light emitting thyristor L1 of the light emitting chip Cb1 of the light emitting chip group #b.

Now, the operation of the light emitting device 65 will be described according to the timing chart shown in FIG. 13 with reference to FIGS. 4, 6, 8, 10, 11, and 12.
(1) Time a
A state (initial state) at time a when the supply of the reference potential Vsub and the power supply potential Vga to the light emitting device 65 is started will be described.
<Light emitting device 65>
At time a in the timing chart shown in FIG. 13, the power supply line 200a is set to the reference potential Vsub of “H” (0V), and the power supply line 200b is set to the power supply potential Vga of “L” (−3.3V). (See FIG. 4). Therefore, the Vsub terminals of all the light emitting chips Ca and Cb are set to “H”, and the respective Vga terminals are set to “L” (see FIGS. 6 and 8).

  The transfer signal generation unit 120a of the signal generation circuit 110 sets the first transfer signal φ1a and the second transfer signal φ2a to “H”, and the transfer signal generation unit 120b sets the first transfer signal φ1b and the second transfer signal φ2b, respectively. Set to “H”. Then, the first transfer signal lines 201a and 201b and the second transfer signal lines 202a and 202b become “H” (see FIG. 4). As a result, the φ1 terminal and φ2 terminal of each of the light emitting chip Ca and the light emitting chip Cb become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIGS. 6 and 8).

Further, the permission signal generation unit 130 of the signal generation circuit 110 sets the permission signal φE to “H”. Then, the permission signal line 203 becomes “H” (see FIG. 4). As a result, the φE terminals of the light-emitting chip Ca and the light-emitting chip Cb become “H” (see FIGS. 6 and 8).
Furthermore, the lighting signal generator 140a of the signal generation circuit 110 sets the lighting signal φIa to “H”, and the lighting signal generator 140b sets the lighting signal φIb to “H”. Then, the lighting signal lines 204a and 204b become “H” (see FIG. 4). As a result, the φI terminals of the light emitting chip Ca and the light emitting chip Cb become “H”. The lighting signal line 75 connected to the φI terminal also becomes “H” (see FIGS. 6 and 8).

Write signal generation unit 150 of signal generation circuit 110 sets write signals φW1 to φW20 to “H”. Then, the write signal lines 205 to 224 become “H” (see FIG. 4). As a result, the φW terminals of the light emitting chip Ca and the light emitting chip Cb become “H” (see FIGS. 6 and 8).
In FIG. 13 and the following description, it is assumed that the potential of each terminal changes stepwise, but the potential of each terminal gradually changes. Therefore, even during the potential change, if the following conditions are satisfied, the thyristor changes its state such as turn-on and turn-off.

Next, operations of the light emitting chip Ca and the light emitting chip Cb will be described focusing on the light emitting chips Ca1 and Cb1 belonging to the light emitting chip set # 1.
<Light emitting chip Ca1>
Since the φE terminal and the φW terminal are “H”, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) is “H” (0 V) as shown in FIG. It has become.
Since the anode terminals of the transfer thyristor T, the write thyristor M, and the light-emitting thyristor L are connected to the Vsub terminal, they are set to “H”.
The cathode terminals of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H”. The cathode terminals of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the anode terminal and the cathode terminal of the transfer thyristor T are both “H”, and the transfer thyristor T is in the off state.

Similarly, the cathode terminal of the write thyristor M is connected to the write signal line 74 and is set to “H” as described above. Therefore, both the anode terminal and the cathode terminal of the write thyristor M are “H”, and the write thyristor M is in the OFF state.
Further, the cathode terminal of the light emitting thyristor L is connected to the lighting signal line 75 and set to “H”. Therefore, the anode terminal and the cathode terminal of the light emitting thyristor L are both “H”, and the light emitting thyristor L is in the OFF state.

The gate terminal Gt of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rgx. The power supply line 71 is set to the power supply potential Vga of “L” (−3.3 V). Therefore, the potential of the gate terminal Gt is “L” (−3.3 V) except for the gate terminals Gt1 and Gt2 described later.
The gate terminal Gm of the write thyristor M is connected to the power supply line 71 via the power supply line resistance Rgy. Therefore, the potential of the gate terminal Gm is “L” except for the gate terminal Gm1 described later.
Further, the gate terminal Gl of the light emitting thyristor L is connected to the power supply line 71 via the power supply line resistance Rgz. Therefore, the potential of the gate terminal Gl is “L”.
From the above, the threshold voltages of the transfer thyristor T, the write thyristor M, and the light emitting thyristor L are the potentials of the respective gate terminals Gt, Gm, Gl except for the transfer thyristors T1, T2 and the write thyristor M1, which will be described later. The value (−4.8 V) is obtained by subtracting the diffusion potential Vd (1.5 V) of the pn junction from “L” (−3.3 V)).

  As described above, the gate terminal Gt1 at one end of the transfer thyristor array in FIG. 6 is connected to the cathode terminal of the start diode Dx0. The anode terminal of the start diode Dx0 is connected to the second transfer signal line 73. The second transfer signal line 73 is set to “H”. Then, the start diode Dx0 is forward-biased with its cathode terminal being “L” and its anode terminal being “H”. Thereby, the cathode terminal (gate terminal Gt1) of the start diode Dx0 is obtained by subtracting the diffusion potential Vd (1.5 V) of the start diode Dx0 from “H” (0 V) of the anode terminal of the start diode Dx0 (−1. 5V). Therefore, the threshold voltage of the transfer thyristor T1 is −3V obtained by subtracting the diffusion potential Vd (1.5V) from the potential (−1.5V) of the gate terminal Gt1.

The gate terminal Gt2 of the transfer thyristor T2 adjacent to the transfer thyristor T1 is connected to the gate terminal Gt1 via a coupling diode Dx1. The potential of the gate terminal Gt2 of the transfer thyristor T2 becomes −3 V obtained by subtracting the diffusion potential Vd (1.5 V) of the coupling diode Dx1 from the potential (−1.5 V) of the gate terminal Gt1. Therefore, the threshold voltage of the transfer thyristor T2 becomes −4.5V.
The threshold voltage of the transfer thyristor T having a number of 3 or more is −4.8V as described above.

On the other hand, since the gate terminal Gm1 of the write thyristor M1 is connected to the gate terminal Gt1 via the connection diode Dy1, the potential of the gate terminal Gm1 of the write thyristor M1 is the potential of the gate terminal Gt1 (−1.5V). Minus -3V obtained by subtracting the diffusion potential Vd (1.5V) of the connecting diode Dy1 Therefore, the threshold voltage of the write thyristor M1 is −4.5V.
The threshold voltage of the write thyristor M having a number of 2 or more is −4.8V as described above.
Further, the threshold voltage of the light emitting thyristor L is −4.8 V as described above.

<Light emitting chip Cb1>
Since the potentials at the φE terminal and the φW terminal are “H” (0 V), as described in FIGS. 11A and 11B, the permission thyristor Sb is turned on and turned on. Thereby, the potential of the gate terminal Gsb of the permission thyristor Sb is maintained at “H” (0 V). The potential of the write signal line 74 (φWL (Cb) in FIG. 11A) is “H” (0 V). The permission thyristor Sb maintains the ON state while the power supply potential Vga (“L” (−3.3 V)) is applied. Therefore, in the following, it is not described that the permission thyristor Sb is in the ON state.
In the light-emitting chip Cb1, the states of the transfer thyristor T, the write thyristor M, and the light-emitting thyristor L are the same as those of the light-emitting chip Ca1, and thus the description thereof is omitted.

(2) Time b
At time b shown in FIG. 13, the first transfer signal φ1a transmitted to the light emitting chip group #a shifts from “H” (0 V) to “L” (−3.3 V). As a result, the light emitting device 65 enters an operating state.
<Light emitting chip Ca1>
The transfer thyristor T1 having a threshold voltage of −3V is turned on. However, the odd-numbered transfer thyristors T after the transfer thyristor T3 cannot shift to the ON state because the threshold voltage is −4.8V. On the other hand, the transfer thyristor T2 having a threshold voltage of −4.5V cannot be turned on because the second transfer signal φ2a is “H” (0V).

When the transfer thyristor T1 is turned on, the potential of the gate terminal Gt1 becomes “H” (0 V) of the anode terminal. The potential of the cathode terminal of the transfer thyristor T1 (the first transfer signal line 72 in FIG. 6) is −1.7V. Then, the coupling diode Dx1 whose cathode terminal (gate terminal Gt2) was −3V is forward biased because its anode terminal (gate terminal Gt1) becomes “H” (0V). Therefore, the potential of the cathode terminal (gate terminal Gt2) of the coupling diode Dx1 becomes −1.5 V obtained by subtracting the diffusion potential Vd (1.5 V) from “H” (0 V) of the anode terminal (gate terminal Gt1). . As a result, the threshold voltage of the transfer thyristor T2 becomes −3V.
The potential of the gate terminal Gt3 connected to the gate terminal Gt2 of the transfer thyristor T2 via the coupling diode Dx2 becomes −3V. As a result, the threshold voltage of the transfer thyristor T3 becomes −4.5V. Since the transfer thyristor T having a number of 4 or more is the power supply potential Vga whose gate terminal Gt has the potential “L”, the threshold voltage is maintained at −4.8V.

On the other hand, the transfer thyristor T1 is turned on, and the potential of the anode terminal (gate terminal Gt1) of the connection diode Dy1 becomes “H” (0 V). Then, the connection diode Dy1 whose cathode terminal (gate terminal Gm1) was −3 V is forward biased. Therefore, the potential of the cathode terminal (gate terminal Gm1) of the connection diode Dy1 becomes −1.5 V obtained by subtracting the diffusion potential Vd (1.5 V) of the pn junction from the potential (0 V) of the anode terminal (gate terminal Gt1). . As a result, the threshold voltage of the write thyristor M1 becomes −3V.
Note that the potential of the gate terminal Gm2 of the write thyristor M2 becomes −3V, and the threshold voltage of the write thyristor M2 becomes −4.5V. The write thyristor M having a number of 3 or more maintains a threshold voltage of −4.8V.
However, since the potential of the write signal line 74 is “H” (0 V), none of the write thyristors M is turned on.

The cathode terminal (gate terminal Gm1) of the connection diode Dy1 is the anode terminal (gate terminal Gm1) of the connection diode Dz1. Therefore, the potential of the anode terminal (gate terminal Gm1) of the connection diode Dz1 becomes −1.5V. Then, the connection diode Dz1 is forward biased because the potential of the cathode terminal (gate terminal Gl1) was −3.3V. Therefore, the potential of the cathode terminal (gate terminal Gl1) of the connection diode Dz1 is −3V obtained by subtracting the diffusion potential Vd (1.5V) of the pn junction from the potential (−1.5V) of the anode terminal (gate terminal Gm1). become. As a result, the threshold voltage of the light emitting thyristor L1 becomes −4.5V.
On the other hand, even when the potential of the gate terminal Gm2 becomes −3V, the light emitting thyristor L2 maintains the threshold voltage −4.8V. Similarly, the threshold voltage of −4.8 V is maintained in the light emitting thyristor L having a number of 3 or more.
Since the lighting signal line 75 is “H”, none of the light-emitting thyristors L is turned on.

  That is, at time b, the transfer thyristor T1 is turned on. The transfer thyristor T1 is in the on state immediately after the time b (in this case, when the thyristor or the like changes due to the change in the signal potential at the time b and then enters a steady state). The other transfer thyristors T, all the write thyristors M, and the light emitting thyristors L are in the off state.

<Light emitting chip Cb1>
Since the signal transmitted to the light emitting chip group #b to which the light emitting chip Cb1 belongs does not change, the state of the light emitting chip Cb1 at the time a (initial state) is maintained.

  As described above, the gate terminals (gate terminals Gt, Gm, Gl) of the thyristors (transfer thyristor T, write thyristor M, light emitting thyristor L) are connected to each other by the diodes (coupling diode Dx, connection diodes Dy, Dz). Has been. Therefore, when the potential of the gate terminal changes, the potential of the gate terminal connected to the gate terminal whose potential has changed via the forward-biased diode changes. Then, the threshold voltage of the thyristor having the changed gate terminal changes. When the threshold voltage becomes higher than “L”, the thyristor is turned on.

This will be described more specifically. The potential of the gate terminal connected with one forward-biased diode is −1.5V, and the threshold voltage of the thyristor having the gate terminal is −3V. become. Since this threshold voltage is higher than “L” (−3.3 V) (a negative value with a small absolute value), the thyristor is turned on.
On the other hand, the potential of the gate terminal having the potential of “H” (0 V) and the gate terminal connected by two forward-biased diodes is −3 V, and the threshold voltage of the thyristor having the gate terminal is −4. .5V. Since this threshold voltage is lower than “L” (−3.3 V) (a negative value having a large absolute value), the thyristor cannot be turned on and remains off.
The following description will focus on thyristors (transfer thyristor T, write thyristor M, and light-emitting thyristor L) whose threshold voltage changes so that they can be turned on, and description of other changes will be omitted.

(3) Time c
At time c, the lighting signal φIa transmitted to the light emitting chip Ca belonging to the light emitting chip group #a shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
Even if the lighting signal line 75 becomes “L” (−3.3V), the threshold voltage of the light emitting thyristor L1 is −4.5V, and the threshold voltage of the light emitting thyristor L having a number of 2 or more is −4.8V. Therefore, none of the light emitting thyristors L is turned on.
Therefore, immediately after time c, the transfer thyristor T1 is in the ON state.
<Light emitting chip Cb1>
Since the signal transmitted to the light emitting chip Cb belonging to the light emitting chip group #b to which the light emitting chip Cb1 belongs does not change, the state of the light emitting chip Cb1 at the time a (initial state) is maintained.

(4) Time d
At time d, the permission signal φE transmitted in common to the light emitting chip Ca and the light emitting chip Cb shifts from “H” (0 V) to “E1” (−3.3 V).
<Light emitting chip Ca1>
Since the enabling signal φE shifts to “E1” (−3.3V), the potential (φE) of the φE terminal of the light emitting chip Ca1 becomes −3.3V. On the other hand, since the write signal φW1 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −1.7V.
At this time, the write thyristor M1 has a threshold voltage of −3V, the write thyristor M2 has a threshold voltage of −4.5V, and the write thyristor M having a number of 3 or more has a threshold voltage of −4.8V. None of the write thyristors M can be turned on.
Therefore, immediately after time d, the transfer thyristor T1 is in the ON state.

<Light emitting chip Cb1>
The potential (φE) of the φE terminal of the light emitting chip Cb1 is −3.3V. On the other hand, since the write signal φW2 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −0.6V.
At this time, the write thyristor M1 has a threshold voltage of −4.5V, and the write thyristor M having a number of 2 or more has a threshold voltage of −4.8V. Therefore, none of the write thyristors M can be turned on.

(5) Time e
At time e, the write signal φW1 transmitted to the light emitting chip set # 1 formed by the light emitting chip Ca1 belonging to the light emitting chip group #a and the light emitting chip Cb1 belonging to the light emitting chip group #b is “H” (0 V) To “L” (−3.3 V).
<Light emitting chip Ca1>
The permission signal φE has shifted to “E1” (−3.3 V) at time d. Therefore, the potential (φE) of the φE terminal of the light emitting chip Ca1 is −3.3V, and the potential (φW) of the φW terminal is −3.3V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −3.3V.
Then, the write thyristor M1 having a threshold voltage of −3V is turned on. On the other hand, the write thyristor M2 cannot be turned on because the threshold voltage is −4.5V and the write thyristor M having a number of 3 or more has a threshold voltage of −4.8V.

  When the write thyristor M1 is turned on, the gate terminal Gm1 becomes “H” (0 V). Then, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) is changed from −3.3V to −1.7V.

Thereby, the anode terminal (gate terminal Gm1) of the connection diode Dz1 becomes “H” (0 V). Then, the connection diode Dz1 is forward biased because the cathode terminal (gate terminal Gt1) is −3V. Therefore, the cathode terminal (gate terminal Gl1) of the connection diode Dz1 is −1.5V, and the threshold voltage of the light emitting thyristor L1 is −3V.
Note that the threshold voltage of the light-emitting thyristor L having a number of 2 or more is maintained at −4.8V.

The lighting signal line 75 has shifted to “L” (−3.3 V) at time c. Then, at the timing (time e) when the write signal φW1 shifts from “H” (0 V) to “L” (−3.3 V), the light-emitting thyristor L1 is turned on and lit (emits light). Note that the light-emitting thyristor L having a number of 2 or more cannot be turned on because the threshold voltage is −4.8V.
Therefore, immediately after the time e, the transfer thyristor T1 and the write thyristor M1 are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
The potential (φE) of the φE terminal of the light emitting chip Cb1 is −3.3V, and the potential (φW) of the φW terminal is −3.3V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −2.5V.
Since the write thyristor M1 has a threshold voltage of −4.5V and the write thyristor M having a number of 2 or more has a threshold voltage of −4.8V, none of the write thyristors M can be turned on.

(6) Time f
At time f, the write signal φW1 transmitted to the light-emitting chip set # 1 formed by the light-emitting chip Ca1 belonging to the light-emitting chip group #a and the light-emitting chip Cb1 belonging to the light-emitting chip group #b is “L” (−3 .3V) to “H” (0V).
<Light emitting chip Ca1>
The potential (φE) of the φE terminal of the light emitting chip Ca1 is −3.3V, and the potential (φW) of the φW terminal is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −1.7V.
The write thyristor M1 connected to the write signal line 74 is on. The potential of the write signal line 74 (φWL (Ca) in FIG. 10A) for maintaining the ON state of the write thyristor M1 should be lower than −1.7V (≦ −1.7V). Therefore, the write thyristor M1 continues to be on.
Therefore, immediately after time f, the transfer thyristor T1 and the write thyristor M1 are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
The potential (φE) of the φE terminal of the light emitting chip Cb1 is −3.3V, and the potential (φW) of the φW terminal is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −0.6V.

(7) Time g
At time g, the first transfer signal φ1b transmitted to the light emitting chip group #b shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
Since the signal transmitted to the light emitting chip Ca1 belonging to the light emitting chip group #a is not changed, the state immediately after the time f is maintained.
<Light emitting chip Cb1>
The operation of the light emitting chip Cb1 is similar to the operation of the light emitting chip Ca1 at time b. That is, the transfer thyristor T1 is turned on. As a result, the potential of the first transfer signal line 72 becomes −1.7V. Further, the threshold voltage of the transfer thyristor T2 is -3V, and the threshold voltage of the write thyristor M1 is -3V.
That is, the light-emitting chip Cb1 operates at a timing (a phase is shifted by 180 °) that is a half-period of the period T on the time axis.
Immediately after time g, the transfer thyristor T1 and the permission thyristor Sb are in the ON state.

(8) Time h
At time h, the lighting signal φIb transmitted to the light emitting chip group #b shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
Since there is no change in the signal transmitted to the light emitting chip Ca1 belonging to the light emitting chip group #a, the state immediately after the time f is maintained.
<Light emitting chip Cb1>
Since the operation of the light emitting chip Cb1 is the same as the operation of the light emitting chip Ca1 at time c, detailed description thereof is omitted.
Immediately after time h, the transfer thyristor T1 is in the ON state.
Here, the time c and the time h are shifted by a half of the period T.

(9) Time i
At time i, the permission signal φE transmitted in common to the light emitting chip Ca and the light emitting chip Cb shifts from “E1” (−3.3 V) to “E2” (−5.3 V).
<Light emitting chip Ca1>
Since the permission signal φE is “E2” (−5.3V), the potential (φE) of the φE terminal of the light emitting chip Ca1 is −5.3V. Then, as described above, the permission thyristor Sa is turned on and turned on. On the other hand, since the write signal φW1 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −0.6V.
When the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −0.6 V, the write thyristor M1 can no longer maintain the on state and is turned off. Since the transfer thyristor T1 is in the ON state, the threshold voltage of the write thyristor M1 is −3V.
However, since the lighting signal φIa is “L” (−3.3 V), the light emitting thyristor L1 in the on state maintains the on state.
Therefore, immediately after the time i, the transfer thyristor T1 and the permission thyristor Sa are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
Since the permission signal φE is “E2” (−5.3V), the potential (φE) of the φE terminal of the light emitting chip Cb1 is −5.3V. On the other hand, since the write signal φW2 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −1.5V.
However, at this time, the write thyristor M1 has a threshold voltage of −3V, the write thyristor M2 has a threshold voltage of −4.5V, and the write thyristor M having a number of 3 or more has a threshold voltage of −4.8V. Therefore, none of the write thyristors M can be turned on.
Immediately after time i, the transfer thyristor T1 is in the ON state.

(10) Time j
At time j, the write signal φW1 transmitted to the light emitting chip set # 1 formed by the light emitting chip Ca1 belonging to the light emitting chip group #a and the light emitting chip Cb1 belonging to the light emitting chip group #b is “H” (0 V). To “L” (−3.3 V).
<Light emitting chip Ca1>
Since the permission signal φE is “E2” (−5.3V), the potential (φE) of the φE terminal of the light emitting chip Ca1 is −5.3V. On the other hand, since the write signal φW1 is “L” (−3.3V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is −3.3V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) shifts from −0.6 V to −2.2 V at time i. .
At this time, the threshold voltage of the write thyristor M1 is −3V, the threshold voltage of the write thyristor M2 is −4.5V, and the threshold voltage of the write thyristor M whose number is 3 or more is −4.8V. None of the write thyristors M are turned on.
Therefore, immediately after time j, the transfer thyristor T1 and the permission thyristor Sa are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
Since the permission signal φE is “E2” (−5.3V), the potential (φE) of the φE terminal of the light emitting chip Cb1 is −5.3V. On the other hand, since the write signal φW1 is “L” (−3.3V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is −3.3V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) shifts from −1.5 V at time i to −3.3 V. .
Then, the write thyristor M1 having a threshold voltage of −3V is turned on. On the other hand, the write thyristor M2 cannot be turned on because the threshold voltage is −4.5V and the write thyristor M having a number of 3 or more has a threshold voltage of −4.8V.

  When the write thyristor M1 is turned on, the gate terminal Gm1 becomes “H” (0 V). Then, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) is changed from −3.3V to −1.7V.

Thereby, the anode terminal (gate terminal Gm1) of the connection diode Dz1 becomes “H” (0 V). Then, the connection diode Dz1 is forward biased because the cathode terminal (gate terminal Gt1) is −3V. Therefore, the cathode terminal (gate terminal Gl1) of the connection diode Dz1 is −1.5V, and the threshold voltage of the light emitting thyristor L1 is −3V.
Note that the threshold voltage of the light-emitting thyristor L having a number of 2 or more is maintained at −4.8V.

The lighting signal line 75 has shifted to “L” (−3.3 V) at time h. Then, at the timing (time j) when the write signal φW1 shifts from “H” (0 V) to “L” (−3.3 V), the light-emitting thyristor L1 is turned on and lighted (emits light). Note that the light-emitting thyristor L having a number of 2 or more cannot be turned on because the threshold voltage is −4.8V.
Therefore, immediately after time j, the transfer thyristor T1 and the write thyristor M1 are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(11) Time k
At time k, the write signal φW1 transmitted to the light emitting chip set # 1 formed by the light emitting chip Ca1 belonging to the light emitting chip group #a and the light emitting chip Cb1 belonging to the light emitting chip group #b is “L” (−3 .3V) to “H” (0V).
<Light emitting chip Ca1>
The potential (φE) of the φE terminal of the light emitting chip Ca1 is −5.3V. On the other hand, since the write signal φW1 becomes “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) shifts from −2.2 V at time i to −0.6 V. .
At this time, the threshold voltage of the write thyristor M1 is −3V, the threshold voltage of the write thyristor M2 is −4.5V, and the threshold voltage of the write thyristor M whose number is 3 or more is −4.8V. None of the write thyristors M are turned on.
Therefore, immediately after time k, the transfer thyristor T1 and the permission thyristor Sa are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
The potential (φE) of the φE terminal of the light emitting chip Cb1 is −5.3V. On the other hand, since the write signal φW1 becomes “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) shifts from −3.3V at time j to −1.5V. .
The write thyristor M1 connected to the write signal line 74 is on. The potential of the write signal line 74 (φWL (Cb) in FIG. 11A) for maintaining the ON state of the write thyristor M1 needs to be lower than −1.7V (≦ −1.7V). Therefore, the write thyristor M1 cannot be kept on and is turned off. Since the transfer thyristor T1 is in the on state, the threshold voltage of the write thyristor M1 becomes −3V.
Even when the write thyristor M1 is turned off, the lighting signal φIb is maintained at “L” (−3.3 V), so that the light emitting thyristor L1 is maintained in the ON state.
Therefore, immediately after time k, the transfer thyristor T1 is in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(12) Time l
At time l, the second transfer signal φ2a transmitted to the light emitting chip group #a shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
The transfer thyristor T2 having a threshold voltage of −3V is turned on. However, even-numbered transfer thyristors T having a number of 4 or more cannot be turned on because the threshold voltage is −4.8V.

When the transfer thyristor T2 is turned on, the gate terminal Gt2 becomes “H” (0 V). Then, the potential of the gate terminal Gt3 connected to the gate terminal Gt2 of the transfer thyristor T2 via the coupling diode Dx2 becomes −1.5V. As a result, the threshold voltage of the transfer thyristor T3 becomes -3V.
Then, the potential of the second transfer signal line 73 (see FIG. 6) becomes −1.7V.

  On the other hand, when the transfer thyristor T2 is turned on and the gate terminal Gt2 becomes “H”, the potential of the gate terminal Gm1 becomes −1.5 V via the connection diode Dy2. As a result, the threshold voltage of the write thyristor M2 becomes −3V. However, since the potential (φE) of the φE terminal of the light emitting chip Ca1 is −5.3V and the potential (φW) of the φW terminal is 0V, the potential of the write signal line 74 as shown in FIG. (ΦWL (Ca) in FIG. 10A) is −0.6V. Therefore, the write thyristor M2 cannot be turned on.

  Furthermore, the potential of the gate terminal Gl2 becomes −3 V via the connection diode Dz2. As a result, the threshold voltage of the light emitting thyristor L2 becomes −4.5V. At this time, since the potential of the lighting signal line 75 is −1.7 V by the light emitting thyristor L1 in the on state, the light emitting thyristor L2 is not turned on.

That is, at time l, the transfer thyristor T2 can be turned on.
Immediately after time l, the transfer thyristor T1, the transfer thyristor T2, and the permission thyristor Sa are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

<Light emitting chip Cb1>
Since there is no change in the signal transmitted to the light emitting chip Cb belonging to the light emitting chip group #b, the state immediately after the time k is maintained.

(13) Time m
At time m, the first transfer signal φ1a transmitted to the light emitting chip Ca belonging to the light emitting chip group #a shifts from “L” (−3.3 V) to “H” (0 V).
<Light emitting chip Ca1>
The transfer thyristor T1 in the on state is turned off because both the cathode terminal and the anode terminal are "H". As a result, the gate terminal Gt1 shifts from “H” to “L” (−3.3V), and the threshold voltage of the transfer thyristor T1 becomes −4.8V. The coupling diode Dx1 is reverse-biased because the anode terminal (gate terminal Gt1) is “L” and the cathode terminal (gate terminal Gt2) is “H”.
Similarly, the connection diode Dy1 also has an anode terminal (gate terminal Gt1) of “L” (−3.3 V). Then, since the cathode terminal (gate terminal Gm1) was −1.5 V, the connection diode Dy1 is reverse-biased. As a result, the cathode terminal (gate terminal Gm1) of the connection diode Dy1 starts to shift to “L”.
Further, when the cathode terminal (gate terminal Gm1) shifts to “L”, the connection diode Dz1 becomes reverse biased because the cathode terminal (gate terminal Gl1) is “H” by the light emitting thyristor L1 in the on state. . Therefore, in the write thyristor M1, the gate terminal Gm1 becomes “L”, and the threshold voltage becomes −4.8V.
Immediately after the time m, the transfer thyristor T2 and the permission thyristor Sa are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.
It should be noted that the gate terminal connected to the gate terminal that has become “H” (0 V) with a reverse-biased diode is not affected by the “H” (0 V), and the threshold voltage of the thyristor is high (absolutely The value does not become a small negative or zero value.

<Light emitting chip Cb1>
Since there is no change in the signal transmitted to the light emitting chip Cb1 belonging to the light emitting chip group #b, the state at the time k is maintained.

(14) Time n
At time n, the lighting signal φIa transmitted to the light emitting chip Ca belonging to the light emitting chip group #a shifts from “L” (−3.3 V) to “H” (0 V).
<Light emitting chip Ca1>
When the lighting signal φIa shifts from “L” (−3.3 V) to “H” (0 V), the light-emitting thyristor L1 in the on state is turned off with both the cathode terminal and the anode terminal being “H”. Turns off (turns off). As a result, the gate terminal Gl1 shifts toward “L”. The threshold voltage of the light emitting thyristor L1 is −4.8V.
That is, the light-emitting thyristor L1 of the light-emitting chip Ca1 is lit (lighted) (turned on) at the timing when the writing signal φW1 at time e shifts from “H” to “L”, and the lighting signal φIa at time n is “L”. Is turned off (turned off) at the timing of transition from “H” to “H”. A period from time e to time n corresponds to a lighting (light emitting) period of the light emitting thyristor L1 of the light emitting chip Ca1.
Immediately after time n, the transfer thyristor T2 and the permission thyristor Sa are on.

<Light emitting chip Cb1>
Since there is no change in the signal transmitted to the light emitting chip Cb1 belonging to the light emitting chip group #b, the state at the time k is maintained.

(15) Time o
At time o, the permission signal φE transmitted in common to the light emitting chip Ca and the light emitting chip Cb shifts from “E2” (−5.3 V) to “H” (0 V). In addition, the lighting signal φIa transmitted to the light emitting chip Ca belonging to the light emitting chip group #a shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
When the enabling signal φE shifts from “E2” (−5.3 V) to “H” (0 V), the potential (φE) of the φE terminal of the light emitting chip Ca1 becomes 0 V. On the other hand, since the write signal φW1 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is 0V. As described above, the permission thyristor Sa is turned off, and as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) is − at time n. Transition from 0.6V to 0V. However, since any write thyristor M is in the OFF state, no change in state occurs.
Further, the lighting signal φIa shifts from “H” (0 V) to “L” (−3.3 V), but the threshold voltage of the light-emitting thyristor L1 is −4.8 V and the threshold voltage of the light-emitting thyristor L2 is −. Since the threshold voltage of the light emitting thyristor L with 4.5V and the number of 3 or more is −4.8V, none of the light emitting thyristors L is lit.
Therefore, immediately after time o, the transfer thyristor T2 is in the on state.
The light-emitting thyristor L1 in the on state is turned off at time n, and the potential of the gate terminal Gl1 changes from 0V to “L” (−3.3V). At this time, when the lighting signal φIa is changed from “H” (0 V) to “L” (−3.3 V) when the potential of the gate terminal G11 is higher than −1.8 V, the light emitting thyristor L1 is turned on again. Will do. Therefore, the interval between time n and time o is preferably set until the threshold voltage of the light-emitting thyristor L1 becomes lower than −3.3V.
Immediately after time o, the transfer thyristor T2 is on.

From time o, the lighting control thyristor L2 of the light emitting chip Ca1 enters the lighting control period Ta (2).
Since the first transfer signal φ1a and the second transfer signal φ2a change with the periods Ta (1) and Ta (2) as periods, the waveforms of these signals are different, but the operation of the light-emitting chip Ca1 starts from time c. The period Ta (1) up to o is repeated. Therefore, in the period Ta (2), the description of the operation of the light emitting chip Ca1 is omitted except for the first transfer signal φ1a, the second transfer signal φ2a, and the transfer thyristor T related thereto.

<Light emitting chip Cb1>
When the enabling signal φE shifts from “E2” (−5.3 V) to “H” (0 V), the potential (φE) of the φE terminal of the light emitting chip Cb1 becomes 0 V. On the other hand, since the write signal φW1 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) shifts from −1.5 V at time k to 0 V. However, since any write thyristor M is in the OFF state, no change in state occurs.
Therefore, immediately after time o, the transfer thyristor T1 is in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

  At time o, the transition of the permission signal φE from “E2” (−5.3 V) to “H” (0 V) and the lighting signal φIa from “H” (0 V) to “L” (−3.3 V). ) Is performed in parallel, but either may be performed first. This is because even if the enabling signal φE is changed, neither the writing thyristor M of the light emitting chip Ca1 nor the light emitting chip Cb1 is turned on. Even if the lighting signal φIa is changed, any of the light emitting thyristors of the light emitting chip Ca1 is changed. This is because L does not turn on.

(16) Time p
At time p, as in time d, the permission signal φE transmitted in common to the light emitting chip Ca and the light emitting chip Cb shifts from “H” (0 V) to “E1” (−3.3 V).
<Light emitting chip Ca1>
Since the enabling signal φE shifts to “E1” (−3.3V), the potential (φE) of the φE terminal of the light emitting chip Ca1 becomes −3.3V. On the other hand, since the write signal φW1 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Ca1 is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −1.7V.
At this time, the write thyristor M1 has a threshold voltage of −4.8V, the write thyristor M2 has a threshold voltage of −3V, the write thyristor M3 has a threshold voltage of −4.5V, and the number is 4 or more. Since the thyristor M has a threshold voltage of −4.8V, none of the write thyristors M can be turned on.
Therefore, immediately after time p, the transfer thyristor T2 is in the ON state.

<Light emitting chip Cb1>
The potential (φE) of the φE terminal of the light emitting chip Cb1 is −3.3V. On the other hand, since the write signal φW2 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −0.6V.
At this time, the write thyristor M1 has a threshold voltage of −4.5V, and the write thyristor M having a number of 2 or more has a threshold voltage of −4.8V. Therefore, none of the write thyristors M can be turned on.
Therefore, immediately after time p, the transfer thyristor T1 is in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(17) Time q
At time q, the lighting signal φIb transmitted to the light emitting chip Cb belonging to the light emitting chip group #b shifts from “L” (−3.3 V) to “H” (0 V).
<Light emitting chip Ca1>
Similar to the state at time g, immediately after time q, the transfer thyristor T2 and the write thyristor M2 are in the on state, and the light emitting thyristor L2 is lit (emitted) in the on state.
<Light emitting chip Cb1>
Similarly to the light emitting chip Ca1 at time n, when the lighting signal φIb shifts from “L” (−3.3 V) to “H” (0 V), the light emitting thyristor L1 that is in the on state has the cathode terminal and the anode terminal Both become “H”, shift to the off state, and turn off. As a result, the gate terminal Gl1 shifts toward “L”. The threshold voltage of the light emitting thyristor L1 is −4.8V.
That is, the light emitting thyristor L1 of the light emitting chip Cb1 is lit (lights on) (turned on) at the timing when the write signal φW1 at time j shifts from “H” to “L”, and the lighting signal φIb at time q is “L”. Is turned off (turned off) at the timing of transition from “H” to “H”. A period from time k to time q corresponds to a lighting (light emission) period of the light emitting thyristor L1 of the light emitting chip Cb1.
Immediately after time q, the transfer thyristor T2 is on.

(18) Time r
At time r, the period Tb (1) for controlling the light emitting thyristor L1 of the light emitting chip group #b ends.

(19) Time s
At time s, the first transfer signal φ1a transmitted to the light emitting chip Ca belonging to the light emitting chip group #a shifts from “H” (0 V) to “L” (−3.3 V).
<Light emitting chip Ca1>
The transfer thyristor T3 having the threshold voltage of −3V is turned on. As a result, the gate terminal Gt3 becomes “H” (0 V). As a result, the threshold voltage of the write thyristor M3 becomes -3V, and the threshold voltage of the light emitting thyristor L4 becomes -4.5V. Further, the potential of the gate terminal Gt4 becomes −1.5V. As a result, the threshold voltage of the transfer thyristor T4 becomes −3V.
Immediately after the time s, the transfer thyristors T2 and T3 and the permission thyristor Sa are in the on state, and the light emitting thyristor L2 is lit (emitted) in the on state.
<Light emitting chip Cb1>
Since there is no change in the signal transmitted to the light emitting chip Cb1 belonging to the light emitting chip group #b, there is no change in the state.
Immediately after time s, the transfer thyristor T2 is in the on state, and the light emitting thyristor L2 is lit (emitted) in the on state.

(20) Time t
At time t, the second transfer signal φ2a transmitted to the light emitting chip Ca1 belonging to the light emitting chip group #a shifts from “L” (−3.3 V) to “H” (0 V).
<Light emitting chip Ca1>
The transfer thyristor T2 in the on state is turned off because both the cathode terminal and the anode terminal are "H". Then, the gate terminal Gt2 of the transfer thyristor T2 shifts to “L”. Then, the gate terminal Gm2 of the writing thyristor M2 and the gate terminal Gl2 of the light emitting thyristor L2 also shift to “H”. Then, the threshold voltage of the transfer thyristor T2 and the write thyristor M2 becomes −4.8V.
Immediately after time t, the transfer thyristor T3 is on and the light-emitting thyristor L2 is on (lights on).
<Light emitting chip Cb1>
Since there is no change in the signal transmitted to the light emitting chip Cb1 belonging to the light emitting chip group #b, there is no change in the state.
Immediately after time t, the transfer thyristor T2 and the write thyristor M2 are in the on state, and the light emitting thyristor L2 is in the on state (lights on).

(21) Others At time u, the period Ta (2) for controlling the light emitting thyristor L2 of the light emitting chip Ca belonging to the light emitting chip group #a ends. At time v, the period Tb (2) for controlling the light emitting thyristor L2 of the light emitting chip Cb belonging to the light emitting chip group #b ends. At time w, the period Ta (3) for controlling the light emitting thyristor L3 of the light emitting chip Ca belonging to the light emitting chip group #a ends. At time x, the period Tb (3) for controlling the light emitting thyristor L3 of the light emitting chip Cb belonging to the light emitting chip group #b ends. At time y, the period Ta (4) for controlling the light emitting thyristor L4 of the light emitting chip Ca belonging to the light emitting chip group #a is ended. Similarly, the lighting control of all the light emitting thyristors L of the light emitting chip Ca and the light emitting chip Cb is performed.

The operations of the light emitting chips Ca and Cb of the light emitting device 65 described above will be described together.
First, the operation of the transfer thyristor T will be described.
In the light emitting chips Ca and Cb in the first embodiment, the ON state of the transfer thyristor T is sequentially shifted by the two-phase transfer signals (the first transfer signal φ1 and the second transfer signal φ2).
That is, when one of the two-phase transfer signals becomes “L” (−3.3 V), the transfer thyristor T in which one of the transfer signals is transmitted to the cathode terminal is turned on. The gate terminal Gt becomes “H” (0 V). The potential of the gate terminal Gt of the adjacent transfer thyristor T connected to the gate terminal Gt which has become “H” (0 V) and the forward-biased coupling diode Dx becomes −1.5V. As a result, the threshold voltage of the adjacent transfer thyristor T increases (in the present embodiment, from −4.5 V to −3 V), and the other transfer signal becomes “L” (−3.3 V). Turns on.
That is, the two-phase transfer signals (the first transfer signal φ1 and the second transfer signal φ2) are overlapped by the period of “L” (−3.3 V) (the period from time l to time m in FIG. 13). The transmission thyristors T are sequentially set to the ON state by transmitting with the phase shifted.

  When the transfer thyristor T is turned on and the gate terminal Gt becomes “H” (0 V), the potential of the gate terminal Gm of the write thyristor M connected to the gate terminal Gt via the connection diode Dy is −. 1.5V, and the threshold voltage of the write thyristor M becomes -3V.

  When the potential of the write signal line 74 becomes “L” (−3.3 V) by the combination of the enable signal φE and the write signal φW (φW1 to φW20), the write thyristor M is turned on.

When the write thyristor M is turned on, the gate terminal Gm of the write thyristor M becomes “H” (0 V), and the potential of the gate terminal Gl connected to the gate terminal Gm via the connection diode Dz is −1. 5V. As a result, the threshold voltage of the light emitting thyristor L becomes −3V.
By the combination of the enable signal φE and the write signal φW (φW1 to φW20), the lighting signal φI (φIa or φIb) before the time when the potential of the write signal line 74 becomes “L” (−3.3 V). Is set to “L” (−3.3 V), at the timing (time) when the potential of the write signal line 74 becomes “L” (−3.3 V), the light emitting thyristor L is turned on and turned on (light emitting). )

  Thus, during the lighting period in which the light emitting thyristor L is lit (lights on), the potential of the write signal line 74 is “L” (−) by the combination of the enable signal φE and the write signal φW (φW1 to φW20). 3.3V) to the time when the lighting signal φI (φIa or φIb) changes from “L” to “H” (from time e to time n or from time j to time q in FIG. 13). .

  On the other hand, in a period in which the potential of the write signal line 74 is not “L” (−3.3 V), the write thyristor M is not turned on, and the light emitting thyristor L is not turned on.

In this embodiment, when the enable signal φE is “E1” (−3.3 V) and the write signal φW (φW1 to φW20) is “L” (−3.3 V), the light emitting chip. The light emitting thyristors L of the light emitting chips Ca1 to Ca20 belonging to the group #a are turned on. On the other hand, if the enable signal φE is “E2” (−5.3 V) and the write signal φW (φW1 to φW20) is “L” (−3.3 V), the light emission belonging to the light emitting chip group #b. The light emitting thyristor L of the chip Cb is turned on.
That is, the light emitting chip group is selected and controlled according to the potential level of the enable signal φE.

  Therefore, in the present embodiment, a period of “E1” (−3.3 V) and a period of “E2” (−5.3 V) are provided in the permission signal φE. Then, the writing to be transmitted in common to each of the light emitting chip groups (# 1 to # 20) composed of one light emitting chip Ca belonging to the light emitting chip group #a and one light emitting chip Cb belonging to the light emitting chip group #b. Two periods of “L” are provided for the signal φW (φW1 to φW20) (in φW1 shown in FIG. 13, a period from time e to time f and a period from time j to time k). That is, the light emitting chip Ca belonging to the light emitting chip group #a in the previous “L” period on the time axis, and the light emitting chip Cb belonging to the light emitting chip group #b in the subsequent “L” period on the time axis. Is set to start lighting.

In this embodiment, the light-emitting chip group #a and the light-emitting chip group #b respectively transmit transfer signals (first transfer signals φ1a and φ1b and second transfer signals φ2a and φ2b) and lighting signals φI ( The timing of φIa and φIb) is shifted by a period of ½ of T. Thus, the width (margin) of the period in which two “L” periods provided in the write signal φW (φW1 to φW20) are set is maximized.
In other words, the two “L” times provided for the write signal φW may be provided in the first half of the period Ta and in the second half of the period Ta, respectively.

The combination of the enable signal φE and the write signal φW (φW1 to φW20) causes the potential of the write signal line 74 to be “L” (−3.3 V), so that the light-emitting thyristor L is selected as a lighting target. .
When the potential of the write signal line 74 is “L” (−3.3 V), the lighting signal φIa or φIb that supplies a current for lighting to the light-emitting thyristor L to be lighted is “L” (−3 .3V).

Next, the operation of the light emitting chips Ca2 and Cb2 belonging to the light emitting chip set # 2 will be described. As described above, the light emitting chip Ca2 operates in parallel with the light emitting chip Ca1, and operates in the same manner as the light emitting chip Ca1. The light emitting chip Cb2 operates in parallel with the light emitting chip Cb1, and operates in the same manner as the light emitting chip Cb1.
Therefore, in the light emitting chips Ca2 and Cb2 belonging to the light emitting chip set # 2, a case where some of the light emitting thyristors L are not turned on will be described.

As described above, in the light emitting chip set # 2, the light emitting thyristors L2, L3, and L4 of the light emitting chip Ca2 are turned on, and the light emitting thyristors L1, L3, and L4 of the light emitting chip Cb2 are turned on. The light emitting thyristor L1 of the light emitting chip Ca2 and the light emitting thyristor L2 of the light emitting chip Cb2 were left unlit.
When the light-emitting thyristor L1 of the light-emitting chip Ca2 is left unlit (not lighted), the write signal φW1 is set to “L” to turn on the light-emitting thyristor L1 of the light-emitting chip group # 1 from time e to time f In the period up to this time, the write signal φW2 is maintained at “H”.
That is, since the enabling signal φE is “E1” (−3.3V), the potential (φE) of the φE terminal of the light emitting chip Ca2 is −3.3V. On the other hand, since the write signal φW2 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 10B, the potential of the write signal line 74 (φWL (Ca) in FIG. 10A) becomes −1.7V. The write thyristor M1 is not turned on because the threshold voltage is -3V. Further, since the threshold voltage of the light emitting thyristor L1 is still -4.5V, it is not turned on.
Therefore, the light emitting thyristor L1 of the light emitting chip Ca2 remains unlit.

Similarly, in the light emitting thyristor L2 of the light emitting chip Cb2, the write signal φW2 is maintained at “H”. Since the enabling signal φE is “E2” (−5.3 V), the potential (φE) of the φE terminal of the light emitting chip Cb2 is −5.3 V. On the other hand, since the write signal φW2 is “H” (0V), the potential (φW) of the φW terminal of the light emitting chip Cb1 is 0V. Then, as shown in FIG. 11B, the potential of the write signal line 74 (φWL (Cb) in FIG. 11A) becomes −1.5V. The write thyristor M1 is not turned on because the threshold voltage is -3V. Further, since the threshold voltage of the light emitting thyristor L1 is still -4.5V, it is not turned on.
Therefore, the light emitting thyristor L1 of the light emitting chip Ca2 remains unlit.

On the other hand, the light quantity of the light emitting thyristor L may differ between the light emitting chips Ca or Cb and between the light emitting thyristors L due to variations in manufacturing conditions. For this reason, the light-emitting thyristor L is used after correcting the light amount (light amount correction). There are two methods for correcting the amount of light: a method in which the current passed through the light-emitting thyristor L is adjusted, and a method in which the lighting period of the light-emitting thyristor L is adjusted.
As described above, during the lighting period of the light emitting thyristor L, the lighting signal φI (φIa or φIb) starts from the time when the potential of the write signal line 74 becomes “L” (−3.3 V) and the light emitting thyristor L is turned on. Is from “L” to “H” until the light-emitting thyristor L is turned off (turned off).

As shown in FIG. 13, the light-emitting thyristor L1 of the light-emitting chip Cb1 is turned on and turned on (emits light) by setting the write signal φW1 to “L” at time j. On the other hand, the light-emitting thyristor L1 of the light-emitting chip Cb2 is turned on and turned on (emits light) by setting the write signal φW1 to “L” at a time between time j and time k.
That is, the lighting period of the light emitting thyristor L1 of the light emitting chip Cb2 is shorter than the lighting period of the light emitting thyristor L1 of the light emitting chip Cb1.
In this way, the lighting period can be lengthened or shortened by adjusting the time at which the write signal φW is shifted to “L”.

  As described above, the permission signal φE is a signal that permits the light-emitting chip Ca or Cb to be lit, and the write signal φW is a signal that sets the light-emitting chip Ca or Cb to be lit or not lit. .

[Second Embodiment]
In the second embodiment, the waveform of the permission signal φE is different from that in the first embodiment.
As described above, the permission thyristor Sa provided in the light emitting chip Ca is turned on and turned on when “E2” (−5.3 V) is transmitted to the φE terminal. The on-state permission thyristor Sa is kept on even when the φE terminal shifts to “L” (−3.3 V). That is, regardless of whether the potential (φW) at the φW terminal is “H” (0 V) or “L” (−3.3 V), the potential is turned on and the potential of the write signal line 74 is no longer (FIG. 10). ΦWL (Ca)) in (a) cannot be “L” (−3.3 V).
Therefore, in the first embodiment, as shown in FIG. 13, at time o, the permission signal φE is shifted from “E2” (−5.3 V) to “H” (0 V) to enable the ON state. The thyristor Sa was turned off.
For this reason, the permission signal φE is changed stepwise from “E1” (−3.3 V) to “E2” (−5.3), and the light emitting chip Ca of the light emitting chip group #a is first and then the light emitting chip group. The light emitting chip Cb of #b is controlled to be turned on later.

In the second embodiment, it is possible to control the lighting of the light emitting chip Cb belonging to the light emitting chip group #b first and the light emitting chip Ca belonging to the light emitting chip group #a later.
FIG. 14 is a timing chart for explaining the operation of the light emitting device 65 in the second embodiment.
Here, the light emitting chip Cb belonging to the light emitting chip group #b is controlled to be lighted first, and the light emitting chip Ca belonging to the light emitting chip group #a is controlled to be lighted later.
Therefore, the first transfer signal φ1a, the second transfer signal φ2a, the lighting signal φIa, and the first transfer signal φ1b, the second transfer signal φ2b, and the lighting signal φIb are switched.
At time d, the permission signal φE shifts from “H” (0 V) to “E2” (−5.3 V), and at time h, “E2” (−5.3 V) changes to “H” (0 V). ). Then, at time i, “H” (0 V) is shifted to “E1” (−3.3 V), and at time o, “E1” (−3.3 V) is shifted to “H” (0 V). Yes.
That is, the permission signal φE shifts to “H” (0 V) after shifting to “E1” (−3.3 V) or “E2” (−5.3 V). The permission thyristor Sa in the on state is turned off by the transition to “H” (0 V). Thereby, the light emitting chip Cb belonging to the light emitting chip group #b is controlled to be lighted first, and the light emitting chip Ca belonging to the light emitting chip group #a is controlled to be lighted later.

  Since the operation of the light emitting device 65 in the second embodiment is the same as that described in the first embodiment, the description thereof is omitted.

  In the first embodiment, a period of “H” (0 V) may be provided after a period (for example, from time d to time i) of “E1” (−3.3 V) of the permission signal φE. .

As described above, in the first and second embodiments, the light emitting chip Ca of the light emitting chip group #a and the light emitting chip Cb of the light emitting chip group #b are used, and the light emitting chip group #a is used as the light emitting chip group #a. One light emitting chip Ca and one light emitting chip Cb belonging to the light emitting chip group #b form a light emitting chip group, and each light emitting chip group has a set of signals (first transfer signal φ1, second transfer signal φ2, The lighting signal φI) is transmitted in common. Then, the potentials of the write signal lines 74 of the light emitting chips Ca and Cb are controlled by a combination of the permission signal φE and the write signals φW1 to φW20 transmitted to each light emitting chip group. When the potential of the write signal line 74 becomes “L” (−3.3 V), the light emitting chip group #a or #b is selected and the light emitting device 65 is driven.
Thereby, the lighting signal line 204 for supplying a large current for lighting (light emission) is made common in the light emitting chip group, and the number of wirings is suppressed. Thereby, the size (size) of the circuit board 62 of the light emitting device 65 is suppressed.

In the first and second embodiments, the transfer thyristor T is driven by two phases of the first transfer signal φ1 and the second transfer signal φ2, but the transfer thyristor T transmits three-phase transfer signals for every three transfer thyristors T. And may be driven. Similarly, a transfer signal of four or more phases may be transmitted or driven.
In the first and second embodiments, the coupling diode Dx is used as the first electrical means. However, the first electrical means has a change in the potential of one terminal of the potential of the other terminal. Any resistor may be used as long as it causes a change.
Further, the connection diode Dy was used as the second electrical means, and the connection diode Dz was used as the third electrical means. The connecting diodes Dy and Dz cause a potential drop to shift the potential. Therefore, the second electrical means and the third electrical means may be any one that causes a potential drop, and may be a resistance or the like.

In the first to second embodiments, each of the light emitting chips Ca and Cb is provided with one self-scanning light emitting element array (SLED), but it may be two or more. . When two or more are mounted, each self-scanning light emitting element array (SLED) may be replaced with the light emitting chip Ca or Cb.
Further, the number of light emitting points (light emitting thyristors L) of the light emitting element array 102 has been described as 128, but this number can be arbitrarily set.

  In the first to second embodiments, the number of the light emitting chips Ca and Cb constituting the light emitting chip groups #a and #b and the number of the light emitting chips Ca and Cb constituting the light emitting chip group are the same. , May be different.

  Further, in the first to second embodiments, the anode terminals of the thyristors (transfer thyristor T, write thyristor M, light-emitting thyristor L, permission thyristor Sa, Sb) are described as the common anode for the substrate 80. The cathode common with the cathode terminal as the substrate 80 can also be used by changing the polarity of the circuit.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image forming process part, 11 ... Image forming unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part, 62 ... Circuit board, 63 ... Light emitting unit, 64 ... rod lens array, 65 ... light emitting device, 110 ... signal generating circuit, 120 ... transfer signal generating unit, 130 ... permission signal generating unit, 140 ... lighting signal generating unit, 150 ... write signal generating unit, φ1 (Φ1a, φ1b) ... first transfer signal, φ2 (φ2a, φ2b) ... second transfer signal, φE ... allow signal, φW (φW1-φW20) ... write signal, φe ... erase signal, φI (φIa, φIb) ... Lighting signal, Ca1 to Ca20, Cb1 to Cb20 ... Light emitting chip, L ... Light emitting thyristor, T ... Transfer thyristor, M ... Write thyristor, Sa, Sb ... Enable thyristor, Dx ... Coupling diode, Dy ... connecting diode, Dz ... connecting diode, Vga ... power supply potential, Vsub ... reference potential

Claims (9)

A first light-emitting chip group including a plurality of first light-emitting chips, each of which includes a plurality of light-emitting elements, and lighting is permitted at a first potential level;
A second light-emitting chip group including a plurality of second light-emitting chips, each of which includes a plurality of light-emitting elements, and lighting is permitted at a second potential level;
The plurality of first light emitting chips belonging to the first light emitting chip group and the plurality of second light emitting chips belonging to the second light emitting chip group include the period of the first potential level and the second A permission signal supply means for commonly transmitting a permission signal having a potential level period;
The first potential is applied to a plurality of sets each composed of a first light emitting chip belonging to the first light emitting chip group and a second light emitting chip belonging to the second light emitting chip group. During the level period, the light-emitting elements of the first light-emitting chip belonging to the first light-emitting chip group are set to be lit or not lit, and during the second potential level period, A light-emitting device comprising: a write signal supply means for commonly transmitting a write signal for each of the groups, in which a light-emitting element of the second light-emitting chip to which the light-emitting element belongs is set to be turned on or off. The plurality of first light emitting chips belonging to the first light emitting chip group are provided with a first transfer signal that sequentially designates each light emitting element of the plurality of first light emitting chips to be turned on or off. First transfer signal supply means for transmitting in common;
The plurality of second light emitting chips belonging to the second light emitting chip group are provided with a second transfer signal for designating each light emitting element of the plurality of second light emitting chips as a target to be turned on or off in order. The light-emitting device according to claim 1, further comprising second transfer signal supply means for transmitting in common.   The second transfer signal supply means transmits the second transfer signal by shifting the timing on the time axis with respect to the first transfer signal transmitted by the first transfer signal supply means. The light-emitting device according to claim 2. First lighting signal supply means for commonly transmitting a first lighting signal for supplying power for lighting to the plurality of first light emitting chips belonging to the first light emitting chip group;
And a second lighting signal supply means for commonly transmitting a second lighting signal for supplying power for lighting to the plurality of second light emitting chips belonging to the second light emitting chip group. The light-emitting device according to any one of claims 1 to 3.   The second lighting signal supply means transmits the second lighting signal by shifting the timing on the time axis with respect to the first lighting signal transmitted by the first lighting signal supply means. The light-emitting device according to claim 4. The first light emitting chip is:
A substrate,
A plurality of transfer thyristors provided on the substrate, each having a first gate terminal, a first anode terminal, and a first cathode terminal;
A plurality of first electrical means provided on the substrate and interconnecting the first gate terminals of the respective transfer thyristors of the plurality of transfer thyristors;
Provided on the substrate, each having a second gate terminal, a second anode terminal, and a second cathode terminal, the first gate terminal of each of the plurality of transfer thyristors, A plurality of write thyristors each connected to a second gate terminal via a second electrical means;
Provided on the substrate, each having a third gate terminal, a third anode terminal, and a third cathode terminal, and the second gate terminal of each write thyristor of the plurality of write thyristors; A plurality of light-emitting thyristors each connected to the third gate terminal via a third electrical means;
One end of a write signal line provided on the substrate and connected to either the second anode terminal or the second cathode terminal of each write thyristor of the plurality of write thyristors and the write A write resistor provided between the write signal terminal to which the signal is transmitted;
A first permission resistor and a second permission resistor provided on the substrate and connected in series between one end of the write signal line and a permission signal terminal to which the permission signal is transmitted;
A fourth gate terminal, a fourth anode terminal, and a fourth cathode terminal are provided on the substrate, and one of the fourth anode terminal and the fourth cathode terminal is the first gate terminal. The light-emitting device according to claim 1, further comprising: a first permission thyristor connected to a connection point between the permission resistor and the second permission resistor. The second light emitting chip is
A substrate,
A plurality of transfer thyristors provided on the substrate, each having a first gate terminal, a first anode terminal, and a first cathode terminal;
A plurality of first electrical means provided on the substrate and interconnecting the first gate terminals of the respective transfer thyristors of the plurality of transfer thyristors;
Provided on the substrate, each having a second gate terminal, a second anode terminal, and a second cathode terminal, the first gate terminal of each of the plurality of transfer thyristors, A plurality of write thyristors each connected to a second gate terminal via a second electrical means;
Provided on the substrate, each having a third gate terminal, a third anode terminal, and a third cathode terminal, and the second gate terminal of each write thyristor of the plurality of write thyristors; A plurality of light-emitting thyristors each connected to the third gate terminal via a third electrical means;
One end of a write signal line provided on the substrate and connected to either the second anode terminal or the second cathode terminal of each write thyristor of the plurality of write thyristors and the write A write resistor provided between the write signal terminal to which the signal is transmitted;
A third permission resistor and a permission diode provided on the substrate and connected in series between one end of the write signal line and a permission signal terminal to which the permission signal is transmitted;
A fifth gate terminal, a fifth anode terminal, and a fifth cathode terminal are provided on the substrate, and the fifth gate terminal is at a connection point between the third permission resistor and the permission diode. A second permission thyristor connected via a fourth permission resistor;
6. The device according to claim 1, further comprising a fifth permission resistor provided between the fifth gate terminal and a permission signal terminal to which the permission signal is transmitted. Light-emitting device. A first light-emitting chip group including a plurality of first light-emitting chips, each of which includes a plurality of light-emitting elements and which is allowed to be lit at a first potential level, and each of which includes a plurality of light-emitting elements, and A second light-emitting chip group including a plurality of second light-emitting chips permitted to be lit at a potential level of 2, the plurality of first light-emitting chips belonging to the first light-emitting chip group, and the second Permission signal supply means for commonly transmitting a permission signal having a period of the first potential level and a period of the second potential level to the plurality of second light emitting chips belonging to the light emitting chip group, Is a first potential level for a plurality of sets, each consisting of a first light emitting chip belonging to the first light emitting chip group and a second light emitting chip belonging to the second light emitting chip group. During the period The light emitting elements of the first light emitting chip belonging to the first light emitting chip group are set to be lit or not lit, and the second light emitting element belonging to the second light emitting chip group in the period of the second potential level. And a writing signal supply means for transmitting a writing signal for setting the light emitting element of the light emitting chip to be turned on or off in common for each set, and exposing the image carrier to form an electrostatic latent image Exposure means to perform,
And an optical unit that forms an image of light emitted from the exposure unit on the image carrier. Charging means for charging the image carrier;
A first light-emitting chip group including a plurality of first light-emitting chips, each of which includes a plurality of light-emitting elements and which is allowed to be lit at a first potential level, and each of which includes a plurality of light-emitting elements, and A second light-emitting chip group including a plurality of second light-emitting chips permitted to be lit at a potential level of 2, the plurality of first light-emitting chips belonging to the first light-emitting chip group, and the second Permission signal supply means for commonly transmitting a permission signal having a period of the first potential level and a period of the second potential level to the plurality of second light emitting chips belonging to the light emitting chip group, Is a first potential level for a plurality of sets, each consisting of a first light emitting chip belonging to the first light emitting chip group and a second light emitting chip belonging to the second light emitting chip group. During the period The light emitting elements of the first light emitting chip belonging to the first light emitting chip group are set to be lit or not lit, and the second light emitting element belonging to the second light emitting chip group in the period of the second potential level. And a write signal supply means for transmitting a write signal for setting the light emitting element of the light emitting chip to be turned on or off in common for each set, and exposing the image carrier to form an electrostatic latent image. Exposure means to form;
Optical means for imaging light emitted from the exposure means on the image carrier;
Developing means for developing the electrostatic latent image formed on the image carrier;
An image forming apparatus comprising: a transfer unit that transfers an image developed on the image carrier to a transfer target.

Images