JP2017054995A - Light emitting component, print head, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light emitting component that has improved the operation speed compared with a case where the width of transistors is not made larger than the width of gates.SOLUTION: A light emitting chip U comprises a plurality of light emitting thyristors L1, L2, L3, ... that are arranged in rows; and a plurality of coupling transistors Q1, Q2, Q3, ... that are provided corresponding to the plurality of light emitting thyristors L1, L2, L3, ..., respectively and control lighting of the plurality of light emitting thyristors L1, L2, L3, .... Gates of the plurality of light emitting thyristors L1, L2, L3, ... and the plurality of transistors Q1, Q2, Q3, ... are arranged in parallel within an interval of the arrangement of the plurality of light emitting thyristors L1, L2, L3, ..., and the width of the coupling transistors Q1, Q2, Q3 is set larger than the width of a first gate Gtf1 (Glf1).SELECTED DRAWING: Figure 6

Description

  The present invention relates to a light emitting component, a print head, and an image forming apparatus.

  In Patent Document 1, a large number of light-emitting elements each composed of a first transistor and a second transistor are arranged one-dimensionally, two-dimensionally, or three-dimensionally, and the first transistor of the first transistor of each light-emitting element is arranged. One control electrode is connected to a second control electrode of the second transistor of at least two light emitting elements located in the vicinity of a certain direction with respect to each light emitting element via a third transistor; And a light emitting element array to which a clock line for applying a clock pulse from the outside is connected, wherein the first transistor and the third transistor of the light emitting element constitute a current mirror circuit and emit light in a light emitting state. When the clock pulse is applied to the third transistor connected to the element, the potential of the second control electrode of another light emitting element to which the third transistor is connected Self-scanning light-emitting element array is controlled to be a light emitting state is described.

  Patent Document 2 discloses a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, a third semiconductor layer of the first conductivity type, and a second conductivity type of the first semiconductor layer. Each of the fourth semiconductor layers is configured by a semiconductor stacked body sequentially stacked, and each of the semiconductor stacked bodies is configured by a plurality of light emitting thyristors that emit light having a predetermined wavelength in an ON state. A plurality of transfer thyristors that sequentially turn on so that the on-state is transferred and set the corresponding light-emitting thyristors in a state in which the corresponding light-emitting thyristors can be turned on, and the first semiconductor layer in the semiconductor stack Each of the second semiconductor layer and the third semiconductor layer, and the plurality of transfer thyristors are adjacent to each other in the order in which the ON state sequentially shifts, When the previous transfer thyristor is turned on and is turned on, the first semiconductor layer and the second semiconductor layer are continuous with the previous transfer thyristor. A light emitting component is described that includes a plurality of coupled transistors that are continuous with a thickness that causes a third semiconductor layer to be depleted when no potential is applied.

Japanese Patent No. 2784011 JP 2014-216439 A

By the way, in a light-emitting component in which a light-emitting part in which a plurality of light-emitting elements are arranged is controlled by a transfer part including a transistor, the charge / discharge speed of the transistor becomes a rule, and the operation speed is sometimes limited. Therefore, an increase in the current amplification factor of the transistor and a reduction in load capacitance have been demanded.
An object of the present invention is to provide a light-emitting component and the like whose operation speed is improved as compared with a case where the width of a transistor is not larger than the width of a gate.

The invention according to claim 1 is a plurality of light emitting thyristors arranged in a row, a plurality of transistors provided for each light emitting thyristor of the plurality of light emitting thyristors, and controlling lighting of the light emitting thyristor; Each of the light emitting thyristors of the plurality of light emitting thyristors and each of the plurality of transistors are arranged in parallel within an interval of the arrangement of the plurality of light emitting thyristors, and the width of the transistor is The light-emitting component is set to be larger than the width of the gate.
According to a second aspect of the present invention, each transfer thyristor of the plurality of transfer thyristors provided for each of the light emitting thyristors of the plurality of light emitting thyristors intersects the arrangement direction of the transistors and the plurality of light emitting thyristors. 2. The light-emitting component according to claim 1, wherein the transfer thyristor is set to be smaller than a width of the transistor.
The invention according to claim 3 is a plurality of light emitting thyristors arranged in a row, a plurality of transistors provided for each of the light emitting thyristors of the plurality of light emitting thyristors, and controlling the lighting of the light emitting thyristors; A light emitting means including: an optical means for forming an image of light emitted from the light emitting means, and a gate of each light emitting thyristor of each of the plurality of light emitting thyristors, and each transistor of the plurality of transistors, The print head is characterized in that the plurality of light emitting thyristors are arranged in parallel to the direction in which the light emitting thyristors are arranged, and the width of the transistor is set larger than the width of the gate.
According to a fourth aspect of the present invention, there is provided an image carrier, charging means for charging the image carrier, a plurality of light emitting thyristors arranged in a row, and a light emitting thyristor of each of the plurality of light emitting thyristors. And a plurality of transistors that control lighting of the light-emitting thyristor, and an exposure unit that exposes the image carrier through optical means, and a static image that is exposed to the exposure unit and formed on the image carrier. A developing unit that develops the electrostatic latent image; and a transfer unit that transfers the image developed on the image holding member to a transfer target; a gate of each light emitting thyristor of the plurality of light emitting thyristors; Each of the transistors is arranged in parallel with the direction in which the plurality of light emitting thyristors are arranged, and the width of the transistor is larger than the width of the gate. An image forming apparatus characterized by being constant.

According to the first aspect of the present invention, it is possible to provide a light emitting component having an improved operation speed as compared with the case where the width of the transistor is not larger than the width of the gate.
According to the second aspect of the present invention, it is possible to provide a light-emitting component having an improved operation speed as compared with the case where the width of the transfer thyristor is not smaller than the width of the transistor.
According to the invention of claim 3, it is possible to provide a print head having an improved operation speed as compared with the case where the width of the transistor is not larger than the width of the gate.
According to the fourth aspect of the present invention, it is possible to provide an image forming apparatus in which the operation speed is improved as compared with the case where the width of the transistor is not larger than the width of the gate.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. It is sectional drawing which showed the structure of the print head. It is a top view of a light-emitting device. It is the figure which showed the structure of the light emitting chip | tip, the structure of the signal generation circuit of a light-emitting device, and the structure of the wiring (line) on a circuit board. (A) shows the configuration of the light-emitting chip, and (b) shows the configuration of the signal generation circuit of the light-emitting device and the configuration of wiring (lines) on the circuit board. It is an equivalent circuit diagram for demonstrating the circuit structure of the light emitting chip | tip in which the self-scanning light emitting element array (SLED) to which 1st Embodiment is applied is mounted. It is an example of the planar layout figure and sectional drawing of the light emitting chip to which 1st Embodiment is applied. (A) is a plane layout view of the light-emitting chip, and (b) is a cross-sectional view taken along line VIB-VIB shown in (a). It is a figure explaining a transfer thyristor and a coupling transistor. (A) is a diagram in which transfer thyristors and coupling transistors are represented by equivalent transistor symbols, and (b) is a diagram in which the transfer thyristors are represented by thyristor symbols and adjacent transfer thyristors are added in (a). FIG. 6C is a cross-sectional view of the transfer thyristor and the coupling transistor. 6 is a timing chart for explaining operations of the light emitting device and the light emitting chip. It is sectional drawing explaining the manufacturing method of the light emitting chip to which 1st Embodiment is applied. (A) is a semiconductor laminated body formation process, (b) is a 1st gate and collector extraction etching process, (c) is a separate etching process, (d) is an island etching process. It is a figure which expands and shows a 1st island. (A) is a light emitting chip to which the first embodiment is applied, and (b) is a light emitting chip to which the first embodiment is not applied. It is a figure which shows the light emitting chip which made the width | variety of the transfer thyristor small compared with the light emitting chip to which 1st Embodiment is applied. (A) is a top view of a light emitting chip, (b) is a figure which expands and shows a 1st island.

In image forming apparatuses such as printers, copiers, and facsimiles that employ an electrophotographic system, electrostatic latent images are obtained by irradiating image information on a charged photoreceptor with light of a predetermined wavelength by an optical recording means. After the image is obtained, toner is added to the electrostatic latent image to be visualized, and the image is formed by transferring and fixing on the recording paper. In addition to an optical scanning method in which a laser is used as the optical recording means and exposure is performed by scanning a laser beam in the main scanning direction, in recent years, a light emitting diode (LED: Light) as a light emitting element has been received in response to a request for downsizing of the apparatus. A recording apparatus using an LED print head (LPH: LED Print Head) in which a plurality of Emitting Diodes (LEDs) are arranged in the main scanning direction to form a light emitting element array is employed.
A light-emitting thyristor is used as a light-emitting element in a light-emitting chip on which a plurality of light-emitting elements are provided in a row on a substrate and a self-scanning light-emitting element array (SLED) that is sequentially controlled to light is mounted.
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of an overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at predetermined intervals. The image forming unit 11 includes four image forming units 11Y, 11M, 11C, and 11K. The image forming units 11Y, 11M, 11C, and 11K have predetermined surfaces of the photosensitive drum 12 and the photosensitive drum 12 as an example of an image holding body that forms an electrostatic latent image and holds a toner image, respectively. An example of a charging unit 13 as an example of a charging unit that charges at a potential, a print head 14 that exposes a photosensitive drum 12 charged by the charging unit 13, and an example of a developing unit that develops an electrostatic latent image obtained by the print head 14 The developing device 15 is provided. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, the sheet conveying belt 21 that conveys the recording sheet 25, the driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25 are exemplified. A transfer roll 23 and a fixing device 24 for fixing the toner image on the recording paper 25 are provided.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the print head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. Electrostatic transfer is sequentially performed by the transfer electric field, and a composite toner image in which toner of each color is superimposed on the recording paper 25 is formed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing device 24 by heat and pressure and discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing the configuration of the print head 14. The print head 14 as an example of an exposure unit is an example of a light emitting unit including a light source unit 63 including a housing 61 and a plurality of light emitting elements (light emitting thyristors in the first embodiment) that expose the photosensitive drum 12. The light emitting device 65 and the rod lens array 64 as an example of optical means for imaging the light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
The light emitting device 65 includes a circuit board 62 on which the above-described light source unit 63, a signal generation circuit 110 (see FIG. 3 described later) for driving the light source unit 63, and the like are mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and the light emitting surface of the light emitting element of the light source unit 63 (the surface of a region 311 in FIG. 6 described later) is the focal plane of the rod lens array 64. It is set to become. Further, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction and the X direction in FIGS. 3 and 4B described later).

(Light emitting device 65)
FIG. 3 is a top view of the light emitting device 65.
In the light-emitting device 65 shown as an example in FIG. 3, the light source unit 63 includes light-emitting chips U <b> 1 to U <b> 40 as examples of 40 light-emitting components on a circuit board 62. Arranged in a shape.
In the present specification, “to” indicates a plurality of constituent elements each distinguished by a number, and includes those described before and after “to” and those between them. For example, the light emitting chips U1 to U40 include the light emitting chip U1 to the light emitting chip U40 in numerical order.

The configuration of the light emitting chips U1 to U40 may be the same. Therefore, when the light emitting chips U1 to U40 are not distinguished from each other, they are referred to as light emitting chips U.
In the first embodiment, a total of 40 light emitting chips U are used, but the present invention is not limited to this.
The light emitting device 65 includes a signal generation circuit 110 that drives the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). Note that the light emitting device 65 does not have to include the signal generation circuit 110. At this time, the signal generation circuit 110 is provided outside the light emitting device 65 and supplies a control signal and the like for controlling the light emitting chips U1 to U40 via a cable or the like. Here, it is assumed that the light emitting device 65 includes the signal generation circuit 110.
Details of the arrangement of the light emitting chips U1 to U40 will be described later.

  FIG. 4 is a diagram illustrating a configuration of the light emitting chip U, a configuration of the signal generation circuit 110 of the light emitting device 65, and a configuration of wiring (lines) on the circuit board 62. 4A shows the configuration of the light-emitting chip U, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light-emitting device 65 and the configuration of wiring (lines) on the circuit board 62.

First, the configuration of the light-emitting chip U shown in FIG.
The light emitting chip U has a plurality of light emitting elements (in the first embodiment, light emitting thyristors L1, L2, L3) arranged in a row along the long side on one long side on the surface having a rectangular surface shape. ,...)). Further, the light emitting chip U has terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) which are a plurality of bonding pads for taking in various control signals and the like at both ends in the long side direction of the surface. . These terminals are provided in order of the φ1 terminal and the Vga terminal from one end of the light emitting chip U, and are provided in the order of the φI terminal and the φ2 terminal from the other end. The light emitting unit 102 is provided between the Vga terminal and the φ2 terminal. Further, a back electrode 85 (see FIG. 6 described later) is provided as a Vsub terminal on the back surface.

  Note that the “column shape” is not limited to the case where a plurality of light emitting elements are arranged in a straight line as illustrated in FIG. 4A, and the light emitting elements of the plurality of light emitting elements are arranged in the column direction. You may arrange | position with the mutually different deviation | shift amount with respect to the orthogonal direction. For example, when a light emitting surface of a light emitting element (surface of a region 311 in FIG. 6 described later) is a pixel, each light emitting element is arranged with a shift amount of several pixels or several tens of pixels in a direction orthogonal to the column direction. May be. Moreover, you may arrange | position zigzag alternately between adjacent light emitting elements or for every some light emitting element.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62 will be described with reference to FIG.
As described above, the signal generating circuit 110 and the light emitting chips U1 to U40 are mounted on the circuit board 62 of the light emitting device 65, and wirings (lines) for connecting the signal generating circuit 110 and the light emitting chips U1 to U40 are provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
Image signal processed image data and various control signals are input to the signal generation circuit 110 from the image output control unit 30 and the image processing unit 40 (see FIG. 1). The signal generation circuit 110 performs rearrangement of image data, correction of light quantity, and the like based on these image data and various control signals.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips U1 to U40 based on various control signals.
The signal generation circuit 110 includes a lighting signal generation unit 140 that transmits the lighting signals φI1 to φI40 to the light emitting chips U1 to U40 based on various control signals. When the lighting signals φI1 to φI40 are not distinguished from each other, they are expressed as a lighting signal φI.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 that supplies a reference potential Vsub that serves as a potential reference to the light emitting chips U1 to U40, and a power supply potential that supplies a power supply potential Vga for driving the light emitting chips U1 to U40. A supply unit 170 is provided.

Next, the arrangement of the light emitting chips U1 to U40 will be described.
The odd-numbered light emitting chips U1, U3, U5,... Are arranged in a line at intervals in the long side direction of each light emitting chip U. The even-numbered light emitting chips U2, U4, U6,... Are similarly arranged in a row at intervals in the long side direction of each light emitting chip U. The odd numbered light emitting chips U1, U3, U5,... And the even numbered light emitting chips U2, U4, U6,... Are arranged so that the long sides on the light emitting unit 102 side provided in the light emitting chip U face each other. They are arranged in a zigzag pattern in a state rotated by 180 °. The light emitting elements are also arranged between the light emitting chips U at predetermined intervals in the main scanning direction (X direction). In FIG. 4B, the light emitting chips U1, U2, U3,... Are arranged with the arrangement of the light emitting elements of the light emitting unit 102 shown in FIG. 4A (in the first embodiment, the light emitting thyristors L1, L2, L3). ,... In numerical order) are indicated by arrows.

A wiring (line) connecting the signal generation circuit 110 and the light emitting chips U1 to U40 will be described.
The circuit board 62 is provided with a power supply line 200a that is connected to a back electrode 85 (see FIG. 6 described later) that is a Vsub terminal provided on the back surface of the light emitting chip U and supplies a reference potential Vsub.
The circuit board 62 is provided with a power supply line 200b that is connected to a Vga terminal provided in the light emitting chip U and supplies a power supply potential Vga for driving.

  The circuit board 62 includes a first transfer signal line 201 for transmitting the first transfer signal φ1 from the transfer signal generator 120 of the signal generation circuit 110 to the φ1 terminals of the light emitting chips U1 to U40, and the light emitting chips U1 to U40. A second transfer signal line 202 for transmitting the second transfer signal φ2 to the φ2 terminal is provided.

  Further, the lighting signals φI1 to φI40 are transmitted to the circuit board 62 from the lighting signal generator 140 of the signal generation circuit 110 to the respective φI terminals of the light emitting chips U1 to U40 via the current limiting resistors RI. Lighting signal lines 204-1 to 204-40 are provided.

The reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips U1 to U40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted in common (in parallel) to the light emitting chips U1 to U40. On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips U1 to U40, respectively.
When the light emitting device 65 does not include the signal generation circuit 110, the light emitting device 65 includes power supply lines 200a and 200b, a first transfer signal line 201, a second transfer signal line 202, and lighting signal lines 204-1 to 204-1. 204-40 is connected to a connector or the like instead of the signal generation circuit 110. And it connects to the signal generation circuit 110 provided outside by the cable connected to a connector etc.

(Light emitting chip U)
FIG. 5 is an equivalent circuit diagram for explaining a circuit configuration of the light-emitting chip U on which the self-scanning light-emitting element array (SLED) to which the first embodiment is applied is mounted. Each element described below is arranged based on a layout (see FIG. 6 described later) on the light emitting chip U except for terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. The Vsub terminal provided on the back surface of the light emitting chip U is drawn out of the light emitting chip U.
Here, the light emitting chip U will be described by taking the light emitting chip U1 as an example in relation to the signal generation circuit 110. Therefore, in FIG. 5, the light emitting chip U is referred to as a light emitting chip U <b> 1 (U). The configuration of the other light emitting chips U2 to U40 is the same as that of the light emitting chip U1.

The light-emitting chip U1 (U) is a light-emitting thyristor array (light-emitting unit 102 (see FIG. 4A), which is composed of the light-emitting thyristors L1, L2, L3,. )).
The light emitting chip U1 (U) includes a transfer thyristor array composed of transfer thyristors T1, T2, T3,... Arranged in a row like the light emitting thyristor array.

Further, the light emitting chip U1 (U) pairs two transfer thyristors T1, T2, T3,... In the order of numbers, and coupling transistors Q1, Q2, Q3,. It has.
Further, the light emitting chip U1 (U) includes power line resistances Rg1, Rg2, Rg3,.

  The light emitting chip U1 (U) includes one start resistor R0. In order to prevent an excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 to be described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. Current limiting resistors R1 and R2.

The light emitting thyristors L1, L2, L3,... Of the light emitting thyristor array and the transfer thyristors T1, T2, T3,... Of the transfer thyristor array are arranged in numerical order from the left side in FIG. Further, the coupling transistors Q1, Q2, Q3,... And the power line resistances Rg1, Rg2, Rg3,.
The light emitting thyristor array and the transfer thyristor array are arranged in the order of the transfer thyristor array and the light emitting thyristor array from the top in FIG.

  Here, when the light emitting thyristors L1, L2, L3,..., The transfer thyristors T1, T2, T3,..., The coupling transistors Q1, Q2, Q3,... And the power line resistances Rg1, Rg2, Rg3,. The light-emitting thyristor L, the transfer thyristor T, the coupling transistor Q, and the power line resistance Rg are expressed.

The number of light emitting thyristors L in the light emitting thyristor array may be a predetermined number. In the first embodiment, if the number of light emitting thyristors L is, for example, 128, the number of transfer thyristors T is also 128. Similarly, the number of power supply line resistances Rg is 128. However, the number of coupling transistors Q is 127, which is one less than the number of transfer thyristors T.
The number of transfer thyristors T may be larger than the number of light emitting thyristors L.
FIG. 5 shows a portion centering on the light emitting thyristors L1 to L4 and the transfer thyristors T1 to T4.

The thyristor (light emitting thyristor L, transfer thyristor T) is a semiconductor element having a first gate, a second gate, an anode, and a cathode. The coupling transistor Q is a semiconductor element having a collector, a base, and an emitter.
As will be described later, when a p-type ohmic electrode or an n-type ohmic electrode is provided in the semiconductor layer corresponding to the first gate, the second gate, the anode, the cathode, the collector, the base, and the emitter, and connected by wiring In other cases, they are connected to each other through a semiconductor layer.
Here, the thyristor (light-emitting thyristor L, transfer thyristor T) and the coupling transistor Q are represented by circuit symbols, and the first gate (Glf, Gtf described later) and second gate of the thyristor (light-emitting thyristor L, transfer thyristor T). Symbols may not be used for the anode and cathode except for (Gts described later). Similarly, symbols may not be written for the emitter and base except for the collector (C described later) of the coupling transistor Q.

Next, electrical connection of each element in the light emitting chip U1 (U) will be described.
The anodes of the transfer thyristor T and the light-emitting thyristor L are connected to the back electrode 85 of the light-emitting chip U1 (U) (anode common). The emitter of the coupling transistor Q is also connected to the back electrode 85 of the light emitting chip U1 (U).
These anodes are connected to a power supply line 200a (see FIG. 4B) through a back electrode 85 (see FIG. 6 described later) which is a Vsub terminal. The power supply line 200a is supplied with the reference potential Vsub from the reference potential supply unit 160.

Along with the arrangement of the transfer thyristors T, the cathodes of the odd-numbered (odd-numbered) transfer thyristors T1, T3,... Are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1. The first transfer signal line 201 (see FIG. 4B) is connected to the φ1 terminal, and the first transfer signal φ1 is transmitted from the transfer signal generator 120.
On the other hand, the cathodes of the even-numbered (even-numbered) transfer thyristors T2, T4,... Are connected to the second transfer signal line 73 along the arrangement of the transfer thyristors T. The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2. The second transfer signal line 202 (see FIG. 4B) is connected to the φ2 terminal, and the second transfer signal φ2 is transmitted from the transfer signal generator 120.

  The cathode of the light emitting thyristor L is connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. In the light emitting chip U1, the φI terminal is connected to the lighting signal line 204-1 (see FIG. 4B) via the current limiting resistor RI, and the lighting signal φI1 is transmitted from the lighting signal generating unit 140. The lighting signal φI1 supplies a current for lighting to the light emitting thyristor L. The lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips U2 to U40 via current limiting resistors RI, respectively, and the lighting signals φI2 to φI40 are transmitted from the lighting signal generator 140. Is done.

  Each of the first gates Gtf1, Gtf2, Gtf3,... Of the transfer thyristors T1, T2, T3,... Is set to 1 for the first gates Glf1, Glf2, Glf3, etc. of the light emitting thyristors L1, L2, L3,. Connected in a one-to-one relationship. Therefore, the first gates Gtf1, Gtf2, Gtf3,... Of the transfer thyristors T1, T2, T3,... And the first gates Glf1, Glf2, Glf3, etc. of the light emitting thyristors L1, L2, L3,. Are at the same potential. Therefore, for example, the first gate Gtf1 (Glf1) is expressed to indicate that the potentials are the same.

A coupling transistor Q1 is connected between the second gate Gts1 of the transfer thyristor T1 and the first gate Gtf2 of the transfer thyristor T2. The second gate Gts1 of the transfer thyristor T1 is connected to the base of the coupling transistor Q1, and the first gate Gtf2 of the transfer thyristor T2 is connected to the collector C1 of the coupling transistor Q1.
Similarly, the coupling transistor Q is connected between two transfer thyristors T having two or more consecutive numbers.

Also here, when the first gates Gtf1, Gtf2, Gtf3,..., The second gates Gts1, Gts2, Gts3,..., The first gates Glf1, Glf2, Glf3,. Gts is expressed as the first gate Glf. The first gate Gtf (Glf) is represented by the same potential. In addition, the first gate Gtf (Glf) may be expressed as a gate.
The light-emitting thyristor L also has a second gate, but is not connected to other elements, so that no reference numeral is given.

  The first gate Gtf of the transfer thyristor T and the first gate Glf of the light emitting thyristor L are connected to the power supply line 71 via the power supply line resistance Rg provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to the Vga terminal. The Vga terminal is connected to the power supply line 200b (see FIG. 4B), and the power supply potential Vga is supplied from the power supply potential supply unit 170.

  The first gate Gtf1 of the transfer thyristor T1 at one end of the transfer thyristor array is connected to one terminal of the start resistor R0. On the other hand, the other terminal of the start resistor R 0 is connected to the second transfer signal line 73.

  In FIG. 5, a portion including the transfer thyristor T, the coupling transistor Q, the power supply line resistor Rg, the start resistor R0, and the current limiting resistors R1 and R2 of the light emitting chip U1 (U) is referred to as a transfer unit 101. A portion including the light emitting thyristor L corresponds to the light emitting unit 102.

FIG. 6 is an example of a plan layout view and a cross-sectional view of the light emitting chip U to which the first embodiment is applied. 6A is a plan layout view of the light-emitting chip U, and FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG.
Here, since the connection relationship between the light emitting chip U and the signal generation circuit 110 is not shown, it is not necessary to use the light emitting chip U1 as an example. Therefore, it is expressed as a light emitting chip U.

In the plan layout diagram of the light-emitting chip U shown in FIG. 6A, the portions centering on the light-emitting thyristors L1 to L4 and the transfer thyristors T1 to T4 are shown. The light emitting thyristors L1 to L4 are arranged in the x direction. The x direction is the direction of the main scanning direction (X) in FIGS. 3 and 4.
The positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. A Vsub terminal provided on the back surface of the p-type first semiconductor layer 81 is drawn out from the p-type first semiconductor layer 81. If terminals are provided corresponding to FIG. 4A, the φ2 terminal, φI terminal, and current limiting resistor R2 are provided at the right end of the p-type first semiconductor layer 81 in FIG. 6A. The start resistor R0 is placed at the end of the transfer thyristor array on the side where transfer is started.
In FIG. 6A, the wiring (power supply line 71, first transfer signal line 72, second transfer signal line 73, lighting signal line 75, etc.) is indicated by a broken line so that the structure below the wiring can be understood. doing.

  In the cross-sectional view shown in FIG. 6B, the light-emitting thyristor L1, the transfer thyristor T1, the coupling transistor Q1, and the power supply line resistance Rg2 are shown from the bottom in the figure. In FIGS. 6A and 6B, element names, the first gate Gtf1 of the transfer thyristor T1, the first gate Glf1 of the light emitting thyristor L1, and the collector C1 of the coupling transistor Q1 are shown. .

As shown in FIG. 6B, the light emitting chip U includes a p-type first semiconductor layer 81, an n-type second semiconductor layer 82, a p-type third semiconductor layer 83, and an n-type fourth semiconductor layer 84. Is composed of a plurality of island regions (islands) (a first island 301, a second island 302, a third island 303, etc., which will be described later) formed by separating semiconductor stacked bodies stacked in order. The first semiconductor layer 81 also serves as a substrate. That is, as shown in FIG. 6B, at least the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer 84 are separated from each other in the plurality of islands. Has been. The p-type first semiconductor layer 81 is partially removed in the thickness direction. Further, a p-type semiconductor layer may be provided between the p-type first semiconductor layer 81 also serving as the substrate and the n-type second semiconductor layer 82.
As will be described later, in these islands, part or all of the n-type fourth semiconductor layer 84 or the p-type third semiconductor layer 83 is removed, so that the light-emitting thyristor L, the transfer thyristor T, the coupling transistor Q A power line resistance Rg and the like are configured.

  As shown in FIG. 6B, the light emitting chip U is provided with an insulating layer 86 so as to cover the surface and side surfaces of these islands. These islands and wirings are connected through through holes (indicated by “◯” in FIG. 6A) provided in the insulating layer 86. In the following description, description of the insulating layer 86 and the through hole is omitted.

  As shown in FIG. 6A, the first island 301 is U-shaped in plan, and the light-emitting thyristor L1 is located at the center of the U-shape on one side of the U-shape (FIG. 6A). A transfer thyristor T1 and a coupling transistor Q1 are provided on the right side.

The second island 302 and the third island 303 have a planar shape in which square portions at both ends (upper and lower sides in FIG. 6A) are connected, and the power line resistance Rg1 is connected to the second island 302, A power line resistance Rg <b> 2 is provided on the three islands 303.
The fourth island 304, the fifth island 305, and the sixth island 306 have the same planar shape as the second island 302 and the third island 303, and the fourth island 304 has a start resistance R0 and the fifth island 305. Is provided with a current limiting resistor R1, and the sixth island 306 is provided with a current limiting resistor R2.

In the light emitting chip U, a plurality of islands similar to the first island 301 and the second island 302 (third island 303) are formed in parallel. These islands have light emitting thyristors L2, L3, L4,..., Transfer thyristors T2, T3, T4,..., Coupling transistors Q2, Q3, Q4,..., Power line resistances Rg3, Rg4, Rg5,. It is provided in the same manner as the island 301 and the second island 302 (third island 303).
Further, as shown in FIG. 6B, a back electrode 85 serving as a Vsub terminal is provided on the back surface of the p-type first semiconductor layer 81.

Here, with reference to FIGS. 6A and 6B, the first island 301 to the sixth island 306 will be described in detail.
In the first island 301 having a U-shape in plan view, the light-emitting thyristor L1 provided in the center of the U-shape has an n-type fourth semiconductor layer with the p-type first semiconductor layer 81 as an anode and the periphery removed. 84 region 311 is the cathode. An n-type ohmic electrode 321 is provided on the region 311 of the n-type fourth semiconductor layer 84. The p-type first semiconductor layer 81 may be referred to as an anode layer, the n-type fourth semiconductor layer 84 as a cathode layer, and the n-type ohmic electrode 321 as a cathode.
Further, the p-type third semiconductor layer 83 is the first gate Glf1, and the U of the first island 301 is formed on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84. A p-type ohmic electrode 331 is provided along the inside of the letter. The p-type ohmic electrode 331 extends to the vicinity of the transfer thyristor T1 provided at the center portion on one side of the U shape (right side in FIG. 6A), and the other side of the U shape (FIG. 6). On the left side in (a), it extends to the end of the U-shape. The p-type third semiconductor layer 83 may be referred to as a first ohmic layer, and the p-type ohmic electrode 331 may be referred to as a first gate Glf1. The n-type second semiconductor layer 82 is the second gate Gls1. Note that the n-type second semiconductor layer 82 may be referred to as a second gate layer.

  The light emitting thyristor L emits light at the interface between the n-type second semiconductor layer 82 and the p-type third semiconductor layer 83. Light is transmitted through the insulating layer 86 and emitted from the surface (light emitting surface) of the region 311 of the n-type fourth semiconductor layer 84 serving as the cathode. Note that, in the region 311 of the n-type fourth semiconductor layer 84, the portion covered by the n-type ohmic electrode 321 and the branch portion 75 b for connecting the lighting signal line 75 and the n-type ohmic electrode 321 is light emission. Is disturbed.

The transfer thyristor T1 is provided at the center of one side of the U-shape (the right side in FIG. 6A) in the first island 301. In the portion where the transfer thyristor T1 is provided, the p-type first semiconductor layer 81 serves as an anode, and the region 312 of the n-type fourth semiconductor layer 84 excluding the periphery serves as a cathode. An n-type ohmic electrode 322 is provided on the region 312 of the n-type fourth semiconductor layer 84. The p-type first semiconductor layer 81 may be referred to as an anode layer, the n-type fourth semiconductor layer 84 may be referred to as a cathode layer, and the n-type ohmic electrode 322 may be referred to as a cathode.
Further, the p-type third semiconductor layer 83 is the first gate Gtf1. The p-type ohmic electrode 331 on the p-type third semiconductor layer 83 may be referred to as a first gate Gtf1. That is, the first gate Glf1 of the light emitting thyristor L1 and the first gate Gtf1 of the transfer thyristor T1 are common to the p-type ohmic electrode 331. Therefore, the p-type ohmic electrode 331 may be referred to as the first gate Gtf1 (Glf1).
The n-type second semiconductor layer 82 is the second gate Gts1. Note that the n-type second semiconductor layer 82 may be referred to as a second gate layer.

  The coupling transistor Q1 is provided at the end of one side (right side in FIG. 6A) of the U-shaped first island 301 having a U-shaped planar shape. In the portion where the coupling transistor Q1 is provided, the n-type fourth semiconductor layer 84 is removed. The p-type first semiconductor layer 81 is the emitter, the n-type second semiconductor layer 82 is the base, and the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84 is the collector C1. is there. A p-type ohmic electrode 332 is provided on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84. The p-type first semiconductor layer 81 is referred to as an emitter layer, the n-type second semiconductor layer 82 is referred to as a base layer, the p-type third semiconductor layer 83 is referred to as a collector layer, and the p-type ohmic electrode 332 is referred to as a collector C1. There is.

The p-type first semiconductor layer 81 serving as the anode of the light emitting thyristor L1, the p-type first semiconductor layer 81 serving as the anode of the transfer thyristor T1, and the p-type first semiconductor layer 81 serving as the emitter of the coupling transistor Q1. The first semiconductor layers 81 are connected (continuous).
Further, as a base of the n-type second semiconductor layer 82 serving as the second gate Gls1 of the light-emitting thyristor L1, the n-type second semiconductor layer 82 serving as the second gate Gts1 of the transfer thyristor T1, and the coupling transistor Q1. The working n-type second semiconductor layer 82 is connected (continuously).
The portion of the p-type third semiconductor layer 83 serving as the first gate Glf1 of the light emitting thyristor L1 and the portion of the p-type third semiconductor layer 83 serving as the first gate Gtf1 of the transfer thyristor T1 are connected (continuously). Yes.

  As described above, in the first island 301, the first gate Gtf1 (Glf1) and the coupling transistor Q are arranged in parallel with the arrangement direction (x direction) of the light emitting thyristors L. The transfer thyristor T1 and the coupling transistor Q1 are provided in a direction that intersects (or is orthogonal to) the direction (x direction) in which the light emitting thyristors L are arranged. The transfer thyristor T and the coupling transistor Q are arranged in series.

  In the second island 302 provided with the power supply line resistance Rg1, the n-type fourth semiconductor layer 84 is removed. A p-type ohmic electrode 333 and a p-type ohmic electrode 334 are provided on the exposed p-type third semiconductor layer 83. Then, the p-type third semiconductor layer 83 between the p-type ohmic electrode 333 and the p-type ohmic electrode 334 is provided on the p-type third semiconductor layer 83 so as to serve as the power supply line resistance Rg1. The same applies to the third island 303 provided with the power supply line resistance Rg2. That is, the p-type third semiconductor layer 83 between the p-type ohmic electrode 335 and the p-type ohmic electrode 336 provided on the exposed p-type third semiconductor layer 83 is set as the power supply line resistance Rg2. Is provided.

  The start resistor R 0 provided on the fourth island 304, the current limiting resistor R 1 provided on the fifth island 305, and the current limiting resistor R 2 provided on the sixth island 306 are the power line resistance provided on the second island 302. Similarly to Rg1, each of the p-type third semiconductor layers 83 between the two p-type ohmic electrodes (not shown) serves as a resistance.

In FIG. 6A, the connection relationship between each element will be described.
The lighting signal line 75 includes a trunk portion 75a and a plurality of branch portions 75b, and the trunk portion 75a is provided so as to extend in the column direction of the light emitting thyristor row. The branch portion 75 b branches off from the trunk portion 75 a and is connected to the n-type ohmic electrode 321 (cathode) on the region 311 of the n-type fourth semiconductor layer 84 of the light-emitting thyristor L 1 provided on the first island 301. Similarly, the cathodes of the other light emitting thyristors L provided on the same island as the first island 301 are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal.

The first transfer signal line 72 is connected to the n-type ohmic electrode 322 (cathode) on the region 312 of the n-type fourth semiconductor layer 84 of the transfer thyristor T1 provided on the first island 301. The cathodes of other odd-numbered transfer thyristors T provided on an island similar to the first island 301 are also connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided on the fifth island 305.
On the other hand, the second transfer signal line 73 is connected to the cathode of an even-numbered transfer thyristor T provided on an island not labeled. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided on the sixth island 306.

  The power supply line 71 is connected to the p-type ohmic electrode 334 of the power supply line resistance Rg1 provided on the second island 302 and the p-type ohmic electrode 336 of the power supply line resistance Rg2 provided on the third island 303. Other power supply line resistors Rg provided on the same island as the second island 302 (third island 303) are also connected to the power supply line 71 in the same manner. The power supply line 71 is connected to the Vga terminal.

Then, the p-type ohmic electrode 331 (first gate Gtf1 (Glf1)) provided along the inner side of the U-shape of the first island 301 having a U-shape in plan view is the other side of the U-shape (FIG. 6 ( In a), it extends to the end on the left side) and is connected to the p-type ohmic electrode 333 of the power supply line resistance Rg1 provided on the second island 302 by a connection wiring 76.
A p-type ohmic electrode 332 (collector C1 of the coupling transistor Q1) provided at one end of the U-shape of the first island 301 having a U-shape in plan view is a power line provided on the third island 303. A connection wiring 77 is connected to the p-type ohmic electrode 335 of the resistor Rg2.
Although not described here, the same applies to the other light-emitting thyristors L, transfer thyristors T, coupling transistors Q, and power supply line resistors Rg.

The p-type ohmic electrode 331 (first gate Gtf1 (Glf1)) of the first island 301 and the p-type ohmic electrode 333 (one terminal of the power supply line resistance Rg1) of the second island 302 are provided on the fourth island 304. The p-type ohmic electrode (not indicated) of the start resistor R0 is connected by the connection wiring 76 described above. The other terminal of the start resistor R 0 is connected to the second transfer signal line 73.
In this way, the light emitting chip U1 (U) shown in FIG. 5 is configured.

(Transfer thyristor T and coupling transistor Q)
Here, the transfer thyristor T and the coupling transistor Q will be described.
FIG. 7 is a diagram illustrating the transfer thyristor T1 and the coupling transistor Q1. FIG. 7A is a diagram in which the transfer thyristor T1 and the coupling transistor Q1 are represented by equivalent transistor symbols. FIG. 7B is a diagram in which the transfer thyristor T1 is represented by a thyristor symbol and an adjacent transfer thyristor T2 is added in FIG. 7A. FIG. 7C is a cross-sectional view of the transfer thyristor T1 and the coupling transistor Q1. FIG. 7C is an enlarged view of the transfer thyristor T1 and the coupling transistor Q1 in the cross-sectional view of FIG. 6B.
In FIG. 7, for ease of explanation, the anode A1 and cathode K1 of the transfer thyristor T1, the anode A2 and cathode K2 of the transfer thyristor T2, and the emitter E1, base B1, and collector C1 of the coupling transistor Q1 are used.

  As shown in FIG. 7A, the transfer thyristor T1 has a configuration in which a pnp transistor Tr1 and an npn transistor Tr2 are combined. That is, the base of the pnp transistor Tr1 is connected to the collector of the npn transistor Tr2, and the collector of the pnp transistor Tr1 is connected to the base of the npn transistor Tr2. The emitter of the pnp transistor Tr1 is the anode A1 of the transfer thyristor T1, the collector of the pnp transistor Tr1 (base of the npn transistor Tr2) is the first gate Gtf1 of the transfer thyristor T1, and the collector of the npn transistor Tr2 (base of the pnp transistor Tr1). Is the second gate Gts1 of the transfer thyristor T1, and the emitter of the npn transistor Tr2 is the cathode K1 of the transfer thyristor T1. The emitter of the pnp transistor Tr1, which is the anode A1 of the transfer thyristor T1, is connected to the reference potential Vsub.

  The coupling transistor Q1 is a pnp transistor, and the base B1 is connected to the second gate Gts1 of the transfer thyristor T1. The second gate Gts1 of the transfer thyristor T1 is the collector of the npn transistor Tr2 and the base of the pnp transistor Tr1. The emitter E1 of the coupling transistor Q1 is connected to the reference potential Vsub.

  As shown in FIG. 7A, the pnp transistor Tr1 and the coupling transistor Q1 of the transfer thyristor T1 constitute a current mirror circuit. That is, a current proportional to the current flowing through the pnp transistor Tr1 flows through the coupling transistor Q1.

Hereinafter, as an example, the reference potential Vsub supplied to the back electrode 85 (see FIG. 5 and FIG. 6B) which is a Vsub terminal is set to 0V (hereinafter referred to as “H” (0V) or “H” as a high level potential). The power supply potential Vga supplied to the Vga terminal is set to −3.3 V (hereinafter referred to as “L” (−3.3 V) or “L”) as a low level potential. .
As shown in FIG. 6, the thyristor (transfer thyristor T, light-emitting thyristor L) and coupling transistor Q are composed of a p-type semiconductor layer (p-type first semiconductor layer 81, p-type third semiconductor layer 83), n-type. A semiconductor layer (an n-type second semiconductor layer 82 and an n-type fourth semiconductor layer 84) is stacked. These are assumed to be composed of GaAs, GaAlAs, or the like, and a diffusion potential (forward potential) Vd of a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer is set to 1.5 V as an example.

First, the basic operation of the thyristor (transfer thyristor T, light-emitting thyristor L) will be described using the transfer thyristor T1.
The p-type first semiconductor layer 81 that is the anode A1 of the transfer thyristor T1 is at the reference potential Vsub (“H” (0 V)) supplied to the back electrode 85.

In the transfer thyristor T1 in the off state, the current is smaller between the anode A1 and the cathode K1 than in the on state. At this time, the pnp transistor Tr1 and the npn transistor Tr2 constituting the transfer thyristor T1 are in the off state.
Here, it is assumed that the first transfer signal line 72 connected to the cathode K1 of the transfer thyristor T1 becomes “L” (−3.3 V).
At this time, the first gate Gtf1 is a value obtained by adding the diffusion potential Vd (1.5 V) to “L” (−3.3 V), here, higher than −1.8 V (the positive side is said to be high, negative When the potential is low, the emitter-base of the npn transistor Tr2 becomes forward biased and shifts from the off state to the on state. Then, the collector of the npn transistor Tr2 is pulled to the “L” (−3.3 V) side, the emitter (“H” (0 V)) — base of the pnp transistor Tr1 becomes a forward bias, and the pnp transistor Tr1 is also turned off. Transition from state to on state. That is, both the pnp transistor Tr1 and the npn transistor Tr2 are turned on, and the transfer thyristor T1 shifts from the off state to the on state. Transition of the transfer thyristor T1 from the off state to the on state is referred to as turn-on.

In the transfer thyristor T1 in the on state, the first gate Gtf1 becomes a potential close to the potential of the anode A1 (a negative potential whose absolute value is larger than the potential of the anode A1). Here, since the anode A1 is set to the reference potential Vsub (“H” (0 V)), the potential of the first gate Gtf1 is assumed to be “H” (0 V). The second gate Gts1 has a potential (−1.5 V) obtained by subtracting the diffusion potential Vd (1.5 V) of the pn junction from the potential of the anode A1.
The cathode K1 of the transfer thyristor T1 in the ON state has a negative potential (absolute value larger than 1.5V) that is close to the potential obtained by subtracting the diffusion potential Vd (1.5V) from the potential of the anode A1 (“H” (0V)). Potential). The potential of the cathode K1 is set by the current supply capability of the power supply that supplies current to the transfer thyristor T1 in the on state.

  As described above, when a forward bias is applied between the emitter (cathode K1) and base (first gate Gtf1) of the npn transistor Tr2 constituting the transfer thyristor T1, the transfer thyristor T1 is turned on. In order to forward bias between the emitter (cathode K1) and base (first gate Gtf1) of the npn transistor Tr2, the potential of the cathode K1 is obtained by subtracting the diffusion potential Vd (1.5 V) from the first gate Gtf1. It may be lower. A potential obtained by subtracting the diffusion potential Vd (1.5 V) from the potential of the first gate Gtf1 is referred to as a threshold voltage of the transfer thyristor T1. Therefore, the threshold voltage of the transfer thyristor T1 is determined by the potential of the first gate Gtf1, and when the cathode K1 (first transfer signal line 72) is at a potential lower than the threshold voltage, the transfer thyristor T1 is turned on.

In the turned-on transfer thyristor T1, a potential (sustain voltage) lower than the potential obtained by subtracting the diffusion potential Vd (1.5V) from the potential of the anode A1 (“H” (0V)) is applied to the cathode K1, and the power supply is turned on. If the current that can maintain the current (maintenance current) continues to be supplied, the ON state is maintained.
On the other hand, when a potential higher than the potential obtained by subtracting the diffusion potential Vd (1.5 V) from the potential (“H” (0 V)) of the anode A1 is applied to the cathode K1, the transfer thyristor T1 in the on state is turned on. Transition to the off state. Transition of the transfer thyristor T1 from the on state to the off state is referred to as turn-off. For example, when the cathode K1 becomes “H” (0 V), the potential is higher than the sustain voltage (potential lower than −1.5 V) necessary for maintaining the ON state, and the potential of the cathode K1 and the potential of the anode A1 And the transfer thyristor T1 is turned off.

Next, the operation of the coupling transistor Q1 will be described.
When the transfer thyristor T1 is in the off state, the coupling transistor Q1 is also in the off state.
As described above, when the transfer thyristor T1 is turned on, a forward bias is applied between the emitter (anode A1) and the base (second gate Gts1) of the pnp transistor Tr1. Then, since the second gate Gts1 is connected to the base B1 of the coupling transistor Q1, the emitter E1-base B1 of the coupling transistor Q1 is also forward biased, and the coupling transistor Q1 shifts from the off state to the on state.
When the distance between the emitter E1 and the base B1 of the coupling transistor Q1 becomes higher than the potential obtained by subtracting the diffusion potential Vd (1.5 V) from the emitter E1 (“H” (0 V)), the coupling transistor Q1 is turned off from the on state. Migrate to

  Although the transfer thyristor T1 and the coupling transistor Q1 have been described above, the other transfer thyristors T and the coupling transistor Q operate in the same manner. The light emitting thyristor L also operates in the same manner as the transfer thyristor T1.

This will be further described with reference to FIG.
As described above, when the transfer thyristor T1 is turned on, the coupling transistor Q1 shifts from the off state to the on state. The collector C1 of the coupling transistor Q1 is connected to the power supply line 71 of the power supply potential Vga (“L” (−3.3 V)) via the power supply line resistance Rg2 and to the first gate Gtf2 of the transfer thyristor T2. Has been. Therefore, the potential of the collector C1 of the coupling transistor Q1 (the first gate Gtf2 of the transfer thyristor T2) is determined by the current flowing through the coupling transistor Q1 and the power supply line resistance Rg2, and the respective resistances of the coupling transistor Q1 and the power supply line resistance Rg2.

Here, it is assumed that the potential of the collector C1 of the coupling transistor Q1 (the first gate Gtf2 of the transfer thyristor T2) is −1V as an example.
Then, the threshold voltage of the transfer thyristor T2 becomes a potential (−2.5V) obtained by subtracting the diffusion potential Vd (1.5V) from the potential (−1V) of the first gate Gtf2. Therefore, when the potential of the second transfer signal line 73 becomes lower than this potential (−2.5 V), the transfer thyristor T2 is turned on.

  As shown in FIG. 7C, the p-type first semiconductor layer 81 is the anode A1 in the portion where the transfer thyristor T1 is configured, and the emitter E1 in the portion where the coupling transistor Q1 is configured. The n-type second semiconductor layer 82 is the second gate Gts1 in the portion where the transfer thyristor T1 is configured, and the base B1 in the portion where the coupling transistor Q1 is configured. The p-type third semiconductor layer 83 is the first gate Gtf1 in the portion where the transfer thyristor T1 is configured, and the collector C1 in the portion where the coupling transistor Q1 is configured. The n-type fourth semiconductor layer 84 is the cathode K1 in the portion where the transfer thyristor T1 is formed, but is removed in the portion where the coupling transistor Q1 is formed.

As shown in FIG. 7A, since the anode A1 of the transfer thyristor T1 and the emitter E1 of the coupling transistor Q1 are both at the reference potential Vsub (“H” (0V)), the p-type first semiconductor layer 81 is It may be connected (continuously).
Further, as shown in FIG. 7A, the second gate Gts1 of the transfer thyristor T1 and the base B1 of the coupling transistor Q1 are connected. Therefore, the n-type second semiconductor layer 82 is required to be connected (continuously) between the portion where the transfer thyristor T1 is formed and the portion where the coupling transistor Q1 is formed.

On the other hand, as shown in FIG. 7A, the first gate Gtf1 of the transfer thyristor T1 and the collector C1 of the coupling transistor Q1 are not connected. Therefore, the p-type third semiconductor layer 83 is required to be separated by a portion where the transfer thyristor T1 is formed and a portion where the coupling transistor Q1 is formed. In the p-type third semiconductor layer 83, it is only necessary that the portion where the transfer thyristor T1 is formed and the portion where the coupling transistor Q1 is formed are electrically separated.
A distance (interval) _DQ is defined between the cathode K1 of the transfer thyristor T1 and the collector C1 of the coupling transistor Q1.

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the description will be made assuming that the reference potential Vsub is “H” (0 V) and the power supply potential Vga is “L” (−3.3 V). The first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI are described as signals having two potentials of “H” (0 V) and “L” (−3.3 V). Note that “H” (0 V) may be abbreviated as “H” and “L” (−3.3 V) may be abbreviated as “L”.

As described above, the light emitting device 65 includes the light emitting chips U1 to U40 (see FIGS. 3 and 4).
As shown in FIG. 4, the reference potential Vsub (“H” (0 V)) and the power supply potential Vga (“L” (−3.3 V)) are common to all the light emitting chips U1 to U40 on the circuit board 62. To be supplied. Similarly, the first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips U1 to U40.
On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips U1 to U40. The lighting signals φI1 to φI40 are signals for setting the light-emitting thyristors L of the light-emitting chips U1 to U40 to be lit or not lit based on the image data. Therefore, the waveforms of the lighting signals φI1 to φI40 are different depending on the image data. However, the lighting signals φI1 to φI40 are transmitted in parallel at the same timing.
Since the light emitting chips U1 to U40 are driven in parallel, it is sufficient to describe the operation of the light emitting chip U1.

<Timing chart>
FIG. 8 is a timing chart for explaining operations of the light emitting device 65 and the light emitting chip U.
FIG. 8 shows a timing chart of a portion that controls lighting (non-lighting) of the five light emitting thyristors L1 of the light emitting thyristors L1 to L5 of the light emitting chip U1. In FIG. 8, the light emitting thyristors L1, L2, L3, and L5 of the light emitting chip U1 are turned on, and the light emitting thyristor L4 is turned off (not lighted).
As described above, since the other light emitting chips U2 to U40 operate in parallel with the light emitting chip U1, it is sufficient to describe the operation of the light emitting chip U1.

In FIG. 8, it is assumed that time elapses in alphabetical order from time a to time k. The light emitting thyristor L1 is in the period T (1) from time b to time e, the light emitting thyristor L2 is in the period T (2) from time e to time i, and the light emitting thyristor L3 is in the period T (from time i to time j). In 3), the light-emitting thyristor L4 is controlled to be turned on or off (lighting control) in a period T (4) from time j to time k. Thereafter, the light-emitting thyristor L having a number of 5 or more is similarly controlled to be turned on.
Here, the periods T (1), T (2), T (3),... Have the same length, and are referred to as the period T when they are not distinguished from each other.
Note that the lengths of the periods T (1), T (2), T (3),... May be variable as long as the mutual relationship of signals described below is maintained.

  The waveforms of the first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI1 will be described. Note that the period from time a to time b is a period in which the light emitting chip U1 (the same applies to the light emitting chips U2 to U40) is started. The signal in this period will be described in the description of the operation.

  The first transfer signal φ1 transmitted to the φ1 terminal (refer to FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminal (refer to FIGS. 5 and 6) have two continuous periods T (for example, The waveform is repeated with the period T (1) and the period T (2)) as a unit.

The first transfer signal φ1 shifts from “H” to “L” at the start time b of the period T (1), and shifts from “L” to “H” at the time f. Then, at the end time i of the period T (2), the state shifts from “H” to “L”.
The second transfer signal φ2 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time e. Then, “L” is maintained at the end time i of the period T (2).
Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted after the period T on the time axis. The first transfer signal φ1 repeats the waveforms in the period T (1) and the period T (2) after the period T (3). On the other hand, the second transfer signal φ2 repeats the waveform indicated by the broken line in the period T (1) and the waveform in the period T (2) after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that after the period T (3) because the period T (1) is a period during which the light emitting device 65 starts operating.

  As will be described later, a set of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 is transmitted in the ON state by causing the transfer thyristors T shown in FIGS. The light-emitting thyristor L having the same number as the transfer thyristor T is designated as a target for lighting or non-lighting control (lighting control).

  Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip U1 will be described. Note that lighting signals φI2 to φI40 are transmitted to the other light emitting chips U2 to U40, respectively.

Here, the lighting signal φI1 will be described in the lighting control period T (1) for the light emitting thyristor L1 of the light emitting chip U1.
When the light emitting thyristor L1 is turned on, the lighting signal φI1 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time c. Then, it shifts from “L” to “H” at time d and maintains “H” at the end time e of the period T (1).

Now, operations of the light emitting device 65 and the light emitting chip U1 will be described with reference to FIGS. 4 and 5 according to the timing chart shown in FIG. Hereinafter, the periods T (1) and T (2) in which the lighting thyristors L1 and L2 are controlled to be lighted will be described.
(1) Time a
<Light emitting device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub (“H” (0 V)). The power supply potential supply unit 170 sets the power supply potential Vga (“L” (−3.3 V)). Then, the power supply line 200a on the circuit board 62 of the light emitting device 65 becomes the reference potential Vsub (“H” (0 V)), and the Vsub terminals of the light emitting chips U1 to U40 become “H”. Similarly, the power supply line 200b becomes the power supply potential Vga (“L” (−3.3 V)), and the Vga terminals of the light emitting chips U1 to U40 become “L” (see FIG. 4). Thereby, each power supply line 71 of the light emitting chips U1 to U40 becomes “L” (see FIG. 5).

  Then, the transfer signal generator 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H”, respectively. Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). Accordingly, the φ1 terminal and the φ2 terminal of each of the light emitting chips U1 to U40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ2 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIG. 5).

Further, the lighting signal generator 140 of the signal generation circuit 110 sets the lighting signals φI1 to φI40 to “H”, respectively. Then, the lighting signal lines 204-1 to 204-40 become “H” (see FIG. 4). Thereby, each φI terminal of the light emitting chips U1 to U40 becomes “H” via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (see FIG. 5).
8 and the following description, it is assumed that the potential changes stepwise, but the potential gradually changes. Therefore, even when the potential is changing, the thyristor can be turned on or off and the coupling transistor Q can be changed between the on state and the off state if the following conditions are satisfied.

Next, the operation of the light emitting chip U1 will be described.
<Light emitting chip U1>
Since the anodes of the transfer thyristor T and the light emitting thyristor L are connected to the Vsub terminal, they are set to “H” (0 V).

  The cathodes of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H”. The cathodes of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the transfer thyristor T is in the off state because both the anode and the cathode are “H”.

  The cathode of the light emitting thyristor L is connected to the “H” lighting signal line 75. Therefore, the light emitting thyristor L is also in the off state because both the anode and the cathode are “H”.

As described above, the first gate Gtf1 at one end of the transfer thyristor array in FIG. 5 is connected to one terminal of the start resistor R0. The first gate Gtf1 is connected to the power line 71 of “L” (−3.3 V) via the power line resistance Rg1. The other terminal of the start resistor R0 is connected to the second transfer signal line 73 of “H” (0 V) via the current limiting resistor R2. Therefore, the first gate Gtf1 divides the potential difference between “L” (−3.3 V) of the power supply line 71 and “H” (0 V) of the second transfer signal line 73 by the power supply line resistance Rg1 and the start resistance R0. It becomes the electric potential. Since the second transfer signal line 73 is connected to the φ2 terminal of “H” (0V) via the current limiting resistor R2, the first gate Gtf1 is connected to “L” (−3.3V) of the power supply line 71. ) And “H” (0 V) of the φ2 terminal may be a potential divided by the power supply line resistance Rg1, the start resistance R0, and the current limiting resistance R2. Here, it is assumed that the start resistor R0 and the current limiting resistor R2 are smaller than the power supply line resistor Rg1, and the first gate Gtf1 is −1V as an example. Therefore, the threshold voltage of the transfer thyristor T1 is −2.5V.
Note that the potential of the first gate Gtf1 can be set by the power supply line resistance Rg1, the start resistance R0, and the current limiting resistance R2.
Since the first gate Glf1 of the light emitting thyristor L1 is connected to the first gate Gtf1 of the transfer thyristor T1, the threshold voltage of the light emitting thyristor L1 is also −2.5V.

At this time, the anode (p-type first semiconductor layer 81) and the cathode (n-type fourth semiconductor layer 84) are both “H” (0 V), and the transfer thyristor T1 is in the off state. Even when the gate Gtf1 (p-type third semiconductor layer 83) becomes −1V, the second gate Gts1 (n-type second semiconductor layer 82) changes from “H” (0V) to the diffusion potential Vd (1.5V). ) Minus the potential (-1.5V). Therefore, the coupling transistor Q1 cannot be turned on and is in the off state. Note that the first gate Gtf2 of the transfer thyristor T2 is “L” (−3.3 V) of the power supply line 71 via the power supply line resistance Rg2. That is, the threshold voltage of the transfer thyristor T2 is −4.8V. Similarly, the threshold voltages of the other transfer thyristors T3, T4, T5,... Are −4.8V.
Further, the first gates Glf2, Glf3, Glf4,... Of the light emitting thyristors L2, 3, 4,... Are connected to the first gates Gtf2, Gtf3, Gtf4, etc. of the transfer thyristors T2, T3, T4,. Therefore, the threshold voltage is -4.8V.

(2) Time b
At time b shown in FIG. 8, the first transfer signal φ1 shifts from “H” to “L”. Thereby, the light emitting device 65 starts operation.
When the first transfer signal φ1 shifts from “H” to “L”, the potential of the first transfer signal line 72 changes from “H” to “L” (−3.3 V) via the φ1 terminal and the current limiting resistor R1. Migrate to Then, since the potential of the cathode of the transfer thyristor T1 whose threshold voltage is −2.5V becomes “L” (−3.3V), the transfer thyristor T1 is turned on. However, the odd-numbered transfer thyristor T having a cathode connected to the first transfer signal line 72 cannot be turned on because the threshold voltage is −4.8V. On the other hand, the even-numbered transfer thyristor T cannot be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 is “H” (0 V).

  When the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 becomes −1.5 V obtained by subtracting the diffusion potential Vd (1.5 V) from the anode reference potential Vsub (“H” (0 V)). The potential of the first gate Gtf1 becomes “H” (0 V) of the reference potential Vsub (“H” (0 V)) of the anode of the transfer thyristor T1. The potential of the first gate Glf1 of the light emitting thyristor L1 connected to the first gate Gtf1 of the transfer thyristor T1 is also “H” (0 V). Then, the threshold voltage of the light emitting thyristor L1 becomes −1.5V.

On the other hand, when the transfer thyristor T1 is turned on, the coupling transistor Q1 shifts from the off state to the on state. Then, the potential of the collector C1 of the coupling transistor Q1 (the first gate Gtf2 of the transfer thyristor T2) shifts to −1V. As a result, the threshold voltages of the transfer thyristor T2 and the light emitting thyristor L2 become −2.5V.
However, since the second transfer signal line 73 is “H” (0 V), the light emitting thyristor L2 is not turned on.

  Since the transfer thyristor T2 is in the off state, the coupling transistor Q2 is in the off state as described above, and the first gate Gtf3 of the transfer thyristor T3 is “L” (−3.3 V). Therefore, the threshold voltage of the transfer thyristor T3 and the light emitting thyristor L3 is −4.8V. Similarly, the threshold voltage of the transfer thyristor T and the light-emitting thyristor L having a number of 4 or more is −4.8V.

Immediately after time b (in this case, when the thyristor or the like changes due to a change in the signal potential at time b and then enters a steady state), the transfer thyristor T1 and the coupling transistor Q1 are in the on state. The other transfer thyristors T, the coupling transistors Q, and all the light emitting thyristors L are in the off state.
Hereinafter, the transfer thyristor T, the coupling transistor Q, and the light emitting thyristor L in the on state are described, and the transfer thyristor T, the coupling transistor Q, and the light emitting thyristor L in the off state are not illustrated.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” to “L”.
When the lighting signal φI1 shifts from “H” to “L”, the lighting signal line 75 shifts from “H” (0 V) to “L” (−3.3 V) via the current limiting resistor RI and the φI terminal. . Then, the light emitting thyristor L1 having a threshold voltage of −1.5 V is turned on and lit (emits light). As a result, the potential of the lighting signal line 75 becomes a potential close to −1.5V (a negative potential having an absolute value greater than 1.5V). The threshold voltage of the light emitting thyristor L2 is -2.5V, but the light emitting thyristor L1 having a high threshold voltage of -1.5V is turned on, and the lighting signal line 75 has a potential close to -1.5V (absolute Therefore, the light-emitting thyristor L2 is not turned on.
Immediately after time c, the transfer thyristor T1 and the coupling transistor Q1 are in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(4) Time d
At time d, the lighting signal φI1 shifts from “L” to “H”.
When the lighting signal φI1 shifts from “L” to “H”, the potential of the lighting signal line 75 shifts from “L” to “H” via the current limiting resistor RI and the φI terminal. Then, since both the anode and the cathode become “H”, the light emitting thyristor L1 is turned off and turned off (not lit). During the lighting period of the light emitting thyristor L1, the lighting signal φI1 from the time c when the lighting signal φI1 shifts from “H” to “L” to the time d when the lighting signal φI1 shifts from “L” to “H” is “ L ".
Immediately after time d, the transfer thyristor T1 and the coupling transistor Q1 are in the on state.

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” to “L”. Here, the period T (1) for controlling the lighting of the light emitting thyristor L1 ends, and the period T (2) for controlling the lighting of the light emitting thyristor L2 starts.
When the second transfer signal φ2 shifts from “H” to “L”, the potential of the second transfer signal line 73 shifts from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage is −2.5V. As a result, the potential of the first gate Gtf2 (Glf2) becomes “H” (0 V). Therefore, the threshold voltage of the light emitting thyristor L2 is −1.5V.
When the transfer thyristor T2 is turned on, the coupling transistor Q2 shifts from the off state to the on state, and the first gate Gtf3 of the transfer thyristor T3 becomes −1V. Therefore, the threshold voltage of the transfer thyristor T3 and the light emitting thyristor L3 becomes −2.5V.
Note that the threshold voltage of the transfer thyristor T and the light-emitting thyristor L having a number of 4 or more is −4.8V.
Since the lighting signal φI1 is “H” (0 V), none of the light emitting thyristors L is lit.
Immediately after time e, the transfer thyristors T1 and T2 and the coupling transistors Q1 and Q2 are in the on state.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L” to “H”.
When the first transfer signal φ1 shifts from “L” to “H”, the potential of the first transfer signal line 72 shifts from “L” to “H” via the φ1 terminal. Then, the transfer thyristor T1 in the on state is turned off because both the anode and the cathode become “H”.
The first gate Gtf1 (Glf1) is connected to the power supply line 71 (“L” (−3.3 V)) via the power supply line resistance Rg1, and “L” (−3.3 V) via the start resistance R0. ) Is connected to the second transfer signal line 73. Therefore, the potential of the first gate Gtf1 (Glf1) is changed from “H” (0 V) to “L” (−3.3 V). As a result, the threshold voltages of the transfer thyristor T1 and the light emitting thyristor L1 become −4.8V.
Immediately after time f, the transfer thyristor T2 is in the ON state.

(7) Others When the lighting signal φI1 shifts from “H” to “L” at time g, the light-emitting thyristor L2 is turned on and lit (emits light) in the same manner as the light-emitting thyristor L1 at time c.
At time h, when the lighting signal φI1 shifts from “L” to “H”, the light emitting thyristor L2 is turned off and turned off, similarly to the light emitting thyristor L1 at time d.
Further, when the first transfer signal φ1 shifts from “H” to “L” at time i, the threshold voltage is −2.5 V, similarly to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. The transfer thyristor T3 is turned on. At this time, the transfer thyristor T1 cannot be turned on because the threshold voltage is −4.8V.
At time i, the period T (2) for controlling the lighting of the light emitting thyristor L2 ends, and the period T (3) for controlling the lighting of the light emitting thyristor L3 starts.
Thereafter, the above description is repeated.

  When the light-emitting thyristor L is not turned on (emitted) but remains turned off (non-lighted), the lighting signal from time j to time k in the period T (4) during which the light-emitting thyristor L4 in FIG. As with φI1, the lighting signal φI may remain “H” (0 V). By doing so, the light-emitting thyristor L4 remains off (not lit) even when the threshold voltage is −1.5V.

As described above, the transfer thyristors T are connected to each other by the coupling transistor Q. Therefore, when the front transfer thyristor T is turned on, the coupling transistor Q shifts from the off state to the on state, and the threshold voltage of the rear transfer thyristor T is increased. Accordingly, at the timing when the first transfer signal φ1 or the second transfer signal φ2 connected to the cathode of the transfer thyristor T at the subsequent stage shifts from “H” (0 V) to “L” (−3.3 V), The transfer thyristor T is turned on.
When the transfer thyristor T is turned on, the first gate Gtf becomes “H” (0 V). Since the first gate Gtf of the transfer thyristor T and the first gate Glf of the light emitting thyristor L are connected, the threshold voltage of the light emitting thyristor L becomes −1.5V. At the timing when the lighting signal φI shifts from “H” (0 V) to “L” (−3.3 V), the light emitting thyristor L is turned on and lights up (emits light).
That is, when the transfer thyristor T is turned on, the light-emitting thyristor L that is the object of lighting control is designated and set to a lighting-enabled state. The lighting signal φI sets the light-emitting thyristor L, which is the target of lighting control and in a lighting-enabled state, to light or not light.
Thus, the lighting or non-lighting of each light-emitting thyristor L is controlled by setting the waveform of the lighting signal φI according to the image data.

In FIG. 5, there is a method in which the first gate Gtf of the transfer thyristor T is sequentially coupled by a diode without using the coupling transistor Q. In this case, a start diode is used instead of the start resistor R0.
In this case, since the diffusion potential of the diode to be coupled is also 1.5 V, the threshold voltage of the transfer thyristor T before being turned on is −3 V, and “1” of the first transfer signal φ1 and the second transfer signal φ2. The difference from “L” (−3.3V) is only −0.3V.
On the other hand, in the light emitting chip U to which the first embodiment is applied, the threshold voltage before the transfer thyristor T is turned on is −2.5 V, and the first transfer signal φ1 and the second transfer signal are the same. The difference between φ2 “L” (−3.3 V) is −0.8 V, which is large in absolute value.

  That is, since the light emitting chip U to which the first embodiment in which the transfer thyristor T is connected by the coupling transistor Q is applied has a wide operation margin, the light emitting chip U is hardly affected by noise and the like, and the transfer thyristor T is turned on in the transfer unit 101. Occurrence of a transfer failure such that state propagation is interrupted is suppressed. Therefore, the malfunction of the print head 14 is suppressed, and the occurrence of disturbance in the formed image is suppressed.

(Method for manufacturing light emitting chip U)
A method for manufacturing the light-emitting chip U to which the first embodiment is applied will be described.
FIG. 9 is a cross-sectional view illustrating a method for manufacturing the light-emitting chip U to which the first embodiment is applied. 9A is a semiconductor stacked body forming process, FIG. 9B is a first gate and collector extraction etching process, FIG. 9C is a separate etching process, and FIG. 9D is an island etching process. It is. FIG. 9 shows the transfer thyristor T1 and the coupling transistor Q1 of the first island 301 in the cross-sectional view shown in FIG. 6B.

  A method for manufacturing the light-emitting chip U to which the first embodiment is applied will be described with reference to FIG. Here, it is assumed that the light emitting chip U is manufactured by photolithography.

  As shown in FIG. 9A, the light emitting chip U is made of a compound semiconductor such as GaAs or GaAlAs, for example, a p-type first semiconductor layer 81, an n-type second semiconductor layer 82, and a p-type third semiconductor layer. A semiconductor stacked body in which 83 and the n-type fourth semiconductor layer 84 are sequentially stacked is formed (semiconductor stacked body forming step).

Next, as shown in FIG. 9B, a partial region of the n-type fourth semiconductor layer 84 is removed to form the p-type that becomes the first gate Gtf1 of the transfer thyristor T and the collector C1 of the coupling transistor Q. A first gate and collector extraction etching for exposing the third semiconductor layer 83 is performed (first gate and collector extraction etching process). In the first gate and collector extraction etching process, etching is performed so as to expose the surface of the p-type third semiconductor layer 83.
Then, an n-type ohmic electrode 322 is formed on the region 312 of the n-type fourth semiconductor layer 84 (cathode layer) serving as a cathode in the portion where the transfer thyristor T1 is configured. Further, a p-type ohmic electrode 331 that functions as the first gate Gtf1 is formed on the exposed third p-type semiconductor layer 83. Then, a p-type ohmic electrode 332 serving as a collector C1 is formed on the exposed p-type third semiconductor layer 83 in a portion where the coupling transistor Q1 is formed.

Then, as shown in FIG. 9C, separation etching for etching a part of the p-type third semiconductor layer 83 is performed to separate the first gate Gtf1 of the transfer thyristor T1 and the collector C1 of the coupling transistor Q1. (Separation etching process).
In the separation etching step, etching is performed so that the surface of the n-type second semiconductor layer 82 is exposed.

Further, as shown in FIG. 9D, the p-type third semiconductor layer 83, the n-type are exposed from the surface of the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84. A second semiconductor layer 82 of
Then, part of the p-type first semiconductor layer 81 is etched to perform island etching for forming the first island 301 (island etching process).
In the island etching process, etching is performed so as to etch a part of the p-type first semiconductor layer 81 in the thickness direction.
Here, the first island 301 including the transfer thyristor T1 and the coupling transistor Q1 has been described as an example. However, the same applies to other islands (second island to sixth island and islands without reference numerals).
An island formed by etching a semiconductor stacked body may be referred to as a mesa, and an etching for forming an island may be referred to as a mesa etching.

  Etching is performed by wet etching using an etchant (etchant), but may be performed by dry etching in which reactive gas is turned into plasma.

(Characteristics of coupling diode Q)
FIG. 10 is an enlarged view showing the first island 301. FIG. 10A shows a light emitting chip U to which the first embodiment is applied, and FIG. 10B shows a light emitting chip U to which the first embodiment is not applied.
10A and 10B, the first island 301 provided with the light-emitting thyristor L1 is defined as a first island 301-1, and an island similar to the first island 301 provided with the light-emitting thyristor L2 is defined as the first island. 301-2. Then, each element (region 311 or the like) constituting the first island 301-1 is marked with -1, and each element constituting the first island 301-2 is marked with -2. When the first islands 301-1 and 301-2 are not distinguished from each other, they are denoted as the first island 301 as before.

In the coupling transistor Q, a distance (interval) _DQ is set and a width _WQ is set. Further, a portion of the first island 301-1 first gate Gtf1 (Glf1) is formed, and the width _{W G.}

As described in FIG. 7B, when the transfer thyristor T1 is in the off state, the coupling transistor Q1 is also in the off state. At this time, the collector C1 of the coupling transistor Q1 and the first gate Gtf2 of the transfer thyristor T2 are at the power supply potential Vga (“L” (−3.3 V)) due to the power supply line resistance Rg2.
When the transfer thyristor T1 is turned on, the coupling transistor Q1 shifts from the off state to the on state. Then, the first gate Gtf2 of the transfer thyristor T2 connected to the collector C1 of the coupling transistor Q1 shifts from the power supply potential Vga (“L” (−3.3V)) to −1V. As described above, −1V is a value determined by the current flowing through the coupling transistor Q1 and the power supply line resistance Rg2 and the respective resistances of the coupling transistor Q1 and the power supply line resistance Rg2.

  In other words, the coupling transistor Q1 is in the first gate Gtf2 of the transfer thyristor T2 (strictly speaking, the first gate Gtf2 (Glf2) including the second gate Glf2 of the light emitting thyristor L2) connected to the collector C1 of the coupling transistor Q1. Then, the electric charge charged by the power supply potential Vga (“L” (−3.3 V)) is extracted, and is shifted to −1 V. That is, the capacitance formed between the third semiconductor layer 83 that functions as the first gate Gtf2 (Glf2) and the first semiconductor layer 81 is a load of the coupling transistor Q1. The capacitance formed between the third semiconductor layer 83 and the first semiconductor layer 81 in the portion where the p-type ohmic electrode 331-2 is formed shown in FIG. 10 is a load of the coupling transistor Q1.

In order to improve the driving speed of the light emitting device 65, that is, the light emitting chip U, it is required to increase the transfer speed (drive speed) of the transfer unit 101 including the transfer thyristor T and the coupling transistor Q.
For this purpose, the driving capability of the coupling transistor Q is improved and the load on the coupling transistor Q is reduced.

The current amplification factor is a driving capability of the coupling transistor Q beta is represented by the formula (1) and the collector current I _C and base current I _B.

The base current I _B is an approximation, is proportional to the cathode current I _K of the transfer thyristors T, the formula (2).

Here, the current amplification factor β ′ of the coupling transistor Q is approximately expressed by Expression (3) with the width W _Q and the interval D _Q of the coupling transistor Q, where a and b are coefficients.

That is, the current amplification factor β ′ increases as the interval D _Q decreases and the width W _Q increases. Therefore, in order to improve the driving capability of the coupling transistor Q, to reduce the distance D _Q, it is possible to set a large width W _Q. The interval _DQ is the distance between the regions where charges are diffused and moved.

On the other hand, the load of the coupling transistor Q1 includes the third semiconductor layer 83 (first gate layer) and the first semiconductor layer 81 (anode layer) of the first gate Gtf2 (Glf2) on which the p-type ohmic electrode 331-2 is formed. a capacitance C _G formed between the. The capacitance _{C G,} since that can be regarded as a plate capacitor, and the surface area _{S G} of a portion which acts as capacitance _{C G} in the first island 301-2 third semiconductor layer 83 (first gate layer) and the first semiconductor layer 81 ( The distance (thickness) d _G between the anode layer and the anode layer is expressed by the equation (4).

That is, the load of the coupling transistor Q1 is smaller the smaller the surface area S _G of a portion which acts as capacitance C _G. Therefore, as shown in FIG. 10 (a), as the width _{W G} of the first gate Gtf2 (Glf2) is small, the surface area _{S G} is reduced, the capacitance _{C G} decreases.

Therefore, in the first embodiment, with respect to the spacing of arranging the light-emitting thyristors L (pitch) p, increasing the width _{W Q} of the coupling transistor Q, the width W of the first gate Gtf2 acting as capacitance _{C G} (Glf2) _G is laid out small. The same applies to the other first gates Gtf (Glf).

The interval p at which the light emitting thyristors L are arranged is determined by the specifications of the light emitting device 65. Therefore, it is not preferable to change the arrangement pitch p.
Therefore, in the light-emitting chip U of the first embodiment, without changing the spacing p of arranging the light-emitting thyristors L, in the interval p, by increasing the width W _Q of the coupling transistor Q, and, as the capacitance C _G By reducing the width W _G of the working first gate Gtf (Glf), the driving capability (current amplification factor β ′) of the coupling transistor Q is increased, and the load capacitance (capacitance C _G ) is decreased.

Figure 10 (b) in the light-emitting chip U first embodiment is not applied as shown in, 'the width _{W G} of the first gate Gtf serve as a capacitor _{C G} (GLF)' width _{W Q} of coupling transistor Q and the same It is laid out in size. In this case, compared to the light emitting chip U to which the first embodiment shown in FIG. 10A is applied, the current amplification factor β ′ of the coupling transistor Q is small and the capacitance _CG is large. . For this reason, the operation speed of the light emitting chip U is slowed down. That is, the operation speeds of the light emitting device 65 and the image forming apparatus 1 are reduced.

[Second Embodiment]
In the light-emitting chip U of the first embodiment is applied, the width W _T of the transfer thyristors T (the transfer thyristor T1 in the case of coupling transistor Q1) is set wide according to the width W _Q of the coupling transistor Q (See FIG. 10A).
However, since the area of the transfer thyristor T (mainly the area of the cathode) is related to the capacity between the cathode and the anode, the operation speed of the transfer thyristor T is affected. That is, the smaller the area of the transfer thyristor T, the faster the operation of the transfer thyristor T. Then, the transfer thyristor T may flow a current that maintains the ON state.
Other configurations are the same as those of the first embodiment. Therefore, the difference from the light emitting chip U to which the first embodiment is applied will be described.

Figure 11 is a view showing a light emitting chip U was smaller than the light-emitting chip U of the width W _T of the transfer thyristor T is the first embodiment is applied. FIG. 11A is a plan view of the light emitting chip U, and FIG. 11B is an enlarged view of the first island 301.
As shown in FIG. 11B, the width W _T ′ of the transfer thyristor T is smaller than the width W _T of the transfer thyristor T in the first embodiment shown in FIG. ing.
Thereby, the turn-on and turn-off speed of the transfer thyristor T is improved.

Note that the width of the p-type third semiconductor layer (p-type gate layer) 83 in the transfer thyristor T may be narrowed in accordance with the width W _T ′ of the transfer thyristor T.
However, as shown in FIG. 11B, in order for the current from the transfer thyristor T1 to the coupling transistor Q1 to flow without being concentrated on a part of the coupling transistor Q1, the p-type of the transfer thyristor T is used. It is not necessary to reduce the width of the third semiconductor layer (p-type gate layer) 83 in accordance with the width W _T ′ of the transfer thyristor T.
That is, as shown in FIG. 11B, a current should flow from the transfer thyristor T1 to the coupling transistor Q1 as indicated by the arrow I.

  In the first and second embodiments, the thyristor (transfer thyristor T, light-emitting thyristor L) is an anode common whose anode is connected to the p-type first semiconductor layer 81 as a substrate, and the coupling transistor Q Has been described as a pnp bipolar transistor. By changing the polarity of the circuit, the thyristor (transfer thyristor T, light-emitting thyristor L) may be a cathode common whose cathode is connected to an n-type semiconductor layer as a substrate, and the coupling transistor Q may be an npn bipolar transistor. .

  In the first embodiment and the second embodiment, the light emitting element is the light emitting thyristor L, and the light emitting element is a light emitting diode (LED) in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. ).

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image formation process part, 11 (11Y, 11M, 11C, 11K) ... Image formation unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing , 62 ... circuit board, 63 ... light source part, 64 ... rod lens array, 65 ... light emitting device, 71 ... power supply line, 72 ... first transfer signal line, 73 ... second transfer signal line, 75 ... lighting signal line, 75a ... trunk part, 75b ... branch part, 81 ... first semiconductor layer, 82 ... second semiconductor layer, 83 ... third semiconductor layer, 84 ... fourth semiconductor layer, 101 ... transfer part, 102 ... light emitting part, 110 ... signal Generation circuit 120... Transfer signal generation unit 140... Lighting signal generation unit 160 .. reference potential supply unit 170 .. power supply potential supply unit .phi.1 first transfer signal .phi.2 second transfer signal .phi.I (.phi.I1 to .phi.I40) ) ... Lighting signal, Gt f (Gtf1, Gtf2, Gtf3,...) ... first gate, Gts (Gts1, Gts2, Gts3,...) ... second gate, L (L1, L2, L3,...) ... light emitting thyristor, T (T1, T2,. T3,...) ... transfer thyristor, Q (Q1, Q2, Q3,...) ... coupling transistor, U (U1-U40) ... light emitting chip, Vga ... power supply potential, Vsub ... reference potential

Claims (4)

A plurality of light emitting thyristors arranged in a line;
A plurality of transistors provided for each light-emitting thyristor of the plurality of light-emitting thyristors and controlling lighting of the light-emitting thyristor,
A gate of each light emitting thyristor of each of the plurality of light emitting thyristors and each transistor of the plurality of transistors are arranged in parallel within an interval of the arrangement of the plurality of light emitting thyristors, and the width of the transistor is equal to that of the gate. A light-emitting component that is set to be larger than the width. Each transfer thyristor of the plurality of transfer thyristors provided for each light emitting thyristor of the plurality of light emitting thyristors is in series with the transistor in a direction intersecting with the arrangement direction of the plurality of light emitting thyristors. Arranged,
The light-emitting component according to claim 1, wherein a width of the transfer thyristor is set smaller than a width of the transistor. A plurality of light emitting thyristors arranged in a row, and a plurality of transistors provided for each of the light emitting thyristors of the plurality of light emitting thyristors to control lighting of the light emitting thyristors;
Optical means for imaging light emitted from the light emitting means,
The gates of the light emitting thyristors of the plurality of light emitting thyristors and the transistors of the plurality of transistors are arranged in parallel to the direction in which the plurality of light emitting thyristors are arranged, and the width of the transistors is A print head characterized in that it is set larger than the width of the gate. An image carrier,
Charging means for charging the image carrier;
A plurality of light emitting thyristors arranged in a row, and a plurality of transistors provided for each light emitting thyristor of the plurality of light emitting thyristors to control lighting of the light emitting thyristor, and through the optical means, Exposure means for exposing the image carrier;
Developing means for developing the electrostatic latent image exposed by the exposure means and formed on the image carrier;
Transfer means for transferring the image developed on the image holding member to a transfer target,
The gates of the light emitting thyristors of the plurality of light emitting thyristors and the transistors of the plurality of transistors are arranged in parallel to the direction in which the plurality of light emitting thyristors are arranged, and the width of the transistors is An image forming apparatus, wherein the image forming apparatus is set larger than a width of a gate.

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