JPH04257239A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04257239A JPH04257239A JP1864491A JP1864491A JPH04257239A JP H04257239 A JPH04257239 A JP H04257239A JP 1864491 A JP1864491 A JP 1864491A JP 1864491 A JP1864491 A JP 1864491A JP H04257239 A JPH04257239 A JP H04257239A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polyimide film
- photoresist
- carbon
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229920001721 polyimide Polymers 0.000 claims abstract description 48
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 25
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000004380 ashing Methods 0.000 claims abstract description 15
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000003960 organic solvent Substances 0.000 claims abstract description 4
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 9
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012778 molding material Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 150000001721 carbon Chemical class 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、高信頼性の半導体装置
を得るための半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for obtaining a highly reliable semiconductor device.
【０００２】0002
【従来の技術】近年、素子の微細化，高密度化に伴って
、半導体素子の応力の影響を受け易くなっている。特に
、拡散工程後の実装工程で、半導体素子にかかる応力が
大きいため、この工程での応力を低減する目的でポリイ
ミド膜が応力緩和材として一般的に用いられている。2. Description of the Related Art In recent years, with the miniaturization and higher density of semiconductor devices, semiconductor devices have become more susceptible to stress. In particular, since the stress applied to semiconductor elements is large in the mounting process after the diffusion process, a polyimide film is generally used as a stress relaxation material for the purpose of reducing the stress in this process.
【０００３】ここでは例として、拡散工程完了後、実装
工程の直前でポリイミド膜を形成する場合について説明
する。[0003] As an example, a case will be described in which a polyimide film is formed after the completion of the diffusion process and immediately before the mounting process.
【０００４】図２は、ボンディングパッド用のＡｌ（ア
ルミニウム）部分での断面図である。図２において、１
は単結晶シリコン、２はＳｉＯ２膜、３はＳｉ，Ｃｕを
含有したＡｌ膜、４はｐ−ＳｉＮ膜、５はポリイミド膜
、６はポリイミド膜５の変質層である。ここで、ボンデ
ィングパッド用Ａｌ膜３の上に、保護膜としてｐ−Ｓｉ
Ｎ膜４が形成されており、さらにその上に応力緩和材と
してのポリイミド膜５が形成されている。ボンディング
パッド用Ａｌ膜３の上部のｐ−ＳｉＮ膜４とポリイミド
膜５は、その後のボンディングのために除去されている
。ここで、ポリイミド膜５は、Ａｌ膜３上を開孔した後
、４００℃で硬化して最終状態のポリイミド膜にするた
め、その硬化の際の炭素系堆積物が先に開孔した領域に
堆積する。Ａｌ膜３上にこの炭素系堆積物が存在すると
、ボンディング材とＡｌ膜３の密着強度が劣化してしま
うため、Ａｌ膜３上の炭素系堆積物を除去する目的で、
オゾンによるアッシングを行ない、先に開孔した領域の
炭素系堆積物を除去していた。FIG. 2 is a cross-sectional view of an Al (aluminum) portion for a bonding pad. In Figure 2, 1
2 is a single crystal silicon, 2 is an SiO2 film, 3 is an Al film containing Si and Cu, 4 is a p-SiN film, 5 is a polyimide film, and 6 is a degraded layer of the polyimide film 5. Here, on the Al film 3 for bonding pad, p-Si is used as a protective film.
An N film 4 is formed, and a polyimide film 5 as a stress relaxation material is further formed thereon. The p-SiN film 4 and polyimide film 5 above the bonding pad Al film 3 are removed for subsequent bonding. Here, the polyimide film 5 is cured at 400° C. after forming holes on the Al film 3 to form the polyimide film in its final state, so that the carbon-based deposits during the curing will cover the area where the holes were formed first. accumulate. If this carbon-based deposit exists on the Al film 3, the adhesion strength between the bonding material and the Al film 3 will deteriorate, so in order to remove the carbon-based deposit on the Al film 3,
Ashing with ozone was performed to remove carbon-based deposits in the area where the holes were previously drilled.
【０００５】なお、炭素系堆積物の膜厚とボンディング
材の密着強度間には、図３のような相関が存在するため
、炭素系堆積物の膜厚は２０Å以下であることが好まし
い。[0005] Since there is a correlation between the thickness of the carbon-based deposit and the adhesion strength of the bonding material as shown in FIG. 3, the thickness of the carbon-based deposit is preferably 20 Å or less.
【０００６】以上の構造のＡｌボンディングパッドにお
いては、Ａｌパッド上の炭素系堆積物は除去できるが、
オゾンアッシングの時に、ポリイミド膜５自体もオゾン
アッシングされるため、ポリイミド膜５の表面の０．３
μｍ以下の領域にポリイミド変質層６ができてしまって
いた。[0006] In the Al bonding pad having the above structure, carbon deposits on the Al pad can be removed, but
During ozone ashing, the polyimide film 5 itself is also ozone ashed, so 0.3% of the surface of the polyimide film 5
A polyimide degraded layer 6 was formed in a region smaller than μm.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、ポリイミド膜５の硬化時に付着する炭素系
堆積物を除去する際に、ポリイミド膜の表面に変質層が
できるため、その後のモールド材との密着性が劣化し、
半導体装置の信頼性上で課題があった。[Problems to be Solved by the Invention] However, in the above-mentioned conventional structure, when removing the carbon-based deposits that adhere to the polyimide film 5 when it hardens, a degraded layer is formed on the surface of the polyimide film, which makes it difficult to use the subsequent molding material. The adhesion of the
There were issues with the reliability of semiconductor devices.
【０００８】本発明は、このような課題を解決するもの
で、Ａｌパッドとボンディング材との密着強度を劣化さ
せることなく、ポリイミド膜とモールド材との密着性を
向上した半導体装置を提供することを目的とする。The present invention is intended to solve these problems, and provides a semiconductor device in which the adhesion between the polyimide film and the molding material is improved without deteriorating the adhesion strength between the Al pad and the bonding material. With the goal.
【０００９】[0009]
【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置の製造方法は、ポリイミド膜の硬
化後にそのポリイミド膜上にフォトリソ法によりフォト
レジストをパターン形成する工程と、オゾンアッシング
法により前述のフォトレジストで覆われた領域以外の領
域のポリイミド膜の硬化時にできた炭素系堆積物を除去
する工程と、フォトレジストを有機溶剤で除去する工程
とを少なくとも有する構成からなる。[Means for Solving the Problems] In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes a step of patterning a photoresist on the polyimide film by photolithography after curing the polyimide film, and ozone ashing. The method includes at least a step of removing carbon-based deposits formed during curing of the polyimide film in areas other than the area covered with the photoresist, and a step of removing the photoresist with an organic solvent.
【００１０】0010
【作用】この構成によって、炭素系堆積物をオゾンアッ
シング法で除去する時、ポリイミド膜の上をフォトレジ
スト膜で保護しているので、ポリイミド膜の表面にポリ
イミド変質層ができない。[Operation] With this structure, when removing carbonaceous deposits by the ozone ashing method, the top of the polyimide film is protected by the photoresist film, so no altered polyimide layer is formed on the surface of the polyimide film.
【００１１】[0011]
【実施例】本発明の半導体装置の製造方法の一実施例を
図１を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
【００１２】まず、図１（ａ）において単結晶シリコン
１上に、ＳｉＯ２膜２を９００〜１０００℃で５０００
〜１００００Å形成する。その後、ＳｉとＣｕを含有し
たＡｌ膜３をスパッタリング法でＳｉＯ２膜２上に堆積
する。この時のスパッタリングの条件は、圧力５〜１０
ｍＴｏｒｒ、パワー５〜１０ＫＷとし、Ａｌ膜３の膜厚
は０．５〜１．０μｍとする。その後、フォトリソ法に
よって、所定の場所のみレジストを残し（図示せず）、
そのレジストをマスクにしてＡｌ膜３をエッチングする
。エッチング後、レジストをアッシングによって除去す
る。
その後、３８０〜４５０℃でＡｌ膜３のシンタリングを
Ｈ２雰囲気で行なう。その後、ｐ−ＳｉＮ膜４を全面に
０．５〜１．５μｍ堆積する。ｐ−ＳｉＮ膜４堆積後、
フォトリソ法によって、ボンディングパッド用Ａｌ上以
外の領域にレジストを残し、ドライエッチによってＡｌ
膜３上のｐ−ＳｉＮ膜４を除去する。その後、アッシン
グレジストを除去する。次に、３８０〜４５０℃のＨ２
雰囲気で熱処理を行ない、拡散工程を完了する。次に全
面にワニス状のポリイミド前駆体（図示せず）をスピン
コート法で５〜１０μｍ塗布する。ここではネガ型、感
光性ポリイミドについて説明する。その後、１００℃で
数分溶剤を揮発させて、ステッパーまたはプロジェクシ
ョンアライナーで露光を行なう。露光時間はステッパー
で５００〜１０００ｍｓｅｃとする。その後、露光され
た領域以外の領域のポリイミド前駆体をＮＭＰ（Ｎ−メ
チル−２−ピロリドン）を含む溶剤によって除去（現像
）する。この時、ボンディングパッド用Ａｌ膜３上のポ
リイミド前駆体は除去しておく。現像後、Ｎ２雰囲気で
３００〜４００℃で前記ポリイミド前駆体を硬化させ、
ポリイミド膜５にする。この時、最終状態でのポリイミ
ド膜５の膜厚は初期のワニス状態での膜厚の半分程度に
なる。この硬化の時に、ワニス状態で含まれていた溶剤
および感光基が揮発し、その一部がウエハ上に炭素系堆
積物７となって付着する。この時の膜厚は５０〜１００
Å程度である。First, in FIG. 1(a), a SiO2 film 2 is formed on a single crystal silicon 1 at a temperature of 900 to 1000°C for 5000°C.
~10000 Å is formed. Thereafter, an Al film 3 containing Si and Cu is deposited on the SiO2 film 2 by sputtering. The conditions for sputtering at this time are a pressure of 5 to 10
mTorr, power is 5 to 10 KW, and the thickness of the Al film 3 is 0.5 to 1.0 μm. After that, by photolithography, resist is left only in predetermined places (not shown).
The Al film 3 is etched using the resist as a mask. After etching, the resist is removed by ashing. Thereafter, the Al film 3 is sintered at 380 to 450° C. in an H2 atmosphere. Thereafter, a p-SiN film 4 is deposited to a thickness of 0.5 to 1.5 μm over the entire surface. After depositing p-SiN film 4,
By photolithography, resist is left in areas other than on the Al for bonding pads, and by dry etching, the Al is removed.
The p-SiN film 4 on the film 3 is removed. After that, the ashing resist is removed. Next, H2 at 380-450℃
Heat treatment is performed in an atmosphere to complete the diffusion process. Next, a varnish-like polyimide precursor (not shown) is applied to the entire surface by spin coating to a thickness of 5 to 10 μm. Here, negative type, photosensitive polyimide will be explained. Thereafter, the solvent is evaporated at 100° C. for several minutes, and exposure is performed using a stepper or projection aligner. Exposure time is set to 500 to 1000 msec using a stepper. Thereafter, the polyimide precursor in areas other than the exposed area is removed (developed) using a solvent containing NMP (N-methyl-2-pyrrolidone). At this time, the polyimide precursor on the bonding pad Al film 3 is removed. After development, the polyimide precursor is cured at 300 to 400°C in an N2 atmosphere,
Polyimide film 5 is used. At this time, the film thickness of the polyimide film 5 in the final state is about half of the film thickness in the initial varnish state. At the time of this curing, the solvent and photosensitive group contained in the varnish state are volatilized, and some of them adhere as carbon-based deposits 7 on the wafer. The film thickness at this time is 50 to 100
It is about Å.
【００１３】次に図（ｂ）に示すように、全面にレジス
ト８を０．５〜１．０μｍスピンコート法で塗布する。
その後、露光，現像によって所定の場所のみ開孔する。
この時、ポリイミド膜５上は全てレジスト８で覆うよう
にして、ボンディングパッド用Ａｌ上のレジスト８は完
全に除去しておく。Next, as shown in Figure (b), a resist 8 is applied to the entire surface to a thickness of 0.5 to 1.0 .mu.m by spin coating. Thereafter, holes are formed only at predetermined locations by exposure and development. At this time, the polyimide film 5 is entirely covered with the resist 8, and the resist 8 on the bonding pad Al is completely removed.
【００１４】次に図１（ｃ）に示すように、オゾンアッ
シング法によって、先のレジスト８のない領域の炭素系
堆積物７を除去する。この時のオゾンアッシング条件は
、基板温度１８０〜２５０℃、アッシング時間１０〜６
０秒程度とする。炭素系堆積物除去後、レジスト８を１
５〜２５℃のアセトンで除去する。アセトンでは、レジ
スト８以外の膜は変質しないため、レジスト以外の膜に
損傷を与えることなく、レジスト８を除去できる。Next, as shown in FIG. 1(c), the carbon-based deposit 7 in the area where the resist 8 is not present is removed by ozone ashing. The ozone ashing conditions at this time are: substrate temperature 180-250℃, ashing time 10-6
It should be about 0 seconds. After removing carbon-based deposits, resist 8
Remove with acetone at 5-25°C. Since acetone does not change the quality of the films other than the resist 8, the resist 8 can be removed without damaging the films other than the resist.
【００１５】以上の構造のボンディングパッドにおいて
は、レジスト８でポリイミド膜５を覆って炭素系堆積物
７を除去するため、ポリイミド膜５の表面を変質させる
ことなくＡｌ膜３上の炭素系堆積物７を除去できる。In the bonding pad having the above structure, since the carbon-based deposits 7 are removed by covering the polyimide film 5 with the resist 8, the carbon-based deposits on the Al film 3 are removed without altering the surface of the polyimide film 5. 7 can be removed.
【００１６】なお、ポリイミド膜５の硬化時にできた炭
素系堆積物７をオゾンアッシング法により除去する際、
炭素系堆積物７を完全に除去する必要は必ずしもなく、
図３に示すように炭素系堆積物の膜厚が２０Å以下であ
ればよい。[0016] When removing the carbon-based deposit 7 formed during curing of the polyimide film 5 by the ozone ashing method,
It is not necessarily necessary to completely remove the carbon-based deposits 7;
As shown in FIG. 3, it is sufficient if the thickness of the carbon-based deposit is 20 Å or less.
【００１７】[0017]
【発明の効果】以上のように本発明の半導体装置の製造
方法は、ポリイミド膜の硬化後にそのポリイミド膜上に
フォトリソ法によりフォトレジストをパターン形成する
工程と、オゾンアッシング法によりフォトレジストで覆
われた領域以外の領域のポリイミド膜の硬化時にできた
炭素系堆積物を除去する工程と、フォトレジストを有機
溶剤で除去する工程とを少なくとも有する構成によるの
で、ポリイミド膜の表面を変質させることなく、炭素系
堆積物を除去できるため、Ａｌ膜とボンディング材との
密着強度を劣化させることなく、ポリイミド膜とモール
ド材との密着性が向上した高信頼性の半導体装置を提供
できる。As described above, the method for manufacturing a semiconductor device of the present invention includes the steps of forming a photoresist pattern on the polyimide film by the photolithography method after curing the polyimide film, and covering the polyimide film with the photoresist by the ozone ashing method. This structure includes at least the step of removing carbon-based deposits formed during curing of the polyimide film in areas other than the areas where the polyimide film is cured, and the step of removing the photoresist with an organic solvent, so that the surface of the polyimide film is not altered. Since carbon-based deposits can be removed, a highly reliable semiconductor device with improved adhesion between the polyimide film and the molding material can be provided without degrading the adhesion strength between the Al film and the bonding material.
【図１】本発明の一実施例の半導体装置の製造方法を示
す工程断面図FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置の断面図[Figure 2] Cross-sectional view of a conventional semiconductor device
【図３】炭素系堆積物の膜厚に対するＡｌパッドとボン
ディング材の密着強度の相関図[Figure 3] Correlation diagram of adhesion strength between Al pad and bonding material with respect to film thickness of carbon-based deposit
１ 単結晶シリコン
２ ＳｉＯ２膜
３ アルミニウム膜（Ｓｉ，Ｃｕ含有）４ ｐ−Ｓ
ｉＮ膜
５ ポリイミド膜
７ 炭素系堆積物
８ レジスト（フォトレジスト）1 Single crystal silicon 2 SiO2 film 3 Aluminum film (containing Si and Cu) 4 p-S
iN film 5 Polyimide film 7 Carbon-based deposit 8 Resist (photoresist)
Claims (2)
のポリイミド膜上にフォトリソ法によりフォトレジスト
をパターン形成する工程と、オゾンアッシング法により
前記フォトレジストで覆われた領域以外の領域のポリイ
ミド膜の硬化時にできた炭素系堆積物を除去する工程と
、前記フォトレジストを有機溶剤で除去する工程とを少
なくとも有することを特徴とする半導体装置の製造方法
。1. A step of forming a pattern of a photoresist on the polyimide film by photolithography after curing a polyimide film as an insulating film, and forming a pattern of the polyimide film in an area other than the area covered with the photoresist by an ozone ashing method. A method for manufacturing a semiconductor device, comprising at least the steps of removing carbon-based deposits formed during curing, and removing the photoresist with an organic solvent.
で覆われた領域以外の領域のポリイミド膜の硬化時にで
きた炭素系堆積物を除去する工程が、オゾンアッシング
法によりフォトレジストで覆われた領域以外の領域のポ
リイミド膜の硬化時にできた炭素系堆積物の膜厚が２０
Å以下になるように除去する工程であることを特徴とす
る請求項１記載の半導体装置の製造方法。2. The step of removing carbon-based deposits formed during curing of the polyimide film in areas other than areas covered with photoresist by ozone ashing is performed in areas other than areas covered with photoresist by ozone ashing. The film thickness of carbon-based deposits formed during curing of the polyimide film in the area is 20%.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing is performed so that the thickness is less than .ANG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1864491A JPH04257239A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1864491A JPH04257239A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04257239A true JPH04257239A (en) | 1992-09-11 |
Family
ID=11977319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1864491A Pending JPH04257239A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04257239A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009290040A (en) * | 2008-05-30 | 2009-12-10 | Renesas Technology Corp | Method for manufacturing semiconductor integrated circuit device |
| JP2020044464A (en) * | 2018-09-14 | 2020-03-26 | 株式会社Ｓｃｒｅｅｎホールディングス | Processing device, processing system and processing method |
-
1991
- 1991-02-12 JP JP1864491A patent/JPH04257239A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009290040A (en) * | 2008-05-30 | 2009-12-10 | Renesas Technology Corp | Method for manufacturing semiconductor integrated circuit device |
| JP2020044464A (en) * | 2018-09-14 | 2020-03-26 | 株式会社Ｓｃｒｅｅｎホールディングス | Processing device, processing system and processing method |
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