JPH0293081A - Method for etching multilayer film - Google Patents
Method for etching multilayer filmInfo
- Publication number
- JPH0293081A JPH0293081A JP24101988A JP24101988A JPH0293081A JP H0293081 A JPH0293081 A JP H0293081A JP 24101988 A JP24101988 A JP 24101988A JP 24101988 A JP24101988 A JP 24101988A JP H0293081 A JPH0293081 A JP H0293081A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- etched
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000005530 etching Methods 0.000 title claims description 25
- 239000010408 film Substances 0.000 claims abstract description 36
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 238000004380 ashing Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Weting (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜の配線を形成するエツチング技術に係り
、形状的欠陥を防止し信頼性の高い薄膜のパターンを得
るエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an etching technique for forming thin film wiring, and more particularly to an etching method for preventing geometrical defects and obtaining a highly reliable thin film pattern.
従来技術における多層配線パターン形成法を第2図及び
第3図に示す。多層膜の配線パターンをウェットエツチ
ングにより形成する場合、第3図に示す様に1層ずつレ
ジストを形成する方法があるが、この方法では工程が増
えコストに問題がある。そこで共通レジストにより2層
の膜をエツチングすると等方性エツチングのため下層膜
のサイドエッチを生じ、その結果上層膜のオーバハング
が出来、その後の工程における不良の原因となる。A conventional multilayer wiring pattern forming method is shown in FIGS. 2 and 3. When forming a wiring pattern of a multilayer film by wet etching, there is a method of forming resist layer by layer as shown in FIG. 3, but this method increases the number of steps and has a cost problem. Therefore, when two layers of films are etched using a common resist, side etching of the lower film occurs due to isotropic etching, resulting in overhang of the upper film, which causes defects in subsequent steps.
この問題を解決する方法として、特開昭60−2349
82号において、共通レジストにおいて上層膜をウェッ
トエツチングし、下層膜を異方性エツチングを特徴とし
たドライエツチングを行うことにより、その問題を解決
し、安定なパターンを形成出来ることが述べられている
。しかしこの方法の場合には、工程が複雑で製造コスト
について配慮がなされていなかった。As a method to solve this problem,
In No. 82, it is stated that this problem can be solved and a stable pattern can be formed by wet etching the upper layer of a common resist and dry etching the lower layer, which is characterized by anisotropic etching. . However, in the case of this method, the process was complicated and no consideration was given to manufacturing costs.
上記従来技術を用いて、コストを重視して2層の膜を同
一レジストによりエツチングした場合、下層膜が上層膜
よりサイドエッチしてしまい、上層膜のパターン端部に
オーバハングが出来てしまう。そのため後の工程でその
オーバハングがはがれ、線間ショート及びレジスト不良
等の原因となり機能を果たす薄膜回路を得ることが困難
であった。また、他の方法では工程数が増え製造コスト
が高くなる。本発明の目的は、上記問題を解決し容易な
方法で多層膜配線を得ることにある。When using the above-mentioned conventional technique and etching two layers of films using the same resist with emphasis on cost, the lower layer will be side-etched more than the upper layer, resulting in overhangs at the pattern ends of the upper layer. Therefore, the overhang peels off in a later process, causing short circuits between lines and resist defects, making it difficult to obtain a functional thin film circuit. In addition, other methods increase the number of steps and increase manufacturing costs. An object of the present invention is to solve the above-mentioned problems and obtain multilayer film wiring by an easy method.
上記目的は以下の手段により達成される。まず、2層の
膜をジャスエツチングでパターンを形成したのち、レジ
ストパターンの端部を02アツシング処理により後退さ
せることによりレジストパターンを1〜数μm狭くする
。その結果、上層のオーバハング部分が露出するので、
この部分をエツチングすることによりオーバーハング部
分を除去し、安定な配線パターンとする。The above objective is achieved by the following means. First, a pattern is formed on the two-layer film by JAS etching, and then the ends of the resist pattern are set back by 02 ashing process to narrow the resist pattern by 1 to several μm. As a result, the overhang part of the upper layer is exposed, so
By etching this part, the overhang part is removed and a stable wiring pattern is obtained.
従来方法では、レジストをマスクとしてまず上層膜をエ
ツチングし、続いて下層膜は上層膜がマスクとなりエツ
チングが行なわれるため、サイドエッチが進みオーバハ
ングが生じ、この部分が不良の原因となった。In the conventional method, the upper layer film is first etched using a resist as a mask, and then the lower layer film is etched using the upper layer film as a mask, so side etching progresses and overhang occurs, which causes defects.
そこで上下層を通常通りジャストエツチングを行い、次
に02アツシング処理を行う。この処理により、レジス
トは数μm削られ、パターンの端部はレジストが薄いた
め、レジストが無くなりパターンが狭くなる。この処理
のためオーバハング部分が露出し、エツチングされやす
くなる。その後、このオーバーハング部分をエツチング
して除去するのであるが、オーバーハング部分が除去さ
れ易い状態であるために下層の更に下にある層が上層と
同じ材料であっても、この層が上層の膜厚と同等以上の
膜厚があれば良好な配線パターンを形成することも可能
となる。Therefore, the upper and lower layers are just etched as usual, and then the 02 ashing process is performed. By this process, the resist is shaved off by several micrometers, and since the resist is thin at the edges of the pattern, the resist disappears and the pattern becomes narrower. This process exposes the overhanging portion, making it susceptible to etching. This overhanging part is then removed by etching, but because the overhanging part is easily removed, even if the layer further below the lower layer is of the same material as the upper layer, this layer will be removed by etching. If the film thickness is equal to or greater than the film thickness, it is also possible to form a good wiring pattern.
以下、本発明の一実施例を第1図により説明する。図中
に示すようにCuとCrの2層配線を形成する場合、ま
ず基板上にCuとCrの配線となるべき金属膜をスパッ
タ等により成膜する。An embodiment of the present invention will be described below with reference to FIG. As shown in the figure, when forming a two-layer interconnection of Cu and Cr, first, a metal film to become the interconnection of Cu and Cr is formed on a substrate by sputtering or the like.
成膜した膜の上に所望の配線レジストパターン膜4を形
成する。次にCrとCuをそれぞれの所定のエツチング
液によりジャストエツチングを行う。A desired wiring resist pattern film 4 is formed on the formed film. Next, Cr and Cu are just etched using respective predetermined etching solutions.
基板乾燥後、02プラズマアッシングを10分間処理を
行う、この処理により、レジストパターンは初期の状態
より2〜3μm程度細くなり、Cu膜のエツチング時に
生じたサイドエツチングの結果出来るCr膜のオーバハ
ング部分が露出し、オーバーハング部分のエツチングが
容易に出来る状態になる。After drying the substrate, perform 02 plasma ashing for 10 minutes. Through this process, the resist pattern becomes thinner by about 2 to 3 μm than the initial state, and the overhang part of the Cr film that is created as a result of side etching that occurs when etching the Cu film is removed. This will expose the overhang and allow for easy etching.
次に02プラズマアッシングにより露出したCr膜のオ
ーバハング部分をCrの所定のエツチング液により、エ
ツチングを行う。この時のエツチングは最初に行なった
Cr膜のエツチング時間より短時間にエツチング出来る
。その後レジスト膜をレジスト除去液により、通常の処
理により除去する。本実施例によれば1層のレジストに
より2層の膜を理想的な形にフォトエツチングが出来、
レジスト膜形成工程を減らすことが出来る。Next, the overhanging portion of the Cr film exposed by the 02 plasma ashing is etched using a predetermined Cr etching solution. Etching at this time can be performed in a shorter time than the etching time of the Cr film that was performed first. Thereafter, the resist film is removed using a resist removal solution through normal processing. According to this example, two layers of films can be photo-etched into an ideal shape using one layer of resist.
The number of resist film forming steps can be reduced.
本発明によれば、−回のレジスト形成工程により、二層
の膜を理想的なエツチングが出来るため工程の[1化が
出来る。更に一層ごとにレジス1−を形成しエツチング
する方法に比ベレジスト形成の工程における位置ずれが
無いため精度よく細い配線パターンが作ることが出来る
。またその後のフォトエツチング工程に全く支障を与え
ることなく進めることが出来、信頼性も増しコスト低減
になる。According to the present invention, the two-layer film can be ideally etched through the resist forming process twice, so that the number of steps can be reduced to one. Furthermore, compared to the method of forming and etching the resist 1- layer by layer, there is no positional shift in the process of forming the resist, so it is possible to form fine wiring patterns with high accuracy. Furthermore, the subsequent photoetching process can be carried out without any hindrance, increasing reliability and reducing costs.
第1図は1本発明の一実施例の工程図、第2、第3図は
従来技術の例を示す工程図である。
1・・・上層膜、2・・・下層膜、3・・・基板、4・
・・レジスト膜、1′−・上層膜(Cr)、2′−下層
膜(Cu)。
3′・・基板、4′・・・レジスト膜。FIG. 1 is a process diagram of one embodiment of the present invention, and FIGS. 2 and 3 are process diagrams showing an example of the prior art. DESCRIPTION OF SYMBOLS 1... Upper layer film, 2... Lower layer film, 3... Substrate, 4...
...Resist film, 1'--upper layer film (Cr), 2'--lower layer film (Cu). 3'...Substrate, 4'...Resist film.
Claims (1)
を構成する材料が同一のエッチング液で同時にエッチン
グ出来ない膜構成の場合において、隣接する2つの層を
同一のレジストによってウェットエッチングによりパタ
ーン形成する際に、該2層をジャストエッチングを行っ
た後、O_2プラズマアッシング処理を行い、レジスト
パターンの形状を適度に縮小し、上層のオーバハング部
分を露出させ、その後上層のエッチング液によりエッチ
ングを行い、上層のひさし状部分を除去することを特徴
とする多層膜のエッチング法。1. In the case of a film structure that has at least two or more thin film layers and the materials constituting each layer cannot be etched simultaneously with the same etching solution, two adjacent layers are patterned by wet etching with the same resist. After just etching the two layers, O_2 plasma ashing is performed to reduce the shape of the resist pattern to expose the overhang part of the upper layer, and then the upper layer is etched with an etching solution to remove the upper layer. A multilayer film etching method characterized by removing the eaves-like parts of the film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24101988A JPH0293081A (en) | 1988-09-28 | 1988-09-28 | Method for etching multilayer film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24101988A JPH0293081A (en) | 1988-09-28 | 1988-09-28 | Method for etching multilayer film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0293081A true JPH0293081A (en) | 1990-04-03 |
Family
ID=17068126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24101988A Pending JPH0293081A (en) | 1988-09-28 | 1988-09-28 | Method for etching multilayer film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0293081A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002252231A (en) * | 1998-05-29 | 2002-09-06 | Samsung Electronics Co Ltd | Method of forming thin film transistor for liquid crystal display device |
JP2008124299A (en) * | 2006-11-14 | 2008-05-29 | Toppan Printing Co Ltd | Manufacturing method of emi shield member and the emi shield member, and image display device |
KR20130126479A (en) * | 2012-05-10 | 2013-11-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for forming wiring, semiconductor device, and method for manufacturing semiconductor device |
JP6126315B1 (en) * | 2013-11-25 | 2017-05-10 | アーカーカー ゲゼルシャフト ミット ベシュレンクテル ハフツングAKK GmbH | Stencil for forming surface structure by etching |
-
1988
- 1988-09-28 JP JP24101988A patent/JPH0293081A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002252231A (en) * | 1998-05-29 | 2002-09-06 | Samsung Electronics Co Ltd | Method of forming thin film transistor for liquid crystal display device |
JP2008124299A (en) * | 2006-11-14 | 2008-05-29 | Toppan Printing Co Ltd | Manufacturing method of emi shield member and the emi shield member, and image display device |
KR20130126479A (en) * | 2012-05-10 | 2013-11-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for forming wiring, semiconductor device, and method for manufacturing semiconductor device |
JP2013254946A (en) * | 2012-05-10 | 2013-12-19 | Semiconductor Energy Lab Co Ltd | Method for forming wiring, semiconductor device, and method for manufacturing semiconductor device |
US20150111340A1 (en) * | 2012-05-10 | 2015-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming wiring, semiconductor device, and method for manufacturing semiconductor device |
JP6126315B1 (en) * | 2013-11-25 | 2017-05-10 | アーカーカー ゲゼルシャフト ミット ベシュレンクテル ハフツングAKK GmbH | Stencil for forming surface structure by etching |
JP2017515967A (en) * | 2013-11-25 | 2017-06-15 | アーカーカー ゲゼルシャフト ミット ベシュレンクテル ハフツングAKK GmbH | Stencil for forming surface structure by etching |
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