JPH05308182A - Manufacture of film circuit board - Google Patents
Manufacture of film circuit boardInfo
- Publication number
- JPH05308182A JPH05308182A JP7972392A JP7972392A JPH05308182A JP H05308182 A JPH05308182 A JP H05308182A JP 7972392 A JP7972392 A JP 7972392A JP 7972392 A JP7972392 A JP 7972392A JP H05308182 A JPH05308182 A JP H05308182A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- thin film
- hole
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、薄膜集積回路の製造に
用いられる膜回路基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a membrane circuit board used for manufacturing a thin film integrated circuit.
【０００２】[0002]
【従来の技術】貫通孔で表面と裏面の導体が接続された
従来の膜回路基板の製造方法を図２（ａ）〜（ｄ）を用
いて説明する。2. Description of the Related Art A conventional method of manufacturing a membrane circuit board in which conductors on the front surface and the back surface are connected by through holes will be described with reference to FIGS.
【０００３】まず図２（ａ）に示すように、貫通孔６を
有した多層又は単層のアルミナセラミック基板１に薄膜
抵抗層２としてＴａ2 Ｎ膜をマグネトロンスパッタ法に
より基板の表面及び裏面に付着形成する。次でこの上部
に薄膜導体層７としてＴｉ／Ｐｄ／Ａｕ膜をマグネトロ
ンスパッタ法により基板表面及び裏面に連続して形成す
る。さらに薄膜導体層７の上部にＡｕメッキ層５を２〜
５μｍの厚さに施す。First, as shown in FIG. 2A, a Ta 2 N film as a thin film resistance layer 2 is formed on a front surface and a back surface of a substrate by a magnetron sputtering method on a multilayer or single layer alumina ceramic substrate 1 having a through hole 6. Attach and form. Next, a Ti / Pd / Au film as a thin film conductor layer 7 is continuously formed on the top surface and the back surface of the substrate by magnetron sputtering. Further, the Au plating layer 5 is formed on the thin film conductor layer 7 by 2 to 2
It is applied to a thickness of 5 μm.
【０００４】次に図２（ｂ）に示すように、基板の表面
と裏面にフォトレジスト膜８からなるパターンを形成す
る。次に図２（ｃ）に示すように、このフォトレジスト
膜をマスクとしてＡｕメッキ層５，薄膜導体層７及び薄
膜抵抗層２をエッチングし、貫通孔において導体により
接続された膜回路基板を完成させる。Next, as shown in FIG. 2B, a pattern made of a photoresist film 8 is formed on the front and back surfaces of the substrate. Next, as shown in FIG. 2C, the Au plating layer 5, the thin film conductor layer 7 and the thin film resistance layer 2 are etched using this photoresist film as a mask to complete a film circuit board connected by a conductor in a through hole. Let
【０００５】[0005]
【発明が解決しようとする課題】上述したように膜回路
基板の製造方法としては、一般に貫通孔６の内壁部の導
体がエッチングされないようにフォトレジスト膜８で保
護する必要があるため、スピンナーによる塗布方法やホ
トレジスト溶液中に基板をディッピングする方法により
フォトレジスト膜を５μｍ以上の膜厚に塗布する必要が
ある。しかしながら、貫通孔内壁や貫通孔の角部では、
フォトレジスト膜が極端に薄くなるため、図２（ｄ）に
示すように、Ａｕメッキ層５及び薄膜導体層７の導体膜
が貫通孔の角部で欠損を生じやすいという問題があっ
た。As described above, in the method of manufacturing the membrane circuit board, it is generally necessary to protect the conductor on the inner wall of the through hole 6 with the photoresist film 8 so as not to be etched. It is necessary to apply the photoresist film to a film thickness of 5 μm or more by the application method or the method of dipping the substrate in the photoresist solution. However, at the inner wall of the through hole and the corners of the through hole,
Since the photoresist film is extremely thin, there is a problem that the conductor films of the Au plating layer 5 and the thin film conductor layer 7 are likely to be damaged at the corners of the through holes as shown in FIG. 2 (d).
【０００６】また、この問題点を解決するために、従来
必要以上のフォトレジスト膜厚にすることも試みられて
いるが、ファインパターンが形成できないという問題が
生じている。更に貫通孔の角部を筆などによりフォトレ
ジスト膜で保護して、フォトレジスト膜を補強する方法
がとられてきたが、補強が不完全であるばかりでなく、
多大の工数を必要とするという問題があった。In order to solve this problem, it has been attempted to increase the photoresist film thickness more than necessary, but there is a problem that a fine pattern cannot be formed. Furthermore, a method of reinforcing the photoresist film by protecting the corner portions of the through holes with a photoresist film with a brush etc. has been taken, but not only is the reinforcement incomplete,
There was a problem that a great number of man-hours were required.
【０００７】[0007]
【課題を解決するための手段】本発明の膜回路の形成方
法は、貫通孔が設けられた絶縁性基板の表面と裏面に薄
膜抵抗層を形成する工程と、前記薄膜抵抗層上に第１の
金属層と第２の金属層からなる薄膜導体層を順次形成す
る工程と、前記貫通孔の内部及び前記薄膜導体層上のパ
ターン形成部を除いた領域にメッキ用のフォトレジスト
膜を形成した後パターン形成部にＡｕメッキ層を形成す
る工程と、前記フォトレジスト膜を除去した後前記Ａｕ
メッキ層をマスクとして前記薄膜導体層及び前記薄膜抵
抗層をパターニングする工程とを含むものである。A method of forming a film circuit according to the present invention comprises a step of forming a thin film resistance layer on a front surface and a back surface of an insulating substrate having a through hole, and a first step on the thin film resistance layer. Step of sequentially forming a thin film conductor layer composed of the metal layer and the second metal layer, and forming a photoresist film for plating inside the through hole and in a region on the thin film conductor layer excluding a pattern forming portion. A step of forming an Au plating layer on the rear pattern forming portion, and a step of forming the Au plating layer after removing the photoresist film.
Patterning the thin film conductor layer and the thin film resistance layer using the plating layer as a mask.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）〜（ｄ）は本発明の一実施例を説明する
ための工程順に示した基板の断面図である。The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views of a substrate shown in the order of steps for explaining an embodiment of the present invention.
【０００９】まず図１（ａ）に示すように、貫通孔６を
有したアルミナセラミック基板１の表面と裏面の両面に
薄膜抵抗層２としてＴａ2 Ｎ膜を１００ｎｍの厚さに形
成し、この上部に薄膜導体層３としてまず厚さ１００ｎ
ｍのＴｉ膜を次に厚さ３００ｎｍのＣｕ膜をマグネトロ
ンスパッタ法により付着させる。First, as shown in FIG. 1A, a Ta 2 N film having a thickness of 100 nm is formed as a thin film resistance layer 2 on both the front surface and the back surface of an alumina ceramic substrate 1 having a through hole 6. First, a thin film conductor layer 3 having a thickness of 100 n
Then, a Ti film of m and a Cu film of 300 nm in thickness are deposited by magnetron sputtering.
【００１０】次に図１（ｂ）に示すように、貫通孔内及
び導体パターン部を除いた領域に約８μｍ厚のメッキ用
のフォトレジスト膜４からなるパターンを形成する。Next, as shown in FIG. 1B, a pattern of a photoresist film 4 for plating having a thickness of about 8 μm is formed in the through hole and in the region excluding the conductor pattern portion.
【００１１】次に、図１（ｃ）に示すように、フォトレ
ジスト膜４をマスクとして貫通孔内および導体パターン
とすべき部分に厚さ約５μｍのＡｕメッキ層５を電解メ
ッキ法により形成する。Next, as shown in FIG. 1C, an Au plating layer 5 having a thickness of about 5 μm is formed by electrolytic plating using the photoresist film 4 as a mask in the through holes and in the portions to be conductor patterns. .
【００１２】次に図１（ｄ）に示すように、フォトレジ
スト膜４を除去した後、ＴｉとＣｕの薄膜導体層３及び
薄膜抵抗層２をＡｕメッキ層５をマスクとしてエッチン
グし除去する。これによって、基板の表面と裏面が貫通
孔部においておＡｕメッキ層５で接続された膜回路基板
を得ることができる。Next, as shown in FIG. 1D, after removing the photoresist film 4, the thin film conductor layer 3 and the thin film resistance layer 2 of Ti and Cu are etched and removed using the Au plating layer 5 as a mask. As a result, it is possible to obtain a film circuit board in which the front surface and the back surface of the substrate are connected by the Au plating layer 5 in the through holes.
【００１３】このように本実施例によれば、導体層とな
るＡｕメッキ層のパターンを、従来のようにエッチング
により形成してないため貫通孔の角部におけるＡｕメッ
キ層の欠損をなくすことができる。As described above, according to this embodiment, since the pattern of the Au plating layer to be the conductor layer is not formed by etching as in the conventional case, it is possible to eliminate the defect of the Au plating layer at the corner portion of the through hole. it can.
【００１４】尚、薄膜導体層３としてＴｉとＣｕを使用
することにより、薄膜導体層のパターニングの時に、Ｔ
ｉとＣｕのエッチャントとしてＡｕメッキ層を浸食しな
いエッチャント、例えばＴｉは希硫酸溶液、ＣｕはＨ2
Ｏ2 とＥＤＴＡの混合溶液を選べる利点がある。By using Ti and Cu as the thin film conductor layer 3, it is possible to use T and Cu when patterning the thin film conductor layer.
As an etchant for i and Cu, an etchant that does not erode the Au plating layer, for example, Ti is a dilute sulfuric acid solution, Cu is H 2
There is an advantage that a mixed solution of O 2 and EDTA can be selected.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、貫通孔が
設けられた絶縁性基板の表面と裏面の両面に薄膜抵抗層
を形成し、この上部にＴｉとＣｕの薄膜導体層を形成す
る。そして、貫通孔部及び導体層のパターン形成部を除
いた領域にメッキ用のフォトレジスト膜を形成後Ａｕメ
ッキ層を形成し、続いて薄膜導体層及び薄膜抵抗層をＡ
ｕメッキ層をマスクにして除去するという工程にしたの
で、従来のフォトレジスト膜のパターンだけで貫通孔の
内壁や角部を被覆してエッチングする方法に比べ、本発
明は貫通孔部のＡｕメッキ層をエッチングしないエッチ
ャントを選択できるため、膜の欠損のない信頼性のある
貫通孔部を得ることができ、かつ、フォトレジスト膜の
パターン形状に忠実な導体及び抵抗パターンを基板の表
裏面に形成できるという効果を有する。As described above, according to the present invention, the thin film resistance layers are formed on both the front surface and the back surface of the insulating substrate having the through holes, and the thin film conductor layers of Ti and Cu are formed on the thin film resistance layers. . Then, after forming a photoresist film for plating on a region excluding the through-hole portion and the pattern forming portion of the conductor layer, an Au plating layer is formed, and then the thin film conductor layer and the thin film resistance layer are
Since the step of removing the u-plated layer is used as a mask, the present invention is different from the conventional method in which the inner wall and corners of the through-hole are covered and etched only with the pattern of the photoresist film. Since an etchant that does not etch the layer can be selected, it is possible to obtain a reliable through-hole portion with no defect in the film, and a conductor and resistance pattern that is faithful to the pattern shape of the photoresist film are formed on the front and back surfaces of the substrate. It has the effect of being able to.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施例を説明するための基板の断面
図。FIG. 1 is a sectional view of a substrate for explaining an embodiment of the present invention.
【図２】従来の膜回路基板の製造方法を説明するための
基板の断面図。FIG. 2 is a cross-sectional view of a substrate for explaining a conventional method for manufacturing a membrane circuit substrate.
１ アルミナセラミック基板 ２ 薄膜抵抗層 ３ 薄膜導体層 ４ フォトレジスト膜 ５ Ａｕメッキ層 ６ 貫通孔 ７ 薄膜導体層 ８ フォトレジスト膜 DESCRIPTION OF SYMBOLS 1 Alumina ceramic substrate 2 Thin film resistance layer 3 Thin film conductor layer 4 Photoresist film 5 Au plating layer 6 Through hole 7 Thin film conductor layer 8 Photoresist film
Claims (2)
裏面に薄膜抵抗層を形成する工程と、前記薄膜抵抗層上
に第１の金属層と第２の金属層からなる薄膜導体層を順
次形成する工程と、前記貫通孔の内部及び前記薄膜導体
層上のパターン形成部を除いた領域にメッキ用のフォト
レジスト膜を形成した後パターン形成部にＡｕメッキ層
を形成する工程と、前記フォトレジスト膜を除去した後
前記Ａｕメッキ層をマスクとして前記薄膜導体層及び前
記薄膜抵抗層をパターニングする工程とを含むことを特
徴とする膜回路基板の製造方法。1. A step of forming a thin film resistance layer on a front surface and a back surface of an insulating substrate provided with a through hole, and a thin film conductor layer comprising a first metal layer and a second metal layer on the thin film resistance layer. And a step of forming a photoresist film for plating on the inside of the through hole and a region on the thin film conductor layer excluding the pattern forming portion, and then forming an Au plating layer on the pattern forming portion, And a step of patterning the thin film conductor layer and the thin film resistance layer using the Au plating layer as a mask after removing the photoresist film.
はＣｕである請求項１記載の膜回路基板の製造方法。2. The method for manufacturing a membrane circuit board according to claim 1, wherein the first metal layer is Ti and the second metal layer is Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7972392A JPH05308182A (en) | 1992-04-01 | 1992-04-01 | Manufacture of film circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7972392A JPH05308182A (en) | 1992-04-01 | 1992-04-01 | Manufacture of film circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05308182A true JPH05308182A (en) | 1993-11-19 |
Family
ID=13698126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7972392A Withdrawn JPH05308182A (en) | 1992-04-01 | 1992-04-01 | Manufacture of film circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05308182A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140139435A (en) | 2013-05-27 | 2014-12-05 | 미쓰보 시베루토 가부시키 가이샤 | Hole-filling substrate having surface conductive film and production method thereof, and method for preventing swelling and peeling |
| KR20180043320A (en) | 2015-09-24 | 2018-04-27 | 미쓰보 시베루토 가부시키 가이샤 | VIA FILLED SUBSTRATE, PREPARATION METHOD THEREFOR, |
-
1992
- 1992-04-01 JP JP7972392A patent/JPH05308182A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140139435A (en) | 2013-05-27 | 2014-12-05 | 미쓰보 시베루토 가부시키 가이샤 | Hole-filling substrate having surface conductive film and production method thereof, and method for preventing swelling and peeling |
| KR20180043320A (en) | 2015-09-24 | 2018-04-27 | 미쓰보 시베루토 가부시키 가이샤 | VIA FILLED SUBSTRATE, PREPARATION METHOD THEREFOR, |
| US10517178B2 (en) | 2015-09-24 | 2019-12-24 | Mitsuboshi Belting Ltd. | Via fill substrate, production method therefor, and precursor therefor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990608 |