JPH07111518B2 - Method of forming thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In the present invention, two conductive layers having different etchants are laminated on the surface of a transparent insulating substrate, and a resist film formed according to a predetermined pattern thereon is used as a mask. The upper conductive layer and the lower conductive layer are selectively etched in this order to form a pattern of the gate electrode and a gate bus line connected to the gate electrode, and then the upper conductive layer is exposed from the exposed side surface.
Side etching is performed to the extent that the conductive layer of the narrow gate electrode portion is removed to form a wide gate bus line stepwise.

[Industrial application field]

The present invention relates to a method of forming a thin film transistor matrix used for driving a liquid crystal or the like.

[Conventional technology]

A thin film transistor (hereinafter abbreviated as TFT) matrix of a liquid crystal display device obtains a display by driving each TFT through two kinds of intersecting bus lines.
When a short circuit occurs between each type of bus line and each TFT, a display defect not only occurs in the pixel in the area where the short circuit occurs but also in the entire line including the pixel. Therefore, the short circuit defect between the bus line and the TFT becomes a serious obstacle in the TFT matrix panel.

The structure of the conventional gate electrode and gate bus line is
It is shown in the plan view of FIGS. (A) and (b) and the sectional view taken along the line BB.

In the figure, 1 is a glass substrate, 2 is a gate bus line, and 3 is a gate electrode.

Conventionally, a metal such as Ti as an electrode material is formed into a film having a thickness of about 80 nm on the surface of the glass substrate 1, and the photolithography patterning method
Gate bus line 2 and gate electrode 3 by etching method
Had formed.

After that, the gate insulating film is formed by the plasma chemical vapor deposition (hereinafter referred to as P-CVD) method. However, a satisfactory coverage cannot be obtained at the shoulders of the gate bus line 2 and the gate electrode 3. Therefore, a problem such as a short circuit defect with the conductive layer formed in the upper layer or a reduction in withstand voltage occurs at this portion.

Therefore, if the film thickness of the gate electrode 3 is made thin in order to improve the coverage, the thin film of the gate bus line 2 formed at the same time also becomes thin, so that the resistance of the bus line becomes high, which hinders driving. The problem occurs.

In order to solve this difficulty, there is also a method of forming the gate bus line 2 and the gate electrode 3 in separate steps, but in this case, the number of photomasks and the steps are increased, so that the yield is reduced and the cost is increased. There is a problem.

[Problems to be solved by the invention]

As described above, in the conventional manufacturing method, there is a problem in the characteristics and reliability of the liquid crystal display device, and an attempt to solve this difficulty requires an additional photomask, which leads to a reduction in yield and an increase in man-hours, resulting in high cost. There was a problem that became.

The present invention eliminates the need for an extra photomask,
An object of the present invention is to provide a method for forming a thin film transistor matrix capable of preventing the occurrence of short circuit defects and reduction in breakdown voltage.

[Means for solving problems]

According to the present invention, two conductive layers having different etchants are laminated on the surface of a transparent insulating substrate, and a resist film formed according to a predetermined pattern is used as a mask to remove exposed portions of the upper conductive layer and the lower conductive layer. (First and second stage etching) to form a pattern of the gate electrode and the gate bus line, and then, using the same resist film as a mask, only the upper conductive layer is treated with an etchant capable of etching to form a gate electrode portion. Side etching (third stage etching) is performed to such an extent that the upper conductive layer is removed.

[Work]

During the first and second stages of etching, since the exposed surface of the conductive layer is only the surface, the etching proceeds from the film surface in the direction of the thin film, and the upper and lower conductive layers are patterned according to the resist film. At the time of the third stage etching, the two conductive layers are already patterned, so that the side surfaces are exposed. Therefore, when only the upper conductive layer is treated with an etchant capable of being etched, the etching proceeds from the side surface of the upper conductive layer toward the inner depth and side etching is performed. Therefore, by controlling this processing time to such an extent that the upper conductive layer of the gate electrode portion having a narrow width is removed, the gate bus line has the upper conductive layer whose end portions are removed but the central portion remains and the stairs are stepped. Formed into a shape.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 (a) to (e) and FIGS. 2 (a) and (b).

1 (a) to 1 (d) are cross-sectional views of an essential part showing the above-described one embodiment in the order of manufacturing steps, and FIGS. 2 (a) and 2 (b) are plan views and A showing the structure of the obtained thin film transistor. FIG. 6 is a sectional view taken along line A-A.

First, as shown in FIG. 3A, a glass substrate 1 having a thickness of about 40 is formed as a lower conductive layer on the surface of the glass substrate 1 by using, for example, an evaporation method.
A titanium (Ti) layer 10 having a thickness of nm and an aluminum (Al) layer 11 as an upper conductive layer are formed thereon.

Then, as shown in FIG. 3B, on the Al layer 11,
The resist film 12 is selectively formed according to a predetermined pattern. The two patterns shown show the gate electrode portion G and the gate bus line portion B.

Then, as shown in FIG.
Using the as a mask, the Al layer 11 and subsequently the exposed portion of the Ti layer 10 are selectively removed. This etching may be performed using a usual etching method.

That is, the Al layer 11 has about 3000 ml of phosphoric acid (H ₃ PO ₄ ) and nitric acid (H ₂ N 4
O ₃ ) about 200 ml, acetic acid (CH ₃ COOH) about 600 ml, water (H ₂ O) about 200 m
It is removed by heating the mixed solution of 1 to about 50 ° C. and treating it for about 10 seconds.

Further, the Ti layer 10 uses carbon tetrachloride (CCl ₄ ) as a reaction gas,
Under the pressure of about 10 Pascal, about 500 W of high frequency power of 27.56 MHz is applied, and anisotropic etching is about 3
It is removed by applying for a minute. As described above, the exposed portions of the Al layer 11 and the Ti layer 10 are selectively removed, and only the Al layer 11 'and the Ti layer 10' immediately below the resist film 12 remain.

Then, again using the photoresist film 12 as a mask,
The remaining Al layer 11 'is side-etched by treating the mixed solution for about 20 seconds. The etching time is selected so that the Al layer 11 'of the gate electrode portion G having a narrow width can be completely removed. By controlling the etching time in this manner, both sides of the Al layer 11 'in the gate bus line B portion are 1 / the width of the gate electrode G portion as shown in FIG.
Only about 2 are removed, and the central part remains without being removed.

Then, as shown in FIG. 7E, the resist film 12 is removed to stack a Ti layer 10 'having a thickness of about 40 nm and an Al layer 11' having a width narrower than this and having a thickness of about 40 nm in a stepwise manner. A gate bus line B is formed and a gate electrode G composed of a Ti layer 10 'having a film thickness of about 40 μm is formed.

Lower Ti layer 10 'of the above gate bus line B, upper Al layer
11 'and the Ti layer 10' of the gate electrode G are respectively the lower gate bus line 5 and the upper gate bus line in FIG.
6, and the gate electrode 3 is formed.

After that, the TFT matrix is completed by proceeding according to a normal manufacturing process.

In this embodiment, two conductive layers having different etchants are laminated on the surface of a transparent insulating substrate, and a resist film formed according to a predetermined pattern thereon is used as a mask to form an upper conductive layer, a lower conductive layer, and an upper conductive layer. Etching is performed in order of layers with an etchant capable of etching only one of them. During the first and second stages of etching, since the exposed surface of the conductive layer is only the surface, the etching progresses in the film thickness direction from the film surface, so that the upper and lower conductive layers are patterned according to the resist film. . Third
The side surfaces of the two conductive layers are exposed because they have already been patterned during the step etching. Therefore, when processing with an etchant that etches only the upper conductive layer,
Etching proceeds from the side surface of the upper conductive layer toward the inner depth, and side etching is performed. Therefore, by controlling this processing time to such an extent that the upper conductive layer of the narrow gate electrode portion is removed, the gate bus line portion slightly removes only the end portion of the upper conductive layer and leaves the central portion. Let
It is formed in a desired step shape.

As described above, in this embodiment, the number of steps is small, the work is simple, and the pattern positional accuracy is extremely good.

〔The invention's effect〕

As described above, according to the present invention, the thickness of the gate electrode can be reduced and the gate bus line can be formed in a step shape by only partially changing the manufacturing process. It is possible to obtain a TFT matrix panel which can be made satisfactory and which has improved coverage at both shoulders, has less short-circuit defects with other bus lines formed thereon, and has a high breakdown voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an essential part showing a forming method of an embodiment of the present invention in the order of manufacturing steps, and FIGS. 2 (a) and 2 (b) are views showing an essential part structure of a TFT matrix obtained in the above-mentioned embodiment. 3 (a) and 3 (b) are explanatory views of the structure of the essential part for explaining the problems of the conventional TFT matrix. In the figure, 1 is a glass substrate, 2 and 3 are gate bus lines, 3 and G are gate electrodes, 10 and 10 'are lower conductive layers, and 11 and 1
Reference numeral 1'denotes an upper conductive layer, and reference numerals 12 and 12 'denote resist films.

Claims (1)

[Claims] 1. A display active matrix panel in which transistor elements corresponding to pixels are arranged in a matrix and a gate electrode (G) of each element is led out through a gate bus line (B) connected to the gate electrode. In doing so, a lower conductive layer (10) and an upper conductive layer (11) having a different etchant from that of the lower conductive layer are formed on the surface (1) of the transparent insulating substrate, and then a predetermined layer is formed thereon. A step of forming a resist film (12) according to the pattern, and using the resist film (12) as a mask, the upper conductive layer (1
1) and the exposed portion of the lower conductive layer (10) are selectively removed to form a pattern of a gate electrode (G) and a gate bus line (B) connected to the gate electrode, and then the upper conductive layer is formed. A step of removing at least the upper conductive layer remaining in the gate electrode portion by an etchant that is etchable and does not react with the lower conductive layer, and performs side etching on the upper conductive layer. A method of forming a thin film transistor matrix, comprising forming a gate bus line (B) in which a gate electrode (G) made of, a lower conductive layer and an upper conductive layer having a width narrower than this are stacked in a stepwise manner.