JPH0778995A - Thin film transistor matrix and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a thin film transistor matrix, and a fabrication method thereof, in which the source electrode and the drain electrode do not lap over the gate electrode and the parasitic capacitance is decreased between a pixel electrode, the gate electrode and the gate bus line. CONSTITUTION:An electrode offset film 12 is formed of amorphous Si on a glass substrate 1 while bulging from a gate electrode 3 formed thereon. A gate insulation film 4, an operational semiconductor layer 5, and a channel protective film 6 are then formed thereon. A source electrode 8 and a drain electrode 10 are formed while partially lapping over the channel protective film 6 with the edges thereof being defined by the electrode offset film 12. Consequently, a pixel electrode extends while being connected electrically with the source electrode 8 and the gate electrodes are connected through a gate bus line 2 whereas the drain electrodes are connected through a drain bus line 9 intersecting the gate bus line.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a thin film transistor for driving a liquid crystal display panel.
istor: TFT). Suitable method for manufacturing a matrix.

A liquid crystal display panel driven by a TFT matrix has a display quality of CRT (cathode ra).
It has been recognized that it has been improved to a degree comparable to that of y tube), but in recent years, there has been a demand for realization of larger size and clearer display.

By the way, in a liquid crystal display panel driven by a TFT matrix, there is a problem that a clear display is hindered by the TFT matrix itself, and this must be solved.

[0004]

2. Description of the Related Art FIGS. 15 to 20 are explanatory views of a main portion of a TFT matrix in process steps for explaining a conventional technique, which will be described below with reference to these drawings.
In any figure, the left side is the plane of the main part,
Further, the right side shows the cut surfaces along the line XX seen in the main part plane, but there are some parts omitted for the sake of simplicity of the drawing. For example, in the main part plane, Does not show the laminated coatings which are easier to understand when the cut surface along the line XX is seen.

15- (1) A Cr film is formed on a glass substrate 1 and then patterned to form a gate bus line 2 and a gate electrode 3 connected thereto.

15- (2) A gate insulating film 4 made of SiN, an operating semiconductor layer 5 made of amorphous Si, and a channel protection film 6 made of SiN are continuously laminated on the entire surface.

16- (1) Form a resist film 13 having the same width as the gate electrode 3 in the direction of line XX.

17- (1) Using the resist film 13 as a mask, the channel protection film 6 is etched to remove a portion which covers the gate electrode 3 and others. 17- (2) The resist film 13 is removed.

18- (1) After forming the electrode contact layer 7 made of n ⁺ -amorphous Si, a Cr film is formed.

19- (1) The Cr film, the electrode contact layer 7 and the operating layer 5 are patterned to form the source electrode 8, the drain bus line 9 and the drain electrode 10.

19- (2) The electrode contact layer 7 and the operating layer 5 are patterned. In this case, the electrode contact layer 7 has the same shape as the source electrode 8 and the drain electrode 10, and the operating layer 5
Needless to say, the edge of the pattern has a pattern in which the channel protective film 6, the source electrode 8, the drain bus line 9, the drain electrode 10 and the like are connected.

See FIG. 20. 20- (1) For example, a transparent conductive film made of ITO (indium tin oxide) is formed and then patterned to form a pixel electrode 11 for completion.

[0013]

According to the prior art, for example, as is apparent from FIG. 20, the source electrode 8 and the drain electrode 10 have a shape in which a part of the source electrode 8 and the drain electrode 10 hang on the channel protective film 6. ing.

The reason for doing this is that the current exposure apparatus,
That is, the stepper causes a deviation of 1 [μm] or less.

In a lithography process for forming the source electrode 8 and the drain electrode 10, if the resist film is displaced, reactive ion etching (reacti) is performed.
The veion etching (RIE) method is applied, and C
r film and underlying n ⁺ - when etched electrode contact layer 7 made of amorphous Si, of course is the source electrode 8 and the drain electrode 10 of the required shape can not be obtained, the underlying n ⁺ - amorphous Si Even the electrode contact layer 7 made of and the operating semiconductor layer 5 made of amorphous Si are etched, and the TFT matrix becomes a defective product.

By the way, as described above, when the source electrode 8 and the drain electrode 10 are partially overlapped on the channel protective film 6, the pixel electrode 11, the gate electrode 3 and the gate bus line 2 are formed. Parasitic capacitance in between C _gs
Will become bigger.

The parasitic capacitance C _gs causes a cross talk in the display, which causes a problem that a good image cannot be obtained.

As a measure for solving such a problem, a storage capacitor is provided in parallel with the pixel electrode 11, but since the storage capacitor has a large area, the aperture ratio of the pixel itself is correspondingly increased. It will be a sacrifice.

The present invention adopts a simple means so that the source electrode and the drain electrode do not overlap with the gate electrode, and the parasitic capacitance C _gs generated between the pixel electrode and the gate electrode and the gate bus line. To reduce the occurrence of cross talk on the display.

[0020]

FIG. 1 is a sectional side view showing a main part of a TFT matrix for explaining the principle of the present invention. The same symbols as those used in FIGS. 15 to 20 are the same parts. Or have the same meaning.

The TFT matrix shown in FIG. 1 differs from the TFT matrix shown in FIG. 20, for example, in that an electrode offset film made of, for example, amorphous Si is formed under the gate electrode 3 (and the gate bus line 2). 12 is provided.

The width of the electrode offset coating 12 in the line XX direction is the gate electrode 3 (and the gate bus line 2).
It is wider than the above, and its protruding portion 12A
Is about 1 [μm], for example.

As described above, since the patterning for forming the channel protection film 6 is performed in the state where the electrode offset coating 12 having a width wider than the gate length of the gate electrode 3 is provided, the resist is applied from the back surface of the glass substrate 1. When the film is exposed to ultraviolet light, the electrode offset coating 12 acts as a light-shielding film in response to the exposure. Therefore, the pattern of the resist film, that is, the channel protective film 6 has the same size as the electrode offset coating 12. Becomes the gate electrode 3
It will be larger than

With such a structure, even if a part of the source electrode 8 and the drain electrode 10 are formed so as to overlap the channel protective film 6, they are in an offset state with respect to the gate electrode 3, so that the parasitic capacitance C _gs does not increase.

From the above, in the thin film transistor matrix and the method for manufacturing the same according to the present invention, (1) the thin film transistor matrix is formed on the transparent insulating substrate (for example, the glass substrate 1) and protrudes from the outer periphery of the gate electrode. The electrode offset coating made of a semiconductor having a size (for example, the electrode offset coating 12 made of amorphous Si), the gate electrode (for example, the gate electrode 3) and the gate electrode laminated on the electrode offset coating are provided. A gate insulating film (for example, the gate insulating film 4) that covers, an operating semiconductor layer (for example, the operating semiconductor layer 5) that is formed on the gate insulating film and faces the gate electrode, and the gate electrode that is formed on the operating semiconductor layer. And a part of the channel protective film (for example, the channel protective film 6) facing each other on the channel protective film. A source electrode (for example, the source electrode 8) and a drain electrode (for example, the drain electrode 1) which are hooked and whose edges are defined by the outline of the electrode offset coating.
0) and a pixel electrode (for example, a pixel electrode 11) formed of a transparent conductive film that is partially conductively connected to the source electrode and extends.
And a gate bus line (for example, a gate bus line 2) connecting between the gate electrodes, and extending so as to intersect the gate bus line through an insulating film to connect between the drain electrodes. Or a drain bus line (for example, drain bus line 9) for

(2) On the transparent insulating substrate (for example, the glass substrate 1), the electrode offset film made of a semiconductor (for example, the electrode offset film 12 made of amorphous Si)
And a gate electrode material film (for example, Cr film) is formed and then patterned to form a gate electrode (for example, gate electrode 3) and a gate bus line (for example, gate A step of forming an electrode offset coating (amorphous Si electrode offset coating 12 described above) having a size protruding from the outer shape of the bus line 2) and its gate electrode and the like, and then a gate insulating film (for example, a gate insulating film). 4) and a step of sequentially forming an operating semiconductor layer (for example, operating semiconductor layer 5) and a channel protective film (for example, channel protective film 6), and then forming a resist film (for example, resist film 13) on the channel protective film. Then, the back surface of the transparent insulating substrate is exposed to form the same pattern as the electrode offset coating. And a step of etching the channel protective film using the resist film as a mask and then peeling off the resist film. Then, an electrode contact layer (for example, electrode contact layer 7) and an electrode material film (for example, Cr). Films are sequentially formed and then patterned to form a source electrode (for example, the source electrode 8) and a drain electrode (for example, the drain electrode 10) partially covered with the channel protection film, and between the drain electrodes in a continuous manner between the drain electrodes. A step of forming a drain bus line (for example, a drain bus line 9) to be connected, and then a pixel electrode (a ITO film) formed of a transparent conductive film (for example, an ITO film) that is partially conductively connected to the source electrode and extends. For example, a step of forming a pixel electrode 11) is included, or

(3) A gate electrode and a gate that connects the gate electrodes in series with the gate electrodes after forming a film for electrode offset made of a semiconductor and a gate electrode material film on a transparent insulating substrate and then performing patterning A step of forming a film for electrode offset having a size protruding from the outer portion of the bus line and its gate electrode, and a step of sequentially forming a gate insulating film, an operating semiconductor layer, and a channel protective film, and then An island-shaped resist film is formed on the channel protection film, and the channel protection film and the operating semiconductor layer are etched using the island-shaped resist film as a mask to form islands of the same pattern, and then the island-shaped resist film. And then forming a resist film on the channel protection film, and then removing the back surface of the transparent insulating substrate. A step of performing exposure to form the same pattern as the electrode offset coating, a step of etching the channel protective film using the resist film as a mask, and then peeling the resist film; A step of forming a transparent conductive film after introducing an impurity into the operating semiconductor layer exposed outside, and then forming an image reversal resist film (eg, image reversal resist film 20) on the surface. A step of performing exposure for forming a pattern of the pixel electrode, the source electrode, and the drain electrode from the front surface side,
Next, a step of performing reversal baking of the image reversal resist film, and then exposing from the back surface of the transparent insulating substrate to form a pattern defined by the outline of the gate electrode, and then the image
The transparent conductive film and the operating semiconductor layer are etched by using the reversal resist film as a mask, and a part of the source electrode is hung on the channel protective film, and a pixel electrode and a drain electrode extending in series with the source electrode. And a step of forming an underlayer of the drain bus line continuous with the drain electrode, and a step of forming a drain bus line below the drain bus line. Or

(4) In the above (1), the gate electrode is made of a material that forms a barrier and is not electrically connected to the electrode offset film made of the underlying semiconductor, or

(5) In the above (1), the film for electrode offset made of a semiconductor, which is the base of the gate electrode, is amorphous Si, or

(6) In the above (2) or (3),
The gate electrode is characterized in that it is made of a material that forms a barrier and is not electrically connected to the electrode offset film made of the underlying semiconductor, or

(7) In the above (2) or (3),
It is characterized in that the electrode offset coating made of a semiconductor, which is the base of the gate electrode, is amorphous Si.

[0032]

By adopting the above means, since the gate electrode does not overlap the source electrode and the drain electrode, the parasitic capacitance C _gs is reduced and the cross talk is eliminated, so that a clear display can be performed, and It is not necessary to interpose the storage capacitor in parallel with the pixel electrode, or even if the storage capacitor is intervened, a small capacitance is sufficient, so that the aperture ratio of the pixel is not sacrificed.

Further, the structure that can obtain such an excellent effect can be achieved by providing an electrode offset film on the base of the gate electrode, and it is sufficient to apply the semiconductor process technology which has been widely used conventionally. So, no special technology is needed.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 to 9 are main part explanatory views showing a TFT matrix in process steps for explaining the first embodiment of the present invention. Hereinafter, these drawings will be referred to. While explaining. In any of the drawings, the main surface plane is shown on the left side, and the cut surface along the line XX seen in the main surface plane is shown on the right side, but the main surface plane is omitted. There are also drawings, and the other points of consideration are exactly the same as the points of concern regarding FIGS. 15 to 20.

See FIG. 2 2- (1) Plasma Chemical Vapor Deposition
l vaporposition: P-CVD)
By applying the method, an amorphous Si film having a thickness of, for example, 10 [nm] is formed on the glass substrate 1.

2- (2) Subsequently, by applying the sputtering method,
A Cr film having a thickness of 100 nm, for example, is formed.

See FIG. 3 3- (1) Resist process in lithography technology, and
By applying a wet etching method using an etchant containing cerium nitrate second ammonium as a main component as an etchant, the Cr film is etched to form the gate bus line 2 and the gate electrode 3 connected thereto.

In this etching, over-etching is carried out so that the gate electrode 3 (and the gate bus line 2) is, for example, a pattern of about 1 [μm] inside the resist film pattern. For this etching, a mixed gas of chlorine and oxygen is used as the etching gas R
The IE method may be applied.

3- (2) Anisotropic etching of an amorphous Si film by applying the RIE method using chlorine gas as an etching gas while leaving the resist film used for forming the gate electrode 3 Then, the electrode offset coating 12 is formed. In this etching, since over-etching is not performed, the electrode offset coating 12 has the same pattern as the resist film pattern. Therefore, the electrode offset coating 12 is projected from the gate electrode 3 by about 1 [μm].

See FIG. 4. 4- (1) By applying the P-CVD method, the thickness is set to, for example, 4
The gate insulating film 4 made of SiN having a thickness of 00 [nm], the operating semiconductor layer 5 made of amorphous Si having a thickness of, for example, 15 [nm], and the channel protective film 6 made of SiN having a thickness of, for example, 120 [nm]. Are continuously formed.

See FIG. 5 5- (1) A resist film 13 is formed on the entire surface by applying a resist process in the lithography technique.

5- (2) The resist film 1 is irradiated with ultraviolet light from the back surface of the glass substrate 1.
3 exposure is performed. UV light is a coating for electrode offset 1
2 is transmitted, but is considerably attenuated, so that the resist film 13
The exposure pattern of is not the pattern of the gate electrode 3 but
The pattern is the same as the pattern of the electrode offset coating 12.

See FIG. 6 6- (1) By applying a wet etching method using buffered hydrofluoric acid as an etchant, the channel protective film 6 is etched using the resist film 13 as a mask. 6- (2) The resist film 13 is removed by immersing it in a resist stripping solution.

See FIG. 7 7- (1) By applying the P-CVD method, phosphine (PH
₃ ) and monosilane (SiH ₄ ) mixed gas as source
As the gas, the electrode contact layer 7 made of n ⁺ -amorphous Si and having a thickness of, for example, 50 nm is formed.

7- (2) Subsequently, by applying the sputtering method,
A Cr film having a thickness of, for example, 200 [nm] is formed.

See FIG. 8 8- (1) Resist process in lithography technology, and
By applying the wet etching method using cerium nitrate second ammonium as an etchant, the Cr film is etched to form the source electrode 8, the drain bus line 9 and the drain electrode 10. Note that this etching may be performed by applying the RIE method using a mixed gas of chlorine gas and oxygen gas as an etching gas.

8- (2) Subsequently, RI using chlorine gas as etching gas
By applying the E method, the electrode contact layer 7 made of n ⁺ -amorphous Si and the operating semiconductor layer 5 made of amorphous Si are etched using the resist film and the channel protective film 6 as a mask. 8- (3) The resist film is removed by immersion in a resist stripping solution.

See FIG. 9 9- (1) By applying the sputtering method, a transparent conductive film made of, for example, ITO and having a thickness of, for example, 80 [nm] is formed.

9- (2) Resist process in lithography technology, and
By applying a wet etching method using an etchant containing hydrochloric acid (HCl aqueous solution) as a main component as an etchant, the transparent conductive film is patterned to form the pixel electrodes 11 to complete the TFT matrix. .

FIG. 10 to FIG. 14 are explanatory views of the essential parts showing the TFT matrix in the process steps for explaining the second embodiment of the present invention. Hereinafter, referring to these figures, FIG. explain. In any of the drawings, the main plane is seen on the left side and the line XX on the right side is seen in the main plane.
Each of the cut surfaces along the line is shown, but there are some drawings in which the plane of the main part is omitted, and the other points to be noted are exactly the same as the points to be noted regarding FIGS. 15 to 20.

Also in the second embodiment, S is entirely formed from the beginning.
Steps for forming the channel protective film 6 made of iN,
That is, since it is exactly the same as the step 4- (1) described with reference to FIG. 4 from the beginning of the step in the first embodiment, description will be given from the next step.

10- (1) By applying the resist process in the lithography technique and the RIE method using a chlorine-based gas as an etching gas, the channel protective film 6 made of SiN is formed.
Then, the operating semiconductor layer 5 made of amorphous Si is etched.

The patterns of the channel protective film 6 and the operating semiconductor layer 5 thus obtained are larger than those of the electrode offset coating 12, for example.

10- (2) Immerse in a resist stripping solution to remove the resist film used for patterning the channel protective film 6 and the operating semiconductor layer 5.

10- (3) Again, a resist process in the lithography technique is applied to form a resist film on the entire surface. The resist film formed here is the resist film 1 in the first embodiment.
Equivalent to 3.

10- (4) The back surface of the glass substrate 1 is irradiated with ultraviolet light to expose the resist film. Also in this case, as in the first embodiment, the exposure pattern of the resist film 13 is not the pattern of the gate electrode 3 but the same as the pattern of the electrode offset coating 12.

10- (5) The channel protective film 6 is etched using the resist film as a mask by applying a wet etching method using buffered hydrofluoric acid as an etchant. 10- (6) The resist film is removed by immersion in a resist stripping solution.

See FIG. 11 11- (1) By applying the ion shower method, the dose amount is set to 5 × 10 ¹⁵ [cm ⁻² ] for the exposed operating semiconductor layer 5 made of amorphous Si. Introduce P to convert into n ⁺ .

As the impurity introduction technique for selectively changing the operating semiconductor layer 5 made of amorphous Si into n ⁺ , a plasma doping method using a P-CVD apparatus is applied in addition to the ion shower method. You can also 11- (2) By applying the sputtering method, a transparent conductive film made of, for example, ITO having a thickness of, for example, 80 [nm] is formed.

See FIG. 12 12- (1) An image reversal resist film 20 is formed on the entire surface by applying a resist process in the lithography technique. The image reversal resist is initially a negative type, but is known as a positive type resist when reversal baking is performed.

12- (2) In the first exposure, the pattern of the source electrode, the pixel electrode, the drain electrode, and the drain bus line is exposed.

12- (3) The second exposure is performed from the back surface of the glass substrate 1, and ultraviolet light is irradiated until the edge of the gate electrode 3 and the edge of the resist film 20 coincide with each other. That is, since this exposure is performed to such an extent that the effect of the electrode offset coating 12 can be ignored, it is necessary to increase the exposure amount. 12- (4) After development, the resist film 20 has the illustrated pattern.

See FIG. 13. 13- (1) The transparent conductive film is patterned by applying a wet etching method using an etchant containing hydrochloric acid (HCl aqueous solution) as a main component as an etchant. Electrode 8, pixel electrode 11 and drain electrode 1
The base 9A of 0 and the drain bus line is formed.

13- (2) By applying the RIE method using a chlorine-based gas as an etching gas, the operating semiconductor layer 5 made of amorphous Si and protruding from the channel protective film 6 is etched. 13- (3) The resist film 20 is removed by immersing it in a resist stripping solution.

See FIG. 14 14- (1) A Cr film having a thickness of, for example, 200 [nm] is formed by applying a sputtering method.

14- (2) Resist process in lithography technology, and
By applying a wet etching method in which the etchant is an etching solution composed of an aqueous solution containing cerium nitrate second ammonium as a main component, the Cr film is etched to form the base of the drain bus line composed of a transparent conductive film. The drain bus line 14 is formed on 9A to complete the TFT matrix.

In any of the above embodiments, there is no overlap between the gate electrode, the source electrode and the drain electrode,
Therefore, there is no parasitic capacitance. Since there is a barrier between the gate electrode and the underlying electrode offset coating made of amorphous Si, and there is no electrical connection, the gate insulation is provided above the electrode offset coating. The parasitic capacitance generated between the source electrode and the drain electrode formed through the film is small enough to be ignored.

Further, the source and drain electrodes and the gate electrode are in an offset state, but since a photocurrent is generated in the amorphous Si due to the influence of the backlight at the time of driving, TFT characteristics are necessary for driving. Can be obtained.

The present invention is not limited to the above-mentioned embodiment, and many other modifications can be realized. For example,
Although Cr is used as the material of the gate electrode in each of the above-described embodiments, any material may be used as long as it is not electrically connected because a barrier is generated between the gate electrode and the semiconductor.

[0070]

In the thin film transistor matrix and the manufacturing method thereof according to the present invention, an electrode offset film having a size protruding from the outer periphery of the gate electrode is formed on the transparent insulating substrate, and the electrode offset film is formed. A gate electrode is formed on the gate insulating film, the gate electrode is covered with a gate insulating film, an operating semiconductor layer and a channel protective film are formed on the gate insulating film, the channel protective film is partially covered, and the edge is a film for electrode offset. A source electrode and a drain electrode defined by the outer periphery of the gate electrode, a pixel electrode partially conductively connected to the source electrode is formed, and a gate bus line connecting the gate electrodes and the gate bus line.
And a drain bus line that extends so as to intersect the line through an insulating film and connects between the drain electrodes.

Since the gate electrode does not overlap the source electrode and the drain electrode by adopting the above structure, the parasitic capacitance C _gs is reduced and cross talk is eliminated.
A clear display can be performed, and it is not necessary to interpose a storage capacitor in parallel with the pixel electrode, or even when interposing, a small capacity is required, so that the aperture ratio of the pixel is sacrificed. There is no such thing.

Further, the structure capable of obtaining such an excellent effect can be achieved by providing an electrode offset film on the base of the gate electrode, and it is sufficient to apply the semiconductor process technology which has been widely used conventionally. So, no special technology is needed.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a main part of a TFT matrix for explaining the principle of the present invention.

FIG. 2 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment in the present invention.

FIG. 3 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment in the present invention.

FIG. 4 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment in the present invention.

FIG. 5 is a principal part explanatory view showing a TFT matrix in a process main part for explaining the first embodiment in the present invention.

FIG. 6 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment of the present invention.

FIG. 7 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment of the present invention.

FIG. 8 is an explanatory diagram of a main part showing a TFT matrix in a process main part for explaining a first embodiment of the present invention.

FIG. 9 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a first embodiment of the present invention.

FIG. 10 is a principal part explanatory view showing a TFT matrix in a process main part for explaining a second embodiment in the present invention.

FIG. 11 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a second embodiment of the present invention.

FIG. 12 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a second embodiment of the present invention.

FIG. 13 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a second embodiment of the present invention.

FIG. 14 is an explanatory view of a main part showing a TFT matrix in a process main part for explaining a second embodiment of the present invention.

FIG. 15 is a principal part explanatory view showing a TFT matrix in a process main part for explaining a conventional technique.

FIG. 16 is an explanatory diagram of a main part showing a TFT matrix in a process main part for explaining a conventional technique.

FIG. 17 is a principal part explanatory view showing a TFT matrix in a process main part for explaining a conventional technique.

FIG. 18 is a principal part explanatory view showing a TFT matrix in a process main part for explaining a conventional technique.

FIG. 19 is a principal part explanatory view showing a TFT matrix in a process main part for explaining a conventional technique.

FIG. 20 is a main part explanatory view showing a TFT matrix in a process main part for explaining a conventional technique.

[Explanation of symbols]

 1 glass substrate 2 gate bus line 3 gate electrode 4 gate insulating film 5 operating semiconductor layer 6 channel protective film 7 electrode contact layer 8 source electrode 9 drain bus line 9A drain bus line base 10 drain electrode 11 pixel Electrode 12 Coating for electrode offset 13 Resist film 20 Image reversal resist film

Claims (7)

[Claims] 1. An electrode offset coating formed of a semiconductor, which is formed on a transparent insulating substrate and has a size protruding from the outline of a gate electrode, and a gate electrode and the gate laminated on the electrode offset coating. A gate insulating film covering an electrode, an operating semiconductor layer formed on the gate insulating film and facing the gate electrode, and a channel protective film formed on the operating semiconductor layer and facing the gate electrode; A pixel formed of a source electrode and a drain electrode which are partially covered by the protective film and whose edges are defined by the outer contour of the electrode offset film, and a transparent conductive film which partially extends in conductive connection with the source electrode. An electrode, a gate bus line connecting between the gate electrodes, and a gate bus line crossing the gate bus line through an insulating film. A drain that extends to connect between the drain electrodes
A thin film transistor matrix comprising: bus lines. 2. A gate electrode and a gate for connecting between gate electrodes in succession to the gate electrode after forming a film for electrode offset made of a semiconductor and a gate electrode material film on a transparent insulating substrate and then performing patterning. A step of forming a film for electrode offset having a size protruding from the outside of the bus line and its gate electrode, etc., and a step of sequentially forming a gate insulating film, an operating semiconductor layer, and a channel protective film, and then, A step of forming a resist film on the channel protective film and then exposing from the back surface of the transparent insulating substrate to form the same pattern as the electrode offset film, and then using the resist film as a mask A step of removing the resist film after etching, and then an electrode contact layer and an electrode A step of forming material films in order and then patterning to form a source electrode and a drain electrode which are partially covered by the channel protection film, and a drain bus line which connects the drain electrodes and is connected to the drain electrodes. Then, a step of forming a pixel electrode made of a transparent conductive film, which is partially conductively connected to the source electrode and extends, is included. 3. A gate electrode for connecting an electrode offset film made of a semiconductor and a gate electrode material film formed on a transparent insulating substrate and then patterning the gate electrode and connecting the gate electrodes in series with the gate electrode. A step of forming a film for electrode offset having a size protruding from the outside of the bus line and its gate electrode, etc., and a step of sequentially forming a gate insulating film, an operating semiconductor layer, and a channel protective film, and then, An island-shaped resist film is formed on the channel protection film, and the channel protection film and the operating semiconductor layer are etched using the island-shaped resist film as a mask to form islands of the same pattern, and then the island-shaped resist film is formed. And then removing a resist film from the transparent insulating substrate after forming a resist film on the channel protective film. To form the same pattern as the electrode offset coating, and then to etch the channel protective film using the resist film as a mask and then peel off the resist film; A step of forming a transparent conductive film after introducing impurities into the operating semiconductor layer exposed to the outside, and then forming an image reversal resist film on the surface to form the pixel electrode, the source electrode and the drain from the surface side. Exposing to form a pattern of electrodes, and then performing reversal baking of the image reversal resist film, and then exposing from the back surface of the transparent insulating substrate to define the outline of the gate electrode. And then masking the image reversal resist film. As a result, the transparent conductive film and the operating semiconductor layer are etched to form a source electrode partially covered by the channel protection film, and a pixel electrode and a drain electrode extending continuously from the source electrode and a drain electrode and a drain electrode thereof. Manufacture of a thin film transistor matrix, which comprises the steps of forming an underlayer of a drain bus line, and then forming a drain bus line below the drain bus line. Method. 4. The thin film transistor matrix according to claim 1, wherein the gate electrode is made of a material which forms a barrier with the electrode offset film made of an underlying semiconductor and is not electrically connected. 5. The thin film transistor matrix according to claim 1, wherein the electrode offset coating made of a semiconductor, which is the base of the gate electrode, is amorphous Si. 6. The method of manufacturing a thin film transistor matrix according to claim 2, wherein the gate electrode is made of a material that forms a barrier with the electrode offset film made of an underlying semiconductor and is not electrically connected. Method. 7. The method of manufacturing a thin film transistor matrix according to claim 2, wherein the electrode offset coating made of a semiconductor which is the base of the gate electrode is amorphous Si.