JPH0195536A - Manufacture of multiple film wiring body - Google Patents
Manufacture of multiple film wiring bodyInfo
- Publication number
- JPH0195536A JPH0195536A JP25342287A JP25342287A JPH0195536A JP H0195536 A JPH0195536 A JP H0195536A JP 25342287 A JP25342287 A JP 25342287A JP 25342287 A JP25342287 A JP 25342287A JP H0195536 A JPH0195536 A JP H0195536A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- etched
- wiring body
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000007788 liquid Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 description 7
- 238000001771 vacuum deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はＴＦ’Ｔ−ＬＣＤ１密着形イメージセンサ等
に用いふ積層構造膜の多重膜配線体の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer interconnection body of laminated structure films used in TF'T-LCD 1 contact type image sensors and the like.
第３図は従来の多重膜配線体の製造方法の各段階での状
態を示す断面図であシ、図において、（１）は基板、（
２）はこの基板（１）上に形成された第１の金属膜、（
３）はこの第１の金属膜（２）上に形成された第２の金
属膜、（４）は第２の金属膜（３）上に所望のパターン
に形成されたレジストである。FIG. 3 is a cross-sectional view showing the state at each stage of a conventional method for manufacturing a multilayer wiring body. In the figure, (1) is a substrate, (
2) is the first metal film formed on this substrate (1), (
3) is a second metal film formed on this first metal film (2), and (4) is a resist formed in a desired pattern on the second metal film (3).
次に製造方法について説明する。基板（１）上に第１の
金属膜（２）、第２の金属膜（３）を形成後、第２の金
属膜（３）上にレジスト（４）を所望のパターンに形成
した後に、第３図（ａ）に示すように、第２の金属膜（
３）を第１の金属膜（２）と選択性のあるエツチング液
でエツチングする。更に、第３図（１））に示すように
、第１の金属膜（２）を第２の金属膜（３）と選択性の
あるエツチング液でエツチングする。この時、第１の金
属膜（２）は第２の金属膜（３）をマスクとしてエツチ
ングされる。この後、第３図（Ｑ）に示すように、レジ
ストパターン（４）を除去し、多重膜配線体を得る。Next, the manufacturing method will be explained. After forming a first metal film (2) and a second metal film (3) on a substrate (1), and forming a resist (4) in a desired pattern on the second metal film (3), As shown in FIG. 3(a), the second metal film (
3) is etched with an etching solution selective to the first metal film (2). Furthermore, as shown in FIG. 3(1)), the first metal film (2) is etched with an etching solution selective to the second metal film (3). At this time, the first metal film (2) is etched using the second metal film (3) as a mask. Thereafter, as shown in FIG. 3(Q), the resist pattern (4) is removed to obtain a multilayer wiring body.
多重膜を連続エツチングするため、高コストのレジスト
パターン形成が１回で良く、従って、低コストに多重膜
配線体を製造出来る。Since multiple films are etched continuously, a high-cost resist pattern can be formed only once, and therefore, a multi-film wiring body can be manufactured at low cost.
従来の多重膜配線体は以上のように第２の金属膜をマス
クとして第１の金属膜をエツチングす、るので、第１の
金属膜がアンダーカットにより第２の金属膜パターンの
内側に入シ込み、断面形状が７字形になる。従って、こ
の多重膜配線体上に更に、膜形成を行うと、パターン端
部での膜のカバレージ不良等が発生し、積層構造の信頼
性が低くなる等の問題点があった。In the conventional multi-layer wiring structure, as described above, the first metal film is etched using the second metal film as a mask, so that the first metal film enters inside the second metal film pattern due to undercuts. It sinks in, and the cross-sectional shape becomes figure 7. Therefore, if a film is further formed on this multi-layer interconnection body, there are problems such as poor coverage of the film at the ends of the pattern, and the reliability of the laminated structure is lowered.
この発明は上記のような問題点を解消するためになされ
たもので、多重膜断面形状を逆Ｔ字形にパターン形成で
きると共に、従来と同等のコストでパターン形成できふ
多重膜配線体の製造方法を得すことを目的とすふ。This invention was made in order to solve the above-mentioned problems, and provides a method for manufacturing a multilayer interconnection body, which can form a multilayer film in an inverted T-shaped cross-sectional shape and at the same cost as the conventional method. The purpose is to obtain.
この発明に係る多重膜配線体の製造方法は、多重膜を連
続エツチング後、上層膜を選択的にエツチングするエツ
チング液で上層膜をサイドエツチングし、しかる後レジ
ストを除去するようにしたものである。The method for manufacturing a multi-layer wiring body according to the present invention is such that after continuous etching of the multi-layer film, the upper layer film is side-etched using an etching solution that selectively etches the upper layer film, and then the resist is removed. .
この発明における多重膜配線体の製造方法は、多層膜を
連続エツチングして、一応Ｔ字形断面形状にした後、更
に上層膜を選択的にエツチングし、下層膜パターンの内
側にまで上層膜のサイドエツチングを進行させることに
より、多重膜の断面形状を逆Ｔ字形とする。The method for manufacturing a multi-layer wiring body according to the present invention involves continuously etching the multi-layer film to give it a T-shaped cross section, and then selectively etching the upper layer film to the inside of the lower film pattern. As the etching progresses, the multilayer film has an inverted T-shaped cross section.
（発明の実施例〕 □
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による多重膜配線体の製造方法
の各段階における状態を示す断面図である。（１）は基
板で例えばシリコン基板（以下１’−８１基板」という
） 、１２）は第１の金属膜で８１基板（１）上に例え
ば真空蒸着法によ膜形成された厚さ１■人〜３０００
Ａのクロム膜（以下「Ｏｒ膜」という）、（３）は第２
の金属膜で、Ｏｒ膜（２）上に例えば真空蒸着法によ膜
形成された厚さ１００人〜３μｍのアルミニウム膜（以
下ｒＡｌ膜」という） 、（４）はレジストパターンで
、Ａｌ膜（３）上に例えば写真製版技術を用いて所望の
パターンに形成されたフオトレジス）ＰＲ−８（東京応
化社製）である。(Embodiment of the invention) □ An embodiment of the invention will be described below with reference to the drawings.
The figures are cross-sectional views showing states at each stage of a method for manufacturing a multilayer interconnection body according to an embodiment of the present invention. (1) is a substrate, for example, a silicon substrate (hereinafter referred to as 1'-81 substrate), and 12) is a first metal film, which is formed on the 81 substrate (1) by, for example, a vacuum evaporation method and has a thickness of 1 cm. ~3000 people
A chromium film (hereinafter referred to as "Or film"), (3) is the second
(4) is a resist pattern, which is an aluminum film (hereinafter referred to as "rAl film") with a thickness of 100 to 3 μm formed on the Or film (2) by, for example, a vacuum evaporation method. 3) A photoresist PR-8 (manufactured by Tokyo Ohka Co., Ltd.) formed in a desired pattern using, for example, photolithography.
この実施例による多重構造配線体の製造方法を説明する
。８１基板（１）上にＯｒ膜＋２３ 、 ＡＡ’膜（３
）を順次形成ｋ 、ｐ”ｌ膜（３）上に所望のパターン
にレジストＰＲ−８（４）を形成する。まず、第１図（
ａ）に示すように、Ａｌ膜（３）をＯｒ膜（２）と選択
性のあるエツチング液でエツチングし、しかる後第１図
（ｂ）に示すようにＯｒ膜（２）をＡｌ膜（３）と選択
性のめ石エツチング液でエツチングする。A method of manufacturing a multi-structure wiring body according to this embodiment will be explained. 81 On the substrate (1), Or film +23, AA' film (3
) are sequentially formed. A resist PR-8 (4) is formed in a desired pattern on the p''l film (3). First, the resist PR-8 (4) shown in FIG.
As shown in a), the Al film (3) is etched with an etching solution that is selective to the Or film (2), and then the Or film (2) is etched with the Al film (2) as shown in FIG. 3) and etching with a selective stone etching solution.
この時、Ｏｒ膜（２）はＡｌ膜（３）をマスクとしてエ
ツチングされるので、アンダーカットによｊ）、Ｏｒ膜
（２）のパターンはＡｌ膜（３）のパターンの内側に入
如込む。この後、第１図（０）に示すように、更にＡｌ
膜（３）をＯｒ膜（２）と選択性のあるエツチング液で
エツチングする。この時Ａｌ膜（３）はサイドエツチン
グが進行する。′第２図Ｋｉ膜すイドエツチング進行量
とエツチング時間との関係の一例を液温をパラメータと
して示す。この例ではエツチング液としてＨ３Ｐ０４
／ＨＮＯ３／ ＣＨ３０００Ｈ／Ｈ２０の混合液を用い
た。例えば、第２図のデータをもとに％ｋｌ膜（３）の
サイドエツチング量を時間、液温により制御し、Ｏｒ膜
（２）のパターンの内側に入シ込むまでＡＩ！膜（３）
のサイドエツチングを進行させる。この後、第１図（ｄ
）に示すように、レジストＰＲ−８（４）を除去、シ、
多重膜配線体を得る０本製造方法によ膜形成された多重
膜配線体の断面形状は逆Ｔ字形をしているので、この多
重膜配線体上に災に膜形成を行ってもパターン端部での
カバレージ不良等は発生せず、積層構造での高い信頼性
が得られる。又、高コストのレジストパターン形成が従
来法と同様に１回で良いので、従来法と同等のコストで
多重膜配線体を製造出来為。At this time, since the Or film (2) is etched using the Al film (3) as a mask, the pattern of the Or film (2) enters inside the pattern of the Al film (3) due to the undercut. . After this, as shown in FIG. 1 (0), further Al
The film (3) is etched with an etching solution selective to the Or film (2). At this time, side etching progresses in the Al film (3). Figure 2 shows an example of the relationship between the progress of Ki film etching and the etching time using the liquid temperature as a parameter. In this example, H3P04 is used as the etching solution.
/HNO3/CH3000H/H20 mixture was used. For example, based on the data in FIG. 2, the amount of side etching of the %kl film (3) is controlled by time and liquid temperature, and the AI! Membrane (3)
Proceed with side etching. After this, Figure 1 (d
), remove resist PR-8 (4),
Since the cross-sectional shape of the multi-film wiring body formed by the zero-layer manufacturing method is in an inverted T-shape, even if a film is accidentally formed on the multi-film wiring body, the pattern edge will not be removed. There are no coverage defects in the parts, and high reliability can be obtained in the laminated structure. In addition, since the high-cost resist pattern formation only needs to be done once as in the conventional method, multi-layer wiring bodies can be manufactured at the same cost as in the conventional method.
なお、上記実施例では基板（１）に８１基板を用いたが
、ガラス基板等地の基板でも良く、第１の金属膜（２）
にＯｒ膜を用いたが、ニッケル膜等他の膜でも良く、第
２の金属膜（３）にＡＩ膜を用いたが、銅膜等信の膜で
も良い。又、第１の金属膜（２）、第２の金属膜（３）
の膜形成方法に真空蒸着法を用いたが、スパッタ法等他
の形成方法でも良い。更に、レジスト（４）にフオトレ
ジス） ＰＲ−８（東京応化社製）を用いたが、ＥＢレ
ジスト等他のレジストでも良い。In the above embodiment, an 81 substrate was used as the substrate (1), but a substrate made of a material such as a glass substrate may also be used, and the first metal film (2)
Although an Or film is used for the second metal film (3), other films such as a nickel film may be used.Although an AI film is used for the second metal film (3), a copper film or other metal film may be used. Moreover, the first metal film (2), the second metal film (3)
Although a vacuum evaporation method was used as the film forming method in the above, other forming methods such as a sputtering method may be used. Further, although photoresist PR-8 (manufactured by Tokyo Ohka Co., Ltd.) was used as the resist (4), other resists such as EB resist may be used.
又、レジスト（４）のパターン形成方法に写真製版技術
を用いたが、印刷法等他の技術を用いてパターン形成し
ても良い。Furthermore, although photolithography is used to form the pattern of the resist (4), other techniques such as printing may be used to form the pattern.
又、多重膜［２重膜を用いたが、３重以五の多重膜でも
良い。Further, a multilayer film (a double layer is used, but a multilayer film of three or more layers may also be used).
以上の工うに、この発明によれば多重膜を連続エツチン
グ後、上層膜のサイドエツチングを行うようにしたので
、多重膜配線体断面形状を逆Ｔ字形に形成でき、従って
積層構造での高い信頼性が得られ、また、高コストのレ
ジストパターン形成も従来法と同じ１回で良いので、従
来法と同等の低コストで多重膜配線体を得られる効果が
ある。As described above, according to the present invention, after the multilayer film is continuously etched, the upper layer film is side-etched, so that the cross-sectional shape of the multilayer wiring body can be formed into an inverted T-shape, and therefore, a highly reliable multilayer structure can be achieved. Furthermore, since the high-cost resist pattern formation only needs to be done once as in the conventional method, there is an effect that a multi-layer wiring body can be obtained at the same low cost as in the conventional method.
第１図はこの発明の一実施例による多重膜配線体の製造
方法の各段階での状態を示す断面図、第２図はこの実施
例方法に用いるアルミニウム膜のサイドエツチング量と
エツチング時間との関係を示すグラフ、第３図は従来の
多重膜配線体の製造方法の各段階での状態を示す断面図
でちる。
図において、（１）は基板、（２）は第１の金属膜、（
３）は第２の金属膜、（４）はレジストパターンである
。
なお、図中同一符号は同一または相当部分を示す０FIG. 1 is a cross-sectional view showing the state at each stage of a method for manufacturing a multilayer interconnection body according to an embodiment of the present invention, and FIG. 2 shows the side etching amount and etching time of an aluminum film used in this embodiment method. A graph showing the relationship, FIG. 3, is a cross-sectional view showing the state at each stage of the conventional method for manufacturing a multilayer wiring body. In the figure, (1) is the substrate, (2) is the first metal film, (
3) is the second metal film, and (4) is the resist pattern. In addition, the same symbols in the figures indicate the same or corresponding parts.
Claims (1)
れ上記第１の金属膜とは異種の金属からなる第２の金属
膜とを有し、上記第２の金属膜を最上層とする多重金属
膜を基板上に形成し、 上記第２の金属膜の上に所望の形状にレジストパターン
を形成し、 このレジストパターンをマスクとして上記第２の金属膜
のみを選択的にエッチングする第１のエッチング液で上
記第２の金属膜をエッチングし、上記レジストパターン
と上記エッチング後の第２の金属膜とをマスクとして上
記第１の金属膜のみを選択的にエッチングする第２のエ
ッチング液で上記第１の金属膜をエッチングし、その後
に、上記第２の金属膜を上記第１のエッチング液で再び
サイドエッチングして当該第２の金属膜の幅を上記第１
の金属膜の幅より小さくし、最後に、上記レジストパタ
ーンを除去する工程を備えた多重膜配線体の製造方法。(1) having a first metal film and a second metal film formed on the first metal film and made of a metal different from the first metal film; A multilayered metal film having a top layer of etching the second metal film with a first etching solution, and selectively etching only the first metal film using the resist pattern and the etched second metal film as a mask; 2, and then the second metal film is side-etched again with the first etching solution to reduce the width of the second metal film to the first etching solution.
A method for manufacturing a multi-layer wiring body, comprising the steps of: making the width of the metal film smaller than the width of the metal film; and finally, removing the resist pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25342287A JPH0195536A (en) | 1987-10-07 | 1987-10-07 | Manufacture of multiple film wiring body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25342287A JPH0195536A (en) | 1987-10-07 | 1987-10-07 | Manufacture of multiple film wiring body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0195536A true JPH0195536A (en) | 1989-04-13 |
Family
ID=17251172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25342287A Pending JPH0195536A (en) | 1987-10-07 | 1987-10-07 | Manufacture of multiple film wiring body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0195536A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7125356B2 (en) | 2001-11-06 | 2006-10-24 | Borgwarner Inc. | Tension-reducing random sprocket |
| US8430775B2 (en) | 2007-09-28 | 2013-04-30 | Borgwarner Inc. | Multiple tension reducing sprockets in a chain and sprocket system |
| JP2015185783A (en) * | 2014-03-26 | 2015-10-22 | 三菱電機株式会社 | Semiconductor device and manufacturing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55138260A (en) * | 1979-04-13 | 1980-10-28 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5863150A (en) * | 1981-10-12 | 1983-04-14 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS58197849A (en) * | 1982-05-14 | 1983-11-17 | Oki Electric Ind Co Ltd | Formation of electrode wiring |
-
1987
- 1987-10-07 JP JP25342287A patent/JPH0195536A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55138260A (en) * | 1979-04-13 | 1980-10-28 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5863150A (en) * | 1981-10-12 | 1983-04-14 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS58197849A (en) * | 1982-05-14 | 1983-11-17 | Oki Electric Ind Co Ltd | Formation of electrode wiring |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7125356B2 (en) | 2001-11-06 | 2006-10-24 | Borgwarner Inc. | Tension-reducing random sprocket |
| US8430775B2 (en) | 2007-09-28 | 2013-04-30 | Borgwarner Inc. | Multiple tension reducing sprockets in a chain and sprocket system |
| JP2015185783A (en) * | 2014-03-26 | 2015-10-22 | 三菱電機株式会社 | Semiconductor device and manufacturing method therefor |
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