JPS62290148A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain excellent ohmic properties while preventing a disconnection at the stepped section of a second layer wiring and the contamination of a wafer by forming an opening section in the same pattern as a first layer wiring to a second insulating film while a contact hole continuing to the opening section is molded to a tapered shape. CONSTITUTION:An opening section 27 for burying a first layer wiring in the same pattern as the first layer wiring is shaped to an insulating film 25 through etching by using an anisotropic dry etching device, employing a photo-resist pattern 26 as a mask. An insulating film 23 is left and only the insulating film 25 is removed in etching at that time. According to such etching, the insulating film 23 on the opening edge section of a contact hole 24 is etched, and the contact hole 24 is molded to a tapered shape. The photo-resist pattern 26 is removed, and a metallic layer 28 as a first layer wiring material is evaporated onto the whole surface in the opening section 27 and on the insulating film 25 containing the contact hole 24. The upper section of the metallic layer is coated with a photo-resist 29 to flatten the surface.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) This invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

(Prior Art '4) In a semiconductor device having a multilayer wiring structure, the multilayer wiring structure is conventionally manufactured as shown in FIG. The following is a step-by-step explanation.

First, an N diffusion layer 2 is formed on a semiconductor substrate 1, an insulating film 3 is formed on the surface, and a photoresist pattern 4 is further formed thereon (FIG. 2(a)).

Next, using the photoresist pattern 4 as a mask, the insulating film 3 is
A contact hole 5 is formed in the insulating film 3 on the N diffusion layer 2 by etching, and then the photoresist pattern 4 is removed (FIG. 2(b)).

Subsequently, a metal layer 6 (here, 11 layers) for forming a first layer wiring is deposited on the entire surface of the insulating film 3, including the contact hole 5 (FIG. 2(c)).

Next, a photoresist pattern 7 is formed on the metal layer 6 (12[](d)), and the metal 6 is etched using the photoresist pattern 7 as a mask to form the first layer wiring 6a made of the remaining metal layer 6. form (Fig. 2(e)
)). Here, the first layer wiring 6a is connected to the contact hole 5.
It is formed so as to be connected to the N diffusion layer 2 through. After that, the resist pattern 7 is removed.

Next, after sintering is performed to make contact between the first layer wiring 6a and the N diffusion layer 2, a spin cord insulating film 8 is applied to the entire surface including the first layer wiring 6a to prevent upper layer wiring from being disconnected.
(for example, 0.C, L manufactured by Tokyo Ohka)), and then an interlayer insulating film 9 is formed thereon (FIG. 2(f)).

Subsequently, as shown in the figure, a photoresist pattern 10 is formed on the interlayer insulating film 9, and then the photoresist pattern 10 is
By etching the interlayer insulating film 9 and the spin foot insulating film 8 using as a mask, a through hole 11 shown in FIG. 2(g) communicating with the first layer wiring 6a is formed in this laminated film.

Thereafter, after removing the photoresist pattern 10, a metal layer (At layer) for forming a second-layer wiring is deposited and patterned, so that the second-layer wiring 6a is connected to the first-layer wiring 6a through the entire through-hole 11. Layer wiring 12 is formed on interlayer insulating film 9 (FIG. 2 □□□)). This completes the multilayer wiring.

(Problems to be Solved by the Invention) However, the above conventional methods have the following problems and are not technically satisfactory.

(2) If the contact hole 5 is minute, the ohmic relationship between the first layer wiring 6a and the N diffusion layer 2 cannot be maintained.

■Aim for the 1st layer! The second layer wiring 12 on the stepped portion 6a is dented (section A in FIG. 2(g)), and unless it is made thicker, the second layer wiring 12 will break. If the thickness is increased, it becomes difficult to realize a three-layer structure, a four-layer structure, etc.

(2) A spin cord insulating film 8 is required, and contamination (flakes) of the wafer caused by this reduces yield.

■To prevent hillocks from occurring from the side of the first layer wiring 6a,
In the case of a fine pattern (section B in figure (e)), a short circuit occurs with the adjacent wiring.

This invention was made in view of the above points, and its purpose is to be able to obtain good ohmic properties even when the contact hole is small, and to prevent breakage of the second layer wiring, contamination of the wafer, and side hillocks. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a high yield and multilayer interconnection forming step that can prevent the above problems.

(Means for solving the problem) In the present invention, an insulating film (first insulating film) on a semiconductor substrate
After forming a contact hole in 1, a rim film for hole 2 is formed on the entire surface of the first insulating film including the contact hole 1.
7-After forming a photoresist pattern on the connection barrier of No. 7 Hani 2, anisotropic dry etching is performed using the photoresist pattern as a mask to form the same pattern as the first layer wiring on the second insulating film. An opening is formed, and at the same time, the contact hole continuous with the opening is formed into a tapered shape. Furthermore, after this anisotropic etching, by forming the first layer wiring material on the entire surface and etching back, the first layer wiring material is left only in the opening and the contact hole.
Form layer wiring.

(Function) In this method, the contact hole is formed into a tapered shape by anisotropic dry etching when forming the opening in the second insulating film. The ohmic properties between the eye wiring and the diffusion 11 formed in the semiconductor substrate are improved. Further, since the first layer wiring is formed embedded in the second insulating film, locking with the sides is eliminated. Furthermore, the surface becomes flat due to the embedding, so that even if the spin cord insulating film is omitted and the total wiring film thickness is reduced to Δ, no cracks or breaks will occur in the second layer wiring.

(Embodiment) An embodiment of the present invention will be described below with reference to FIG. 1'f.

First, after forming N-diffused Nl 22 on the semiconductor substrate 21 to be connected to the first layer wiring, an insulating film 23 for insulating the first layer wiring is formed on the surface of the substrate 21, and further on this insulating film 23. Contact hole 2 leading to the N diffusion layer 22
4 using well-known photolithography and etching technology (first
Figure (a)).

Next, an insulating film 25 (specifically, a PSG film) for embedding the first layer wiring is formed on the entire surface of the insulating film 23 including the contact hole 24 (FIG. 1(b)).

At this time, the insulating film 25 is made to be twice as thick as the insulating film 230, but since the thickness of the insulating film 25 determines the thickness of the first layer wiring, the thickness of the first layer wiring is determined from the wiring current density, etc. after that! @It is necessary to determine the thickness of the membrane 23.25. Furthermore, when the contact hole 24 is formed into a tapered shape in a later process, the angle of the inner wall of the contact hole 24 is determined by the relationship between the film thicknesses of the insulating film 23 and the insulating film 25, and the inner wall angle 45a (45° is To obtain the ideal angle),
It is desirable that the thickness of the insulating film 25 be twice the thickness of the insulating film 23.

Next, a photoresist pattern 261i4 for forming an opening for embedding the first-layer wiring is formed on the insulating film 25 (see FIG. 1).
c)).

Then, by etching using the photoresist pattern 26 as a mask using an anisotropic dry etching device f (RIE device), openings 27 for embedding the first layer wiring in the same pattern as the first layer wiring are formed in the insulating film 25. (xlN(d)). At this time, the etching is such as to remove only the insulating film 25 while leaving the insulating film 23 intact. Such etching removes the N diffusion layer 22 in the contact hole 24 portion that is continuous with the opening portion 27.
It is not a difficult process as it is possible to detect the end point of the etching where it is exposed. However, when such etching is performed, anisotropic dry etching (RIE)
), the insulating film 23 at the opening edge of the contact hole 24 is etched, and as a result, the contact hole 24 is formed into a tapered shape. This has been confirmed through experiments. At this time, in this example, the insulating film 23
．． 25, the inner wall of the contact hole 24 has an ideal angle of 45°.

After that, after removing the photoresist pattern 26,
The insulating film 2 includes the opening 27 and the contact hole 24.
A metal layer 28 (here, an At layer) as a first layer wiring material is deposited on the entire surface of the metal layer 5 (FIG. 1(e)). Furthermore, a photoresist 29 is coated thereon to make the surface flat (FIG. 1(f)).

Thereafter, the photoresist 29 and the metal layer 28 are etched back by anisotropic dry etching (RIE) such that the etching rate is the same for the photoresist and At until the insulating film 25 is exposed, and the metal layer 28 is etched back into the opening. 27 and contact hole 24 (FIG. 1(g)). As a result, a first layer wiring 28a made of the remaining metal layer 28 is connected to the N diffusion layer 22 through the insulating film 25.

Thereafter, an interlayer insulating film 30 (specifically, a PSG film) is formed on the flat surface of the first layer wiring 28aa insulating film 25, and a photoresist pattern 31 for forming through holes is further formed on it (19th layer insulating film 30). (h)).

Then, by etching the interlayer insulation +1iW 30 as a mask for the photoresist coating 31e, the interlayer insulation film 30 is connected to the first layer wiring 28a as shown in FIG.
A through hole 32 shown in 1) is formed. Thereafter, after removing the photoresist pattern 31, a metal layer (Mj) as a second layer wiring material is deposited and patterned. A second layer wiring 33 to be read directly is formed (FIG. 1( )).

This completes the multilayer wiring.

Note that although the above embodiment is a case of two-layer wiring, wiring can be stacked in many layers by following similar steps. In addition, it becomes possible to use the embedding technique used to form the first layer wiring to flatten the wiring shapes in the second and higher layers, and to stack the wiring and i' in many layers.

(Effect of the invention) As explained in detail above, according to the method of this invention,
When the opening for embedding is formed in the second insulating film for embedding by anisotropic dry etching, the contact hole is formed into a tapered shape, so even if the contact hole is small, it can be easily connected to the first layer wiring. Good ohmic properties can be achieved with the diffusion layer formed in the semiconductor substrate. Furthermore, since the first layer wiring is embedded in the second insulating film, there is no occurrence of side hillocks, and short circuits due to side hillocks can be prevented even in fine patterns. Furthermore, since the first layer wiring is embedded and formed in the second insulation film, the surface becomes flat, so there is no need for a spin cord insulation film when forming the second layer wiring, which prevents contamination of the wafer. It can be reduced. In addition, as a result of the flat surface,
The opening characteristics of through-holes for interlayer insulation films are improved,
Furthermore, even if the wiring film thickness is made thinner, it is possible to prevent cracks and breaks in the second layer wiring.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a multilayer wiring structure. 21... Semiconductor substrate, 23... Insulating film, 24...
Contact hole, 25... Extremely rounded top, 26... Photoresist pattern, 27... Opening portion, 28... Metal layer, 28a... First layer wiring, 29... Photoresist. Patent issuer Oki Electric Industry Co., Ltd. 24 Contag Hall A Figure 1 The book is 1R-quality and the typical sword process P side entrance Figure 2 Figure 2

Claims (1)

[Claims] A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising: (a) forming a first insulating film on a semiconductor substrate;
(b) forming a second insulating film over the entire surface of the first insulating film including the contact hole; (c) forming the second insulating film. By forming a photoresist pattern thereon and performing anisotropic dry etching using the photoresist pattern as a mask, openings with the same pattern as the first layer wiring are formed in the second insulating film, and at the same time, openings are formed in the second insulation film. (d) After that, the photoresist pattern is removed, and the second contact hole including the contact hole and the opening is formed into a tapered shape.
(e) Coating a photoresist on the first layer wiring material to make the surface flat, and then combining the photoresist and the first layer wiring material. 1. A method of manufacturing a semiconductor device, comprising the step of etching back to leave the first layer wiring material only in the opening and the contact hole.