JPH0330295B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for forming multilayer wiring using an interlayer insulating film having a two-layer laminated structure of two types of heat-resistant polymer resins having different molecular structures.

(b) Background of the technology For example, with the rapid progress in increasing the density and speed of integrated circuit semiconductor devices, the technology for forming electrodes in finely patterned multilayer wiring structures is becoming increasingly important in determining the degree of integration and performance. It is becoming a new technology.

(c) Prior Art and Problems When forming the multilayer wiring structure in the above-mentioned semiconductor device, in the conventional method, a first electrode wiring layer 2 made of aluminum or the like is formed on a semiconductor substrate 1 as shown in FIG. The semiconductor substrate 1 including the wiring layer 2 is further covered with a silicon dioxide layer 3 by, for example, a CVD method, and an electrode connection window 4 is formed by a normal photoetching technique. A second electrode wiring layer 5 made of Al or the like is formed through the electrode 4. However, in such a structure, in the case of multi-layer lamination, the Al deposited layer becomes thinner at the stepped portion 6, and there is a risk of disconnection of the second wiring. Therefore, as a method for flattening the upper surface of the semiconductor substrate 1 by eliminating the step portion 6 mentioned above, coating with a heat-resistant polymer resin, such as a fluid polyamide resin solution, is often used as shown in FIG. In Fig. 2, parts equivalent to those in the previous figure are given the same reference numerals, but polyamide is spin-coated over the entire surface of the semiconductor substrate on which the first electrode wiring layer 2 is provided, and a predetermined step-curing process is performed. Polyimide layer 7
Then, an electrode connection window 8 is formed on the polyimide layer 7 by a normal photoetching technique, and an electrode connection window 8 is formed through the electrode connection window 8.
An Al second electrode wiring layer 5 is formed. However, in the above conventional method, when forming the electrode connection window 8 on the polyimide layer 7 by etching, as shown in the enlarged cross-sectional view of the main part of FIG. If there is a positional shift in the etching window, the polyimide layer 7 in the region adjacent to the first electrode layer 2 is exposed, and an overetched portion 9 is formed in the polyimide layer 7 in the region, so that the polyimide layer 7 in the region adjacent to the first electrode layer 2 facing the region is exposed. A stepped portion 11 having a sharp corner 10 is formed at the edge of the electrode wiring layer 2 .
For this reason, when forming the second electrode wiring layer 5 in contact with the first wiring layer 2 in the connection window 8, the second electrode wiring layer 5 is
The electrode wiring layer 5 has a sharp corner 1 of the first electrode wiring layer 2.
Cracks 12 starting from 0 tend to occur, which poses a problem of lowering the reliability of the second electrode wiring layer 5. Therefore, conventionally, as a means to prevent the above-mentioned positional deviation, a wide wiring connection pad having one side, for example, about three times the normal wiring width, is formed in the wiring connection area of the first electrode wiring layer 2 to prevent the positional deviation from occurring. Although the above-mentioned problem was prevented from occurring, this method had the problem of lowering the degree of integration of the semiconductor device and hindering higher integration.

(d) Object of the Invention The object of the present invention is to provide a method for forming multilayer interconnections that solves these problems and allows for high integration.

(e) Structure of the Invention That is, the present invention involves coating and curing a first heat-resistant polymer resin on a substrate provided with a lower wiring layer to form a first insulating film, and then partially etching away the first insulating film. to expose the lower wiring layer, and etching the lower wiring layer and the remaining first insulating film at an etching rate under one etching condition compared to the lower wiring layer and the first insulating film. forming a large second insulating film by applying and curing a second heat-resistant polymer resin; and thereafter etching under the etching conditions to form a connection window in the second insulating film that is larger than the width of the lower wiring layer. The method is characterized in that it includes a step of providing an upper wiring layer on the lower wiring layer to form a connection part.

(f) Embodiments of the invention The embodiments of the invention will be described below in Figures 4 to 9.
A detailed explanation will be given using a cross-sectional view of a main process part of an embodiment shown in the figure. The same parts as in the previous figure are given the same reference numerals.

In FIG. 4, a metal film of approximately 1 μm thick, such as aluminum, is formed on a semiconductor substrate 21 by ordinary vapor deposition or sputtering, and a required lower wiring layer 22 is formed by ordinary photo-etching. . Next, as shown in FIG.
When an insulating film 23 made of a first heat-resistant polymer resin layer is applied to a thickness of about 1.2 μm by spin coating on the semiconductor substrate 21 including the semiconductor substrate 21, a flat surface layer is formed due to its fluidity. For example, Pyralin PI-2555 (manufactured by DuPont) is used as the first heat-resistant polymer resin solution, step curing is performed to prevent the inclusion of air bubbles, and the final treatment temperature is approximately 450°C.
The first heat-resistant polymer resin layer 23 is cured by heat treatment for about 30 minutes. The cured first heat-resistant polymer resin 23 has etching resistance against a hydrazine-based etching solution used in subsequent steps. Next, as shown in FIG. 6, the surface of the first heat-resistant polymer resin layer 23 is etched away by ordinary oxygen (O ₂ ) plasma treatment until the lower wiring layer 22 is completely exposed on the surface. Gas pressure as an etching condition
1Torr, output 300W, time about 2 minutes.
Next, as shown in FIG. 7, on the first heat-resistant polymer resin layer 23 including the lower wiring layer 22, a second heat-resistant polymer resin layer 24, for example, an electronic insulating coating material SP-
710 (manufactured by Toray Industries, Inc.) is applied to the entire surface, step cure is performed, and the final treatment temperature is 450℃ and heat treatment is performed for 30 minutes to harden. The cured second heat-resistant polymer resin layer 24 has etching properties with respect to a hydrazine-based etching solution. Then, as shown in FIG.
A desired lower wiring layer 2 is formed on the heat-resistant polymer resin layer 24.
A resist film 26 having an etching window 25 that exposes the surface of the wiring connection window forming area larger than 2 widths is formed using a normal photo process, and then using the resist film 26 as a mask, a resin made of hydrazine or the like is etched. A connection window 27 exposing the upper surface of the lower wiring layer 22 is formed in the second heat-resistant polymer resin layer 24 by ordinary wet etching using a liquid. Of course, the dimensions of the connection window 27 may be equal to or different from the width of the lower wiring layer 2 depending on the purpose of use. In this case, since the first heat-resistant polymer layer 23 is resistant to etching, no steps are caused due to misalignment of the connection window pattern. Next, the resist film 26 is removed using a resist stripper or the like. Then, using conventional methods such as vapor deposition or sputtering and selective etching,
As shown in FIG. 9, the lower wiring layer 22 is placed on the second heat-resistant polymer resin layer 24 at the connection window 27.
For example, an upper wiring layer 28 of aluminum is formed in contact with the upper wiring layer 28 .

As explained above, according to the present invention, the surface of the lower wiring layer 22 is flattened by the first heat-resistant polymer resin layer 23, and the resin layer 23 is etched when the connection window 27 is formed by etching. By taking advantage of this property, there is no difference in level, which eliminates the difficulty of alignment work, and makes it possible to form the electrode connection window 27 larger than the width of the lower wiring layer 22.

(g) Effects of the invention In this way, it is not necessary to provide a large-area wiring connection pattern particularly in the lower wiring layer, and it becomes possible to increase the integration of semiconductor elements, and also improves efficiency by simplifying alignment work. Significant effects such as improved reliability can be obtained by preventing wire breakage during flattening.

Note that the present invention is also applicable to multilayer wiring of three or more layers, and the embodiments are given as examples of the present invention and are not intended to limit the scope of the present invention.

[Brief explanation of the drawing]

1 and 2 are sectional views of the main parts according to the conventional method, FIG. 3 is an enlarged sectional view of the main parts according to the conventional method, and FIGS. 4 to 9 are sectional views of the main parts of the process of an embodiment according to the present invention. be. In the figure, 21 is a semiconductor substrate, 22 is a lower wiring layer, 23 is a first heat-resistant polymer resin layer, 24 is a second heat-resistant polymer resin layer, 26 is a resist film, 27 is a connection window, and 28 is an upper wiring layer. .

Claims (1)

[Claims] 1. Coating and curing a first heat-resistant polymer resin on a substrate provided with a lower wiring layer to form a first insulating film;
Next, a step of etching away a portion of the first insulating film to expose the lower wiring layer, and etching the lower wiring layer and the remaining first insulating film at an etching rate under one etching condition. forming a second insulating film larger than the first insulating film by applying and curing a second heat-resistant polymer resin, and then etching the second insulating film under the etching conditions described above.
A multilayer wiring formation characterized by comprising the steps of: forming a connection window larger than the width of the lower wiring layer in an insulating film; and forming a connection part by providing an upper wiring layer on the lower wiring layer. Method.