JP2002280451A - Method for forming multilayer wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate formation of a flat interlayer insulation film and a multilayer wiring structure. SOLUTION: Under a state where a lower wiring layer 105 is formed by selective plating and a sheet film 202, in which a resin film 201 formed of photosensitive and thermosetting polyimide is formed, is pasted onto an interlayer insulation film 102 including the lower wiring layer 105, the sheet film 202 is boned to a substrate 101 in a container under a specified degree of vacuum by applying a load and heat to the eventually stripped sheet film 202. The photosensitive resin film 201 is exposed entirely and rendered soluble to developer before being developed. Under a state where the upper surface of the lower wiring layer 105 is exposed, the photosensitive resin film 201 is heat treated and thermally set to form an insulation film 106. A resist pattern 108 having a hole 108a at a specified region is then formed on the insulation film 106 and the lower wiring layer 105, a contact part 109 is formed in the hole 108a by selective plating, and then an insulating film 106 is formed similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer wiring in which a plurality of wiring layers are stacked.

[0002]

2. Description of the Related Art Multilayer wiring technology is indispensable for realizing higher density electronic components. In an LSI, in order to realize a multilayer wiring structure, it is necessary to planarize the surface of an insulating film formed between wiring layers and a metal wiring layer. Representative techniques for realizing the planarization include a chemical mechanical polishing (CMP) method and an etch-back method. After forming the desired film,
The flattened portion is flattened. In particular,
The CMP method is a flattening technique widely used in forming a wiring by a damascene method.

In the damascene method, as shown in FIG.
After forming a groove in the interlayer insulating film 902 formed on the semiconductor substrate 901 and forming the seed layer 903, a wiring metal is grown on the seed layer 903 by plating and the wiring metal film 904 is filled so as to fill the groove. To form Thereafter, the wiring metal film 904 is cut and polished by the CMP method, and the wiring pattern 905 is formed in the groove of the interlayer insulating film 902 as shown in FIG.
Is formed.

On the other hand, in a multilayer wiring structure, wiring connections in different wiring layers are made at connection portions formed in holes formed in an insulating film between wiring layers. For example, in the above-described damascene method, a hole for connecting to a wiring in a lower wiring layer and a groove for forming a wiring are simultaneously formed by a method called a double damascene method,
There is also a technique in which a wiring metal is filled and flattened in the same manner as described above, and a connection portion and a wiring are simultaneously formed.

[0005]

However, the technology for realizing the above-mentioned multilayer wiring structure has the following problems. First, the CMP method has a strong pattern dependency, and may require stability and easiness, for example, a dummy pattern may be required. In addition, as the wiring width has become finer, the connection part has also become finer,
It becomes difficult to form fine holes in the interlayer insulating film so as to surely reach the underlying wiring, and there is a case where a problem such as a connection failure occurs because a hole completely penetrating is not formed.

The present invention has been made to solve the above problems, and has as its object to enable a multilayer wiring structure to be formed more easily.

[0007]

According to a method of forming a multilayer wiring of the present invention, an interlayer insulating film is formed on a semiconductor substrate, a first metal film is formed on the interlayer insulating film, and a predetermined metal film is formed on the first metal film. Forming a first mask pattern having a plurality of groove-shaped opening regions extending in the direction of... By plating the first metal film surface exposed at the bottom of the opening region of the first mask pattern by a plating method. After forming the first metal pattern and removing the first mask pattern, the first metal film is etched and removed using the first metal pattern as a mask to form a plurality of first metal patterns and the first metal pattern. Forming a lower wiring layer composed of an electrode wiring of the type described above, forming a first resin film having photosensitivity on the interlayer insulating film so as to absorb the unevenness of the lower wiring layer to be flat, and develop the resin film. To remove a predetermined amount of the first resin film, By forming the first insulating film, the upper surface of the lower wiring layer is exposed, and the upper surface of the first insulating film and the upper surface of the lower wiring layer are substantially in the same plane. Forming a second metal pattern on the film, forming a second mask pattern having holes in a predetermined area on the second metal film in an area above any one of the first metal patterns; The second exposed at the bottom of the hole of the mask pattern
After a columnar second metal pattern is formed on the surface of the metal film by a plating method and the second mask pattern is removed,
The second metal film is etched and removed using the metal pattern as a mask to form a connection portion composed of the second metal film and the second metal pattern, and the photosensitive second resin film is used to remove irregularities in the connection portion. A second insulating film is formed by removing a predetermined amount of the second resin film by developing the resin film to form a second insulating film by absorbing and forming the first insulating film on the first insulating film so as to be flat. As a result, the upper surface of the connection portion is exposed, and the upper surface of the second insulating film and the upper surface of the connection portion form substantially the same plane, and a part of the second insulating film is connected to the connection portion on the second insulating film. This is to form an upper wiring layer composed of a plurality of electrode wirings.
According to the present invention, the second insulating film that separates the lower wiring layer and the upper wiring layer is formed in a state where the connection portion is formed in advance.

In the above invention, the first and second resin films may be removed after the entire area is exposed and then developed. The removal of the first resin film is performed after the exposure is performed on the lower wiring layer, and the removal of the second resin film is performed after the exposure is performed on the connection portion. May be.

According to another aspect of the present invention, there is provided a method for forming a multilayer wiring, comprising forming an interlayer insulating film on a semiconductor substrate, forming a first metal film on the interlayer insulating film, and forming a first metal film on the first metal film in a predetermined direction. Forming a first mask pattern having a plurality of groove-shaped opening regions extending to the first metal pattern, and forming a plurality of first mask patterns on the surface of the first metal film exposed at the bottom of the opening region of the first mask pattern by plating. After a metal pattern is formed and the first mask pattern is removed, the first metal film is etched away using the first metal pattern as a mask, and a plurality of electrodes including the first metal film and the first metal pattern are formed. Forming a lower wiring layer made of wiring, forming a second mask pattern having a hole in a region above any one of the first metal patterns, and exposing the first metal exposed at the bottom of the hole of the second mask pattern Plating method on pattern After forming a connection portion made of a more columnar metal pattern and removing the second mask pattern, the resin film having photosensitivity and thermosetting absorbs the unevenness of the lower wiring layer and the connection portion to be in a flat state. It is formed on the interlayer insulating film so that the resin film is developed, a predetermined amount of the resin film is removed, and the resin film is cured by heat to form an insulating film, thereby exposing the upper surface of the connection portion and connecting to the upper surface of the insulating film. An upper wiring layer is formed on the insulating film, the upper wiring layer being composed of a plurality of electrode wirings, some of which are connected to the connection portions, in a state where substantially the same plane as the upper surface is formed. According to the present invention, the insulating film for separating the lower wiring layer and the upper wiring layer is formed in a state where the connection portion is formed in advance.

In the above invention, the removal of the resin film may be performed after the exposure on the lower wiring layer and the connection portion. In the invention described above, a transfer base material is prepared, a resin film is formed on the transfer base material, and a lower wiring layer forming surface of the semiconductor substrate and a resin film forming surface of the transfer base are brought into contact with each other. By heating to a temperature and pressing with a predetermined force to absorb irregularities due to the lower wiring layer, the semiconductor substrate and the transfer base material are cooled to a predetermined temperature or less, and then the transfer base material is separated from the semiconductor substrate. What is necessary is just to let the film be in the state formed on the semiconductor substrate.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment 1> FIGS. 1 to 3 are process diagrams for explaining a method of forming a multilayer wiring according to an embodiment of the present invention. Hereinafter, the forming method will be described with reference to FIGS. First, as shown in FIG. 1A, an interlayer insulating film 102 is formed on a substrate 101 made of a semiconductor material such as silicon.
To form On the substrate 101 under the interlayer insulating film 102,
Although not shown, an integrated circuit including elements such as transistors is formed.

After forming the interlayer insulating film 102, first, a titanium film having a thickness of 0.1 μm and a
A seed layer (first metal film) 103 made of a two-layer film of a μm copper film is formed. Next, as shown in the perspective view of FIG. 1B, a resist pattern 104 having a thickness of about 1 μm and having groove-shaped opening regions 104a and 104b extending in a predetermined direction is formed on the seed layer 103. The resist pattern 104 is formed by a known photolithography technique. After forming the resist pattern 104, FIG.
As shown in (c), metal patterns (first metal patterns) 105a and 105 made of a copper plating film are formed on the seed layer 103 exposed in the opening regions 104a and 104b.
b is formed to a thickness of about 0.5 μm by an electrolytic plating method.

Thereafter, by removing the resist pattern 104, only the metal patterns 105a and 105b are formed on the seed layer 103 as shown in FIG. The layer 103 is selectively etched. In this etching, first,
Using a nitric acid-based etchant, copper of 0.1 μm above the seed layer 103 is selectively removed. Next, an HF-based etchant is used to form a 0.1 μm
Of titanium is selectively removed.

As a result, as shown in FIG. 1E, a lower wiring layer 105 composed of a plurality of stripe-shaped wiring electrodes extending in a predetermined direction is formed on the interlayer insulating film 102. The lower wiring layer 105 is composed of the metal patterns 105a and 105b in FIG. After the lower wiring layer 105 is formed, a silicon nitride film (not shown) is formed on the surface of the lower wiring layer 105 by a CVD method in order to prevent oxidation of copper. Instead of silicon nitride, a film of ruthenium or nickel may be formed on the surface of the lower wiring layer 105 by an electroless plating method.

Next, as shown in FIG. 2A, a photosensitive resin film (first resin film) 201 made of a photosensitive resin and a thermosetting resin, for example, a photosensitive polyimide is formed. The surface of the sheet film (transfer substrate) 202 on which the photosensitive resin film 201 (thickness: 10 μm) is formed is bonded onto the interlayer insulating film 102 including the lower wiring layer 105. The sheet film 202 has a photosensitive resin film 20 in advance.
1 is formed by spin coating or the like. Photosensitive resin film 2
01 uses a positive photosensitive resin, and as a material, a resin obtained by adding a positive photosensitive agent to a base resin such as polyimide, polyamic acid, or polybenzoxazole is used. As a positive photosensitive resin having polybenzoxazole as a base resin, for example, “C” manufactured by Sumitomo Bakelite Co., Ltd.
RC8304 ”may be used.

With the sheet film 202 adhered, the substrate 101 is placed in a container evacuated to a predetermined degree of vacuum, a load is applied between the substrate 101 and the sheet film 202, and By applying a higher temperature, the photosensitive resin film 201 is heated so that the photosensitive resin film 201 adheres to the lower wiring layer 105 and the interlayer insulating film 102. The degree of vacuum was 10 Torr, the load was 10 kg, the heating temperature was 120 ° C., and the load and heating were applied for about 5 minutes.

Thereafter, the sheet film 202 is peeled off from the photosensitive resin film 201 adhered to the lower wiring layer 105 and the interlayer insulating film 102, and the lower wiring layer 105 is formed on the lower wiring layer 105 as shown in FIG. The photosensitive resin film 201 in a state where the photosensitive resin film 201 has been flattened by absorbing a step due to 105 has a thickness of 2 μm.
It is in a state formed (transferred) to the extent. The formation of the photosensitive resin film 201 by the bonding described above is performed by STP
(Spin coating film Transfer and Hot pressing). The STP method has a simpler process and has less load on the process, such as no generation of foreign substances, as compared with the planarization by the conventional etch-back method or CMP method. Make it easier.

Next, the entire photosensitive resin film 201 is exposed to light so as to be soluble in a developing solution, and is developed to remove a part of the photosensitive resin film 201 from the upper surface thereof. (Metal patterns 105a, 105b) The upper surface is exposed. In addition, when the photosensitive resin film is provided with negative-type photosensitivity, without exposure, only by a developing process of dipping in a developer, a part of the photosensitive resin film 201 is removed from the upper surface. Is also good. Further, the exposure may be performed only on the lower wiring layer 105.

In addition, the photosensitive resin film 201 is thermally cured by performing a heat treatment at 350 ° C., and an insulating film (first insulating film) 106 is formed as shown in FIG. 1
It is assumed that substantially the same plane is formed on the upper surface of the lower wiring layer 105 and the upper surface of the lower wiring layer 105. Although not shown,
Since a silicon nitride film is formed on the surface of the lower wiring layer 105, the exposed surface of the silicon nitride film is removed by wet treatment with HF or dry etching.

As described above, in the present embodiment, since the wet processing is performed using the developing solution, the damage caused by the plasma is given to the element formed on the substrate 101 as compared with the etching back using the plasma. There is no. In addition, since the photosensitive resin film is used and developed to reduce the film thickness, it is possible to shorten the time for this processing. In addition, since the photosensitive resin film is thermally cured after development, it can withstand a subsequent process such as having high heat resistance and sufficiently function as an insulating film.

Next, as shown in FIG. 2D, a titanium / copper seed layer (second metal film) 107 is formed on the insulating film 106 and the lower wiring layer 105. A resist pattern 108 having a hole 108a in the region and a thickness of about 1 μm is formed. This is the seed layer 1
03 and the resist pattern 104.

After the resist pattern 108 is formed, as shown in FIG. 3A, a columnar metal pattern (second metal pattern) made of a copper plating film is formed on the seed layer 107 exposed in the hole 108a. 109a is formed to a thickness of about 0.5 μm by an electrolytic plating method. Thereafter, the resist pattern 108 is removed, and the metal pattern 109a is removed.
As a mask, the seed layer 107 is selectively etched and removed, as shown in FIG. 3B, so that a connection portion 109 composed of the metal pattern 109a and the seed layer 107 left by the etching is formed on the lower wiring layer 105. The state is formed above. In addition, in order to prevent oxidation of copper, the connection portion 1
A silicon nitride film (not shown) is also formed on the surface of the substrate 09 by the CVD method. By forming the columnar connection portion 109 in advance in this way, it is possible to avoid poor connection between the upper wiring layer formed thereon and the lower wiring layer 105.

Next, similarly to the above-described photosensitive resin film 201 (FIG. 2), the lower wiring layer 10 including the connection portion 109 is formed.
The photosensitive resin film (second resin film) 301 in a state where it is flattened by absorbing a step due to the connecting portion 109 is formed (transferred) to a thickness of about 2 μm on the insulating film 106 and the insulating film 106. . After the photosensitive resin film 301 is formed in a flat state, the photosensitive resin film 301 is exposed to the entire area to make it soluble in a developing solution.
Is partially removed from the upper surface of the connecting portion 109 so that the upper surface of the connecting portion 109 (metal pattern 109a) is exposed. A part of the photosensitive resin film 301 may be removed from the upper surface of the photosensitive resin film 301 only by performing a developing process in which the photosensitive resin film 301 is immersed in a developing solution without performing exposure. Alternatively, the exposure may be performed only on the connection section 109.

In addition, a heat treatment at 350 ° C. is performed to thermally harden the photosensitive resin film 301, and an insulating film (second insulating film) 110 is formed as shown in FIG. 1
It is assumed that substantially the same plane is formed on the upper surface of the connecting portion 109 and the upper surface of the connecting portion 109. Also at this time, although not shown, since the silicon nitride film is formed on the surface of the connection portion 109, the exposed surface (the upper surface of the connection portion 109) by a wet process using HF or a dry etching process is used. 2) The silicon nitride film is removed. Conventionally, an interlayer film was first formed, a hole was formed in the interlayer film, and a conductive material was filled in the hole.Therefore, a state in which a through hole was not formed due to the formation of the hole was likely to occur, resulting in poor connection. Although the state was easy, these can be solved according to the present embodiment.

Next, as shown in FIGS. 1A to 1E, first, as shown in FIG. 4A, a seed layer 111 is formed on the upper surface of the connection portion 109 and the upper surface of the insulating film 110. 4B, a resist pattern 112 having an opening region 112a is formed on the seed layer 111, as shown in FIG.
To form Next, as shown in FIG. 4C, a metal pattern 113a is formed on the exposed seed layer 111 by a plating method, and the resist pattern 112 is removed.
The surface of the seed layer 111 around the metal pattern 113a is exposed.

Next, the seed layer 111 is removed by etching using the metal pattern 113a as a mask.
As shown in (a), the upper wiring layer 113 composed of the seed layer 111 and the metal pattern 113a remaining after the etching is formed on the insulating film 110. Thereafter, an insulating material is deposited on the insulating film 110 including the upper wiring layer 113 by a plasma CVD method, and FIG.
As shown in (b), a protective film 114 is formed.

As described above, according to the present embodiment, a multilayer wiring structure can be formed more easily than before. In the above embodiment, a two-layer wiring structure has been described as an example, but the present invention is not limited to this.
It goes without saying that more multilayer wiring structures can be obtained by repeating the steps up to FIG.
In the above description, copper is used as the wiring material.
The invention is not limited to this, and another conductive material may be used.

Second Embodiment Next, another embodiment of the present invention will be described. 6 to 8 are process diagrams illustrating a method of forming a multilayer wiring according to the present embodiment.
The same reference numerals as those shown in FIGS. 1 to 5 denote the same parts, and a detailed description thereof will be omitted.
First, as described in FIGS. 1A to 1D of the above-described embodiment, the metal pattern 10 is formed on the seed layer 103.
5a and 105b are formed (FIG. 6
(A)).

Next, in this embodiment, the seed layer 103 is not etched at this stage, and a resist having a hole 601a in a predetermined region is formed by a known photolithography technique as shown in FIG. A pattern 601 is formed. The resist pattern 601 is formed of the metal pattern 10
It is formed so that the film thickness on 5a is about 1 μm. Next, as shown in FIG. 6C, a columnar connecting portion 159 made of a copper plating film is formed on the metal pattern 105a exposed at the bottom of the hole 601a to a thickness of about 0.5 μm by electrolytic plating. Formed.

Thereafter, the resist pattern 601 is removed to expose the seed layer 103, and the seed layer 10 is exposed using the metal patterns 105a and 105b as masks.
3 is removed by etching to form a state in which the lower wiring layer 105 is formed on the interlayer insulating film 102 and the connection portion 159 is formed at a predetermined position thereon as shown in FIG. 6D. Note that the seed layer may be etched in the same manner as in the above-described embodiment. At this time, the connecting portion 1
An anti-participation film such as a silicon nitride film is formed on the surface of 59.

Next, as described in the above embodiment, the photosensitive resin film 701 is formed by the STP method. In the formation of a thin film by the STP method, a flattened state can be obtained by applying heat and pressure without being significantly affected by the unevenness of the lower layer. Therefore, even if there is a complicated step shape due to the lower wiring layer 105 and the connection portion 159, as shown in FIG. 7A, the photosensitive resin film 701 can be formed in a flat state.

After that, the entire area of the photosensitive resin film 701 is exposed to light so as to be soluble in a developing solution.
9 is in an exposed state. In addition, the photosensitive resin film 701 is thermally cured by performing a heat treatment at 350 ° C., and an insulating film 156 is formed as shown in FIG. 7B, and the upper surface of the insulating film 156 and the upper surface of the connecting portion 159 , And substantially the same plane is formed.

In this case, also on the surface of the connecting portion 159,
Since the silicon nitride film is formed, the exposed surface (the upper surface of the connection portion 159) is removed by a wet process using HF or a dry etching process. Thereafter, the upper wiring layer 113 is formed on the insulating film 156 in the same manner as in the above-described embodiment.
An insulating material is deposited on the insulating film 156 including 13 by a plasma CVD method, and a protective film 114 is formed as shown in FIG.

As described above, also in the present embodiment, a multilayer wiring structure can be formed more easily than before. According to the present embodiment,
The number of steps can be reduced as compared with the embodiment described above. Also in this embodiment, it is needless to say that more multilayer wiring structures of three or more wiring layers can be obtained. Further, the wiring material is not limited to copper, and another conductive material may be used.

[0035]

As described above, according to the present invention,
In the state where the connection portion is formed in advance, the insulating film for separating the layers is formed flat together with the lower wiring layer formed earlier, so that the multilayer wiring structure can be formed more easily. An excellent effect is obtained.

[Brief description of the drawings]

FIG. 1 is a process chart for explaining a multilayer wiring forming method according to an embodiment of the present invention.

FIG. 2 is a process drawing following FIG. 1 for explaining a multilayer wiring forming method.

FIG. 3 is a process drawing following FIG. 2 for explaining a multilayer wiring forming method;

FIG. 4 is a process drawing following FIG. 3 for explaining a multilayer wiring forming method;

FIG. 5 is a process drawing following FIG. 4 for explaining a multilayer wiring forming method;

FIG. 6 is a process chart for explaining a multilayer wiring forming method according to another embodiment of the present invention.

FIG. 7 is a process drawing following FIG. 6 for explaining the multilayer wiring forming method.

FIG. 8 is a process drawing illustrating the method of forming the multilayer wiring, following FIG. 7;

FIG. 9 is a process diagram illustrating a damascene method, which is one of the conventional multilayer wiring forming methods.

[Explanation of symbols]

101: substrate, 102: interlayer insulating film, 103: seed layer, 104: resist pattern, 104a, 104b ...
Opening area, 105 ... Lower wiring layer, 105a, 105b ...
Metal pattern 106 insulating film 107 seed layer 1
08 ... resist pattern, 108a ... hole, 109 ...
Connection portion, 109a: metal pattern (second metal pattern), 110: insulating film (second insulating film), 111: seed layer, 112: resist pattern, 112a: open region, 113: upper wiring layer, 113a ... Metal pattern, 1
14: protective film, 201: photosensitive resin film (first resin film), 202: sheet film (transfer base material), 301 ...
Photosensitive resin film (second resin film).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jin Ishii 2-3-1 Otemachi, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Inventor Bira Kuraki 2-chome Otemachi, Chiyoda-ku, Tokyo No. 1 Nippon Telegraph and Telephone Corporation F-term (reference)

Claims (6)

[Claims] A step of forming an interlayer insulating film on the semiconductor substrate; a step of forming a first metal film on the interlayer insulating film; and a groove extending in a predetermined direction on the first metal film. Forming a first mask pattern having a plurality of opening regions having a plurality of shapes; and forming a plurality of first metal patterns by plating on a surface of the first metal film exposed at the bottom of the opening region of the first mask pattern. Forming the first metal pattern and, after removing the first mask pattern, etching away the first metal film using the first metal pattern as a mask, thereby removing the first metal film and the first metal pattern. Forming a lower wiring layer comprising a plurality of electrode wirings, comprising: forming a first resin film having photosensitivity on the interlayer insulating film so as to absorb unevenness of the lower wiring layer and to be in a flat state; Forming step; and the resin The first resin film is removed by a predetermined amount by developing the film, and is thermally cured to form a first insulating film.
Exposing the upper surface of the lower wiring layer so that the upper surface of the first insulating film and the upper surface of the lower wiring layer form substantially the same plane; and forming a second surface on the first insulating film. Forming a metal film; and forming the second metal film in a region on any one of the first metal patterns.
Forming a second mask pattern having a hole in a predetermined region on the metal film, and forming a second pillar pattern by plating on the surface of the second metal film exposed at the bottom of the hole of the second mask pattern. Forming a second metal pattern, and after removing the second mask pattern, etching away the second metal film using the second metal pattern as a mask to form the second metal film and the second metal pattern. Forming a connection portion made of a second metal pattern; and forming a photosensitive second resin film on the first insulating film so as to absorb unevenness of the connection portion and to be in a flat state. And removing a predetermined amount of the second resin film by developing the resin film and thermally curing the second resin film to form a second insulating film.
A step in which the upper surface of the connection portion is exposed, and the upper surface of the second insulating film and the upper surface of the connection portion form substantially the same plane; Forming an upper wiring layer composed of a plurality of electrode wirings connected to the connection portion. 2. The method for forming a multilayer wiring according to claim 1, wherein the first and second resin films are removed after the entire area is exposed and then the development is performed. . 3. The method according to claim 1, wherein the removing of the first resin film is performed after the lower wiring layer is exposed, and the developing is performed. The method of forming a multilayer wiring according to claim 1, wherein the removing is performed after exposing the connection portion to light. 4. A step of forming an interlayer insulating film on the semiconductor substrate, a step of forming a first metal film on the interlayer insulating film, and a groove extending in a predetermined direction on the first metal film. Forming a first mask pattern having a plurality of opening regions having a plurality of shapes; and forming a plurality of first metal patterns by plating on a surface of the first metal film exposed at the bottom of the opening region of the first mask pattern. Forming the first metal pattern and, after removing the first mask pattern, etching away the first metal film using the first metal pattern as a mask, thereby removing the first metal film and the first metal pattern. Forming a lower wiring layer composed of a plurality of electrode wirings comprising: forming a second mask pattern having holes in a region above any one of the first metal patterns; and forming the second mask. Pattern e Forming a connection portion made of a columnar metal pattern on the first metal pattern exposed at the bottom of the metal layer by plating, and removing the second mask pattern, and then forming a photosensitive resin film on the first metal pattern. A step of forming a flat state on the interlayer insulating film by absorbing irregularities of the lower wiring layer and the connecting portion; removing a predetermined amount of the resin film by developing the resin film; By curing to form an insulating film, the upper surface of the connection portion is exposed, the upper surface of the insulating film and the upper surface of the connection portion are substantially in the same plane, a step of forming on the insulating film, Forming an upper wiring layer composed of a plurality of electrode wirings partly connected to the connection portion. 5. The method for forming a multilayer wiring according to claim 4, wherein the removal of the resin film is performed after the lower wiring layer and the connection portion are exposed to light. Multi-layer wiring formation method. 6. The multilayer wiring forming method according to claim 1, wherein a transfer base material is prepared, and the resin film is formed on the transfer base material, and the lower wiring layer of the semiconductor substrate is provided. The formation surface and the resin film formation surface of the transfer base material are brought into contact with each other, and heated to a predetermined temperature and pressed with a predetermined force to absorb irregularities caused by the lower wiring layer. A method of forming a multilayer wiring, wherein the resin film is formed on the semiconductor substrate by cooling the substrate to a predetermined temperature or less and then separating the transfer substrate from the semiconductor substrate.