KR100368090B1 - Contact hole formation method of nonsensitive polyimide resin insulation layer - Google Patents
Contact hole formation method of nonsensitive polyimide resin insulation layer Download PDFInfo
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- KR100368090B1 KR100368090B1 KR1019950030043A KR19950030043A KR100368090B1 KR 100368090 B1 KR100368090 B1 KR 100368090B1 KR 1019950030043 A KR1019950030043 A KR 1019950030043A KR 19950030043 A KR19950030043 A KR 19950030043A KR 100368090 B1 KR100368090 B1 KR 100368090B1
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- polyimide resin
- contact hole
- nonsensitive
- insulation layer
- resin insulation
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- 229920001721 polyimide Polymers 0.000 title claims abstract description 38
- 239000009719 polyimide resin Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000009413 insulation Methods 0.000 title abstract description 7
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 238000001312 dry etching Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 20
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 18
- 239000011229 interlayer Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 is deposited Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 비감광성 폴리이미드 수지 절연막의 콘택홀 형성 방법 관한 것으로서 보다 상세하게는 다층 배선 구조의 층간 절연막으로 비감광성 폴리이미드 수지(Nonsensitive Polyimide Resin)를 사용한 반도체 장치의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a non-photosensitive polyimide resin insulating film, and more particularly, to a method for forming a contact hole in a semiconductor device using a non-sensitive polyimide resin as an interlayer insulating film having a multilayer wiring structure.
종래 다층 배선구조의 층간 절연막으로 비감광성 폴리이미드 수지를 사용한반도체 장치의 제 1 도에 도시된 바와 같은 공정 순서에 의해 상,하층 금속배선을 연기시키기 위한 콘택홀을 형성하였다.A contact hole for postponing upper and lower metal wirings was formed by a process sequence as shown in FIG. 1 of a semiconductor device using a non-photosensitive polyimide resin as an interlayer insulating film of a conventional multilayer wiring structure.
즉, 비감광성 폴리이미드 수지의 콘택흘 형성 방법은 비감광성 폴리이미드 수지 절연층(40) 상에 감광막(50) 패턴을 형성하는 단계; 상기 감광막(60) 패턴을 마스크로 하여 절연층(40)을 부분적으로 습식식각하고, 하부 메탈(20)이 노출될 때가지 건식식각을 수행하는 단계; 및 감광막을 제거하는 단계로 구성되어 있다.That is, the contact flow forming method of the non-photosensitive polyimide resin may include forming a photosensitive film 50 pattern on the non-photosensitive polyimide resin insulating layer 40; Partially wet etching the insulating layer 40 using the photoresist layer 60 as a mask, and performing dry etching until the lower metal 20 is exposed; And removing the photosensitive film.
그러나 비감광성 폴리이미드 수지를 다층 배선 구조를 갖는 반도체장치의 충간 절연막으로 사용하는 경우, 폴리이미드 수지의 높은 점도 특성과 공정조건상 요구되는 높은 절연막 두께로 인하여 콘택홀 패턴을 확보하는데 어려움이 뒤따랐다.However, when the non-photosensitive polyimide resin is used as an interlayer insulating film of a semiconductor device having a multi-layered wiring structure, it has been difficult to secure a contact hole pattern due to the high viscosity characteristic of the polyimide resin and the high insulating film thickness required for process conditions.
구체적으로 폴리이미드 수지 절연층(40)의 두께가 두꺼워 비감광성 폴리이미드 수지의 반응에 의한 과다한 언더컷(Undercut)현상이 발생하고 콘택홀이 너무 경사지게 형성되어 상층 금속 배선의 끊김 불량이 발생되는 등 문제점이 노출되고 있다.Specifically, the thickness of the polyimide resin insulating layer 40 is too thick, resulting in excessive undercut due to the reaction of the non-photosensitive polyimide resin, and the contact hole is formed to be inclined too much to cause breakage of the upper metal wiring. This is being exposed.
따라서 본 발명은 이러한 종래 기술의 문제점을 해결하고자 한 것으로 그 목적은 비감광성 폴리이미드 수지를 이용하여 다층 배선 구조의 절연막을 구성함에 있어 비감광성 폴리이미드 수지와 양성 감광막의 반응 특성을 이용한 타임방식의 습식 식각과 산소 플라즈마 방식의 건식 식각을 이용한 다층 배선구조 형성시 층간절연막으로 사용되는 비감광성 폴리이미드의 콘택홀 패턴 및 경사 구조의 개선함으로써 상측 금속배선의 끊김 불량이 발생하지 않도록 한 비감광성 폴리이미드 수지 절연막의 콘택홀 형성방법을 제공하는데 있는 것이다.Accordingly, the present invention has been made to solve the problems of the prior art, and its object is to provide a time-based method using the reaction characteristics of the non-photosensitive polyimide resin and the positive photosensitive film in forming an insulating film having a multilayer wiring structure using the non-photosensitive polyimide resin. Non-photosensitive polyimide that prevents breakage of upper metal wiring by improving contact hole pattern and inclined structure of non-photosensitive polyimide used as interlayer insulating film when forming multi-layer wiring structure using wet etching and dry etching of oxygen plasma method The present invention provides a method for forming a contact hole in a resin insulating film.
상기 본 발명의 목적을 달성하기 위한 비감광성 폴리이미드 수지 절연막의 콘택홀 형성방법은, 반도체 장치에서 비감광성 폴리이미드 수지를 절연층으로 하고 이를 습식식각과 건식식각을 통해 콘택홀을 형성하는 데 있어서, 상기 비감광성 폴리이미드 수지 절연층 상에 양성 감광막패턴을 형성한 후 이를 마스크로 하여 상기 비감광성 폴리이미드수지 절연층을 타임방식의 습식식각을 통해 식각하는 단계와; 상기 습식식각된 상기 비감광성 폴리이미드 수지 절연층을 하부의 배선이 노출될 때까지 산소플라즈마 방식의 건식식각을 통해 식각하는 단계와, 상기 양성 감광막패턴을 제거하는 단계로 이루어진다.The contact hole forming method of the non-photosensitive polyimide resin insulating film for achieving the object of the present invention, in the semiconductor device in the non-photosensitive polyimide resin as an insulating layer to form a contact hole through wet etching and dry etching Forming a positive photosensitive film pattern on the non-photosensitive polyimide resin insulating layer, and then etching the non-photosensitive polyimide resin insulating layer through a time-type wet etching method using the positive photosensitive film pattern as a mask; Etching the wet-etched non-photosensitive polyimide resin insulating layer through oxygen plasma dry etching until the lower wiring is exposed, and removing the positive photoresist pattern.
이하, 본 발명의 비감광성 폴리이미드 수지 절연막의 콘택홀 형성 방법을 첨부 도면을 참조하여 상세히 설명한다Hereinafter, a method for forming a contact hole in a non-photosensitive polyimide resin insulating film of the present invention will be described in detail with reference to the accompanying drawings.
제 2도는 본 발명에 따른 폴리이미드수지 절연막의 콘택홀 형성 공정도이다.2 is a process hole forming process of the polyimide resin insulating film according to the present invention.
도면에 도시된 바와 같이, 실리콘 기판(10)상에 질화막(20)을 도포 하층 금속 배선 재료인 메탈(30)을 증착, 그리고 폴리이미드 수지 절연층(40)을 순차적으로 적층한 반도체 장치의 구조에 있어서, 상부에 층착될 상층 금속 배선과 하층 금속 배선을 연결하기 위한 콘택홀을 형성하기 위해 먼저 최상층 절연층(40)상에 양성 감광막(50) 패턴을 형성한다. 그런 다음, 상기 감광막(50) 패턴을 마스크로 하여 하층 금속 배선인 메탈(30)이 노출되지 않는 범위와 과도한 언더컷을 방지할 수 있는 범위 내에서 절연층(40)을 습식식각 바람직하게는 타임방식의 습식 식각을 수행한다. 그리고, 절연층(40)의 습식 식각한 하부를 건식 식각, 바람직하게는 산소 플라즈마방식의 건식식각을 하층 금속 배선인 메탈(30)이 노출되도록 실시한다.As shown in the figure, a structure of a semiconductor device in which a nitride film 20 is coated on a silicon substrate 10, and a metal 30, which is a lower metal wiring material, is deposited, and a polyimide resin insulating layer 40 is sequentially stacked. The positive photosensitive film 50 pattern is first formed on the uppermost insulating layer 40 in order to form contact holes for connecting the upper metal wiring and the lower metal wiring to be deposited on the top. Then, using the photoresist layer 50 as a mask, the wet etching of the insulating layer 40 is preferably performed within a range in which the metal 30, which is a lower metal wiring, is not exposed, and a range in which excessive undercut is prevented. Perform a wet etch of The wet etched lower portion of the insulating layer 40 is subjected to dry etching, preferably dry etching using an oxygen plasma method so that the metal 30, which is a lower metal wiring, is exposed.
이때 사용되는 양성 감광막(50) 패턴은 통상적인 방법, 양성 감광액 도포, 노광, 현상 및 베이크 순으로 형성한다, 이때, 형성된 양성감광막 패턴은 웨이퍼와 집적 닿지 않기 때문에 본 공정에서 유리하고, 좋은 분해능 등으로 2㎛이하의 반도체소자 제조공정에는 유리하지만, 노출시간에 매우 민감하므로 과다 노출되면 상기 양성감광막 패턴보다 훨씬 언더컷이 크게 되기 때문에 상기 양성감광막 패턴의 사용으로 인한 손상을 타임 습식식각을 수행함으로써 방지할 수 있게 된다. 즉, 이때 수행되는 타임방식의 습식식각은 식각하고자 하는 절연층을 원하는 만큼 식각할 수 있도록 하는 시간을 미리 결정하여 이 시간동안만 식각되도록 하는데, 이는 상기 양성감광막 패턴의 사용으로 인한 언더컷이 크게 되는 것을 방지할 수 있어 상기 양성감광막 패턴과 타임방식의 습식식각은 서로 보완하는 역할을 수행하게 된다.At this time, the positive photosensitive film 50 pattern to be used is formed in the order of the conventional method, positive photosensitive liquid coating, exposure, development and baking. In this case, the formed positive photosensitive film pattern is advantageous in this process because it does not come in contact with the wafer and has good resolution. Although it is advantageous to the semiconductor device manufacturing process of less than 2㎛, because it is very sensitive to the exposure time, the undercut is much larger than the positive photoresist pattern when overexposed, thereby preventing damage caused by the use of the positive photoresist pattern by performing time wet etching You can do it. That is, the time-type wet etching performed at this time determines the time for allowing the insulating layer to be etched as much as desired to be etched only during this time, which results in a large undercut due to the use of the positive photoresist pattern. The positive photoresist pattern and the wet etching of the time method may complement each other.
또 이때 타임방식의 습식식각으로 식각한 일부의 콘택홀을 산소 플리즈마 건식식각을 수행하여 완료하게 된다. 이때, 사용되는 건식식각은 상기 양성 감광막패턴을 마스크로 식각을 수행하기 때문에 상기 양성감광막패턴의 손실을 최소화할 수 있어야 하며, 콘택홀 내부에 잔존할 수 있는 절연층(40)의 제거 효과가 우수해야 하기 때문에 상기 건식식각의 조건에 적절히 부합되는 산소 플라즈마 건식식각을 사용하게 된다.In this case, some of the contact holes etched by wet etching in a time method are completed by performing oxygen plasma dry etching. At this time, the dry etching used should be able to minimize the loss of the positive photoresist pattern because the etching is performed using the positive photoresist pattern as a mask, and the removal effect of the insulating layer 40 remaining in the contact hole is excellent. Since it is necessary to use the oxygen plasma dry etching that suits the conditions of the dry etching.
이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
이와 같은 본 발명에 따른 비감광성 폴리이미드 수지 절연층의 콘택홀 형성 방법은 비감광성 폴리이미드 수지의 반응 특성을 이용하여 부분적으로 타임방식의 습식식각을 수행하여 일정양의 언더컷 프로파일(Uudercut Profile)을 형성한 홀 그하부의 비감광성 폴리이미드 수지를 산소 플라즈마 방식의 건식식각을 수행하여 원하는 크기의 콘택홀을 형성시킬 수 있으며, 콘택홀의 형성시 적절한 타임방식의 습식식각으로 과도한 언더컷 현상이 방지되어 콘택홀의 경사도가 개선되는 바, 상층 금속배선 구성을 위한 메탁 증착 공정시 스텝 커버리지 불량이 발생하지 않게 되는 것이다.Such a method for forming a contact hole of a non-photosensitive polyimide resin insulating layer according to the present invention uses a reaction characteristic of a non-photosensitive polyimide resin to partially wet a time method to obtain a certain amount of undercut profile. The non-photosensitive polyimide resin below the formed hole may be subjected to dry etching in an oxygen plasma manner to form a contact hole of a desired size.At the time of forming the contact hole, excessive undercut phenomenon is prevented by wet etching of an appropriate time method. As the inclination of the hole is improved, a step coverage defect does not occur during the methane deposition process for forming the upper metallization.
이상에서 설명한 바와 같이 본 발명은 비감광성 폴리이미드 수지를 절연층으로 사용하여 다층 배선 구조의 소자를 제조할 시 층간 절연의 콘택홀 형성 및 경사도 개선에 따른 금속 배선 끊김 불량 개선으로 논리회로 및 모스 제품의 절연막 및 신뢰성 확보를 위한 비감광성 폴리이미드 수지 활용이 가능해 지는 것이다.As described above, the present invention provides a logic circuit and a MOS product by improving the contact loss of the interlayer insulation and the failure of the breakage of the metal wiring due to the improvement of the inclination when the device having the multilayer wiring structure is manufactured using the non-photosensitive polyimide resin as the insulating layer. It is possible to utilize non-photosensitive polyimide resin for insulating film and securing reliability.
제 1도는 종래 반도체 장치의 비감광성 폴리아미드 수지 절연막의 콘택홀 형성 공정도1 is a process chart of contact hole formation of a non-photosensitive polyamide resin insulating film of a conventional semiconductor device.
제 2도는 본 발명에 따른 비감광성 폴리이미드 수지 절연막의 콘택홀 형성공정도2 is a process chart for forming a contact hole of a non-photosensitive polyimide resin insulating film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명** Explanation of symbols for the main parts of the drawings *
10: 실리콘 기판 20: 질화막10 silicon substrate 20 nitride film
30: 매탈 40: 절연막30: metal 40: insulating film
50: 감광막50: photosensitive film
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950030043A KR100368090B1 (en) | 1995-09-14 | 1995-09-14 | Contact hole formation method of nonsensitive polyimide resin insulation layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950030043A KR100368090B1 (en) | 1995-09-14 | 1995-09-14 | Contact hole formation method of nonsensitive polyimide resin insulation layer |
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| Publication Number | Publication Date |
|---|---|
| KR970018098A KR970018098A (en) | 1997-04-30 |
| KR100368090B1 true KR100368090B1 (en) | 2003-03-26 |
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| KR1019950030043A KR100368090B1 (en) | 1995-09-14 | 1995-09-14 | Contact hole formation method of nonsensitive polyimide resin insulation layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| RU2645920C2 (en) * | 2016-06-24 | 2018-02-28 | федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") | Method for forming contact windows in the layer of the protective foundation of a high-voltage device |
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| KR100376976B1 (en) * | 2000-06-22 | 2003-03-26 | 주식회사 하이닉스반도체 | Method for forming metal line |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS61140150A (en) * | 1984-12-13 | 1986-06-27 | Toshiba Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS61140150A (en) * | 1984-12-13 | 1986-06-27 | Toshiba Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| RU2645920C2 (en) * | 2016-06-24 | 2018-02-28 | федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") | Method for forming contact windows in the layer of the protective foundation of a high-voltage device |
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| KR970018098A (en) | 1997-04-30 |
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